gpioirq(4) version 2
This update makes this driver more than just an example and allows for: o More than one pin to be attached to a gpioirq instance. That is, the mask parameter can be greater than 0x01 now. o A /dev/gpioirqN device that allows GPIO pin interrupts to be transported into userland. This is a device that can be opened for reading with a simple fixed output indicating the device unit, pin number and current pin state. This update was used as part of a physical intrusion detection system where multiple switches (i.e. window magnetic reed switches and etc.) are tied to a bunch of GPIO inputs with userland software that reacts to the pins changing state.
This commit is contained in:
brad
parent
96f512bb33
commit
77871fbede
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@ -1,4 +1,4 @@
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# LIST OF CHANGES FROM LAST RELEASE: <$Revision: 1.3015 $>
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# LIST OF CHANGES FROM LAST RELEASE: <$Revision: 1.3016 $>
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#
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#
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# [Note: This file does not mention every change made to the NetBSD source tree.
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@ -258,3 +258,6 @@ Changes from NetBSD 10.0 to NetBSD 11.0:
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machines. [tsutsui 20231104]
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ena(4): MP-enable always, add RSS support, and reliability fixes.
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[jdolecek 20231105]
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gpioirq(4): allow multiple pins per gpioirq instance, add the ability
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to use a /dev/gpioirqN device to get pin interrupts into userland.
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[brad 20231105]
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@ -1,5 +1,5 @@
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#!/bin/sh -
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# $NetBSD: MAKEDEV.tmpl,v 1.233 2022/12/28 19:23:02 jakllsch Exp $
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# $NetBSD: MAKEDEV.tmpl,v 1.234 2023/11/06 00:35:05 brad Exp $
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#
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# Copyright (c) 2003,2007,2008 The NetBSD Foundation, Inc.
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# All rights reserved.
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@ -232,6 +232,7 @@
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# dtv* Digital TV interface
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# fb* PMAX generic framebuffer pseudo-device
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# fd file descriptors
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# gpioirq* Interrupts on GPIO pins
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# gpiopps* 1PPS signals on GPIO pins
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# grf* graphics frame buffer device
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# hdaudio* High Definition audio control device
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@ -830,7 +831,7 @@ all)
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makedev srt0 srt1 srt2 srt3
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makedev tap tap0 tap1 tap2 tap3
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makedev gpio gpio0 gpio1 gpio2 gpio3 gpio4 gpio5 gpio6 gpio7
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makedev gpiopps0
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makedev gpioirq0 gpiopps0
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makedev pad pad0 pad1 pad2 pad3
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makedev bthub
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makedev putter
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@ -873,6 +874,10 @@ gpio)
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lndev gpio0 gpio
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;;
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gpioirq)
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makedev gpioirq0
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;;
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gpiopps)
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makedev gpiopps0
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lndev gpiopps0 gpiopps
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@ -1547,6 +1552,11 @@ gpio[0-9]*)
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mkdev gpio$unit c %gpio_chr% $unit 664 $g_gpio
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;;
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gpioirq[0-9]*)
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unit=${i#gpioirq}
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mkdev gpioirq$unit c %gpioirq_chr% $unit 444 $g_gpio
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;;
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gpiopps[0-9]*)
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unit=${i#gpiopps}
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mkdev gpiopps$unit c %gpiopps_chr% $unit 664 $g_gpio
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@ -1,6 +1,6 @@
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.\" $NetBSD: gpioirq.4,v 1.3 2023/08/01 20:39:15 andvar Exp $
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.\" $NetBSD: gpioirq.4,v 1.4 2023/11/06 00:35:05 brad Exp $
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.\"
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.\" Copyright (c) 2016 Brad Spencer <brad@anduin.eldar.org>
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.\" Copyright (c) 2016, 2023 Brad Spencer <brad@anduin.eldar.org>
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.\"
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.\" Permission to use, copy, modify, and distribute this software for any
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.\" purpose with or without fee is hereby granted, provided that the above
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@ -14,25 +14,26 @@
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.\" ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
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.\" OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
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.\"
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.Dd May 11, 2018
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.Dd November 5, 2023
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.Dt GPIOIRQ 4
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.Os
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.Sh NAME
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.Nm gpioirq
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.Nd Install an interrupt handler on a GPIO pin
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.Nd Install an interrupt handler on GPIO pins
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.Sh SYNOPSIS
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.Cd "gpioirq* at gpio? offset 0 mask 0x1 flag 0x00"
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.Sh DESCRIPTION
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The
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.Nm
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driver attaches an interrupt handler to a single GPIO pin.
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driver attaches an interrupt handler to a one or more GPIO pins.
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.Pp
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The pin number is specified in the kernel configuration file with the
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The base pin number is specified in the kernel configuration file with the
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.Ar offset
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locator.
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The
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.Ar mask
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locator should always be 0x1.
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locator can be 0x01 or greater to indicate that more pins should have an
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interrupt handler attached to them.
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.Pp
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The
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.Ar flag
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@ -49,7 +50,7 @@ edge of the pin.
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.It Dv 0x04
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Interrupt on both edges of the pin.
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.It Dv 0x08
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Assert the interrupt as long as the pin is high.
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Assert the intrerrupt as long as the pin is high.
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.It Dv 0x10
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Assert the interrupt as long as the pin is low.
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.El
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@ -80,6 +81,36 @@ is attached at runtime using the
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on the
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.Xr gpio 4
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device.
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.Sh FILES
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.Bl -tag -width "/dev/gpioirqu" -compact
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.It /dev/gpioirq Ns Ar u
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GPIOIRQ device unit
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.Ar u
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file.
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The output from this device are three uint8_t bytes every time an interrupt fires.
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The bytes contain the device unit, pin number and the current state of the pin.
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.Sh EXAMPLES
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The following example will output the device unit, pin and
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the pins current state for pins 4, 5, 6, 7, 8, 9, 10, 11, 12 on gpio0:
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.Bd -literal -offset indent
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/etc/gpio.conf contains:
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gpio0 attach gpioirq 4 0x1ff 0x04
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or a kernel was compiled to have the same parameters.
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#!/usr/pkg/bin/perl
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$dev = "/dev/gpioirq0";
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sysopen(DEV,$dev,O_RDONLY) || die "sysopen: $!";
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while (sysread(DEV,$b,3)) {
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@v = unpack("CCC",$b);
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print join(',',@v);
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print "\\n";
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}
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.Sh SEE ALSO
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.Xr gpio 4 ,
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.Xr drvctl 8 ,
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@ -95,3 +126,22 @@ The
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.Nm
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driver was written by
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.An Brad Spencer Aq Mt brad@anduin.eldar.org .
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.Sh BUGS
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When an interrupt fires in most devices there is not any information carried
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along in the interrupt as to whether or not the pin is high or low. Hence the
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driver reads the current state of the pin after the interrupt has fired and it is
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possible that the state of the pin could have changed between the time the interrupt
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fired and the reading of the state. As a practical matter the only time the pin state
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will be reported wrong is if there is a very large number of interrupts happening. The
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driver could have made some assumptions if the interrupt was only for a rising edge or falling
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edge as in those cases it would be possible to know what the pin state would have been, but
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in the case of the double edge, there really will not be any way to be sure with most hardware
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and, in any case, the
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.Xr gpio 4
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infrastructure does not support getting at that information even if it did exist.
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.Pp
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It is important that if the
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.Xr gpioirq 4
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device is opened that it be read, as it may be possible
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to run the kernel out of memory if the device is opened but not read and interrupts
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occur on a pin tied to the driver.
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@ -1,4 +1,4 @@
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# $NetBSD: majors,v 1.102 2022/08/12 11:15:42 riastradh Exp $
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# $NetBSD: majors,v 1.103 2023/11/06 00:35:05 brad Exp $
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#
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# Device majors for Machine-Independent drivers.
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#
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@ -96,3 +96,4 @@ device-major efi char 361 efi
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device-major sht3xtemp char 362 sht3xtemp
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device-major scmd char 363 scmd
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device-major viocon char 364 viocon
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device-major gpioirq char 365 gpioirq
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@ -1,4 +1,4 @@
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/* $NetBSD: gpio.c,v 1.72 2022/12/13 21:50:43 jakllsch Exp $ */
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/* $NetBSD: gpio.c,v 1.73 2023/11/06 00:35:05 brad Exp $ */
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/* $OpenBSD: gpio.c,v 1.6 2006/01/14 12:33:49 grange Exp $ */
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/*
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@ -23,7 +23,7 @@
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#endif
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#include <sys/cdefs.h>
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__KERNEL_RCSID(0, "$NetBSD: gpio.c,v 1.72 2022/12/13 21:50:43 jakllsch Exp $");
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__KERNEL_RCSID(0, "$NetBSD: gpio.c,v 1.73 2023/11/06 00:35:05 brad Exp $");
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/*
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* General Purpose Input/Output framework.
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@ -618,6 +618,14 @@ gpio_intr_str(void *gpio, struct gpio_pinmap *map, int pin, int irqmode,
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return (true);
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}
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int
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gpio_pin_to_pin_num(void *gpio, struct gpio_pinmap *map, int pin)
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{
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struct gpio_softc *sc = gpio;
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return sc->sc_pins[map->pm_map[pin]].pin_num;
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}
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int
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gpio_npins(uint32_t mask)
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{
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@ -1,7 +1,7 @@
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/* $NetBSD: gpioirq.c,v 1.1 2018/05/19 14:15:39 thorpej Exp $ */
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/* $NetBSD: gpioirq.c,v 1.2 2023/11/06 00:35:05 brad Exp $ */
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/*
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* Copyright (c) 2016 Brad Spencer <brad@anduin.eldar.org>
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* Copyright (c) 2016, 2023 Brad Spencer <brad@anduin.eldar.org>
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*
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* Permission to use, copy, modify, and distribute this software for any
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* purpose with or without fee is hereby granted, provided that the above
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@ -17,32 +17,64 @@
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*/
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#include <sys/cdefs.h>
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__KERNEL_RCSID(0, "$NetBSD: gpioirq.c,v 1.1 2018/05/19 14:15:39 thorpej Exp $");
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__KERNEL_RCSID(0, "$NetBSD: gpioirq.c,v 1.2 2023/11/06 00:35:05 brad Exp $");
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/*
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* Example GPIO driver that uses interrupts.
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* GPIO driver that uses interrupts and can send that fact to userland.
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*/
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#include <sys/param.h>
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#include <sys/systm.h>
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#include <sys/device.h>
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#include <sys/device_impl.h>
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#include <sys/gpio.h>
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#include <sys/module.h>
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#include <sys/conf.h>
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#include <sys/proc.h>
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#include <sys/pool.h>
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#include <sys/kmem.h>
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#include <sys/condvar.h>
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#include <dev/gpio/gpiovar.h>
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#define GPIOIRQ_NPINS 1
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#define GPIOIRQ_NPINS 64
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struct gpioirq_iv {
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char sc_intrstr[128];
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void * sc_ih;
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int i_thispin_index;
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uint8_t i_thispin_num;
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uint8_t i_parentunit;
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struct gpioirq_softc *sc;
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};
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struct gpioirq_softc {
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device_t sc_dev;
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device_t sc_parentdev;
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void * sc_gpio;
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struct gpio_pinmap sc_map;
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int _map[GPIOIRQ_NPINS];
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char sc_intrstr[128];
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void * sc_ih;
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struct gpioirq_iv sc_intrs[GPIOIRQ_NPINS];
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int sc_npins;
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kmutex_t sc_lock;
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kmutex_t sc_read_mutex;
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kmutex_t sc_dying_mutex;
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bool sc_verbose;
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bool sc_functional;
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bool sc_opened;
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bool sc_dying;
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kcondvar_t sc_condreadready;
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kcondvar_t sc_cond_dying;
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pool_cache_t sc_readpool;
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char *sc_readpoolname;
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SIMPLEQ_HEAD(,gpioirq_read_q) sc_read_queue;
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};
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struct gpioirq_read_q {
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int parentunit;
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int thepin;
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int theval;
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SIMPLEQ_ENTRY(gpioirq_read_q) read_q;
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};
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#define GPIOIRQ_FLAGS_IRQMODE GPIO_INTR_MODE_MASK
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@ -52,8 +84,9 @@ static int gpioirq_match(device_t, cfdata_t, void *);
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static void gpioirq_attach(device_t, device_t, void *);
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static int gpioirq_detach(device_t, int);
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static int gpioirq_activate(device_t, enum devact);
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static int gpioirq_intr(void *);
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static uint8_t gpioirq_index_to_pin_num(struct gpioirq_softc *, int);
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static uint8_t gpioirq_parent_unit(struct gpioirq_softc *);
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CFATTACH_DECL_NEW(gpioirq, sizeof(struct gpioirq_softc),
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gpioirq_match, gpioirq_attach,
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@ -61,20 +94,47 @@ CFATTACH_DECL_NEW(gpioirq, sizeof(struct gpioirq_softc),
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extern struct cfdriver gpioirq_cd;
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static dev_type_open(gpioirq_open);
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static dev_type_read(gpioirq_read);
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static dev_type_close(gpioirq_close);
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const struct cdevsw gpioirq_cdevsw = {
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.d_open = gpioirq_open,
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.d_close = gpioirq_close,
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.d_read = gpioirq_read,
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.d_write = nowrite,
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.d_ioctl = noioctl,
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.d_stop = nostop,
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.d_tty = notty,
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.d_poll = nopoll,
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.d_mmap = nommap,
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.d_kqfilter = nokqfilter,
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.d_discard = nodiscard,
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.d_flag = D_OTHER
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};
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static uint8_t
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gpioirq_index_to_pin_num(struct gpioirq_softc *sc, int index)
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{
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return (uint8_t)gpio_pin_to_pin_num(sc->sc_gpio, &sc->sc_map, index);
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}
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static uint8_t
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gpioirq_parent_unit(struct gpioirq_softc *sc)
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{
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device_t parent = sc->sc_parentdev;
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return (uint8_t)parent->dv_unit;
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}
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static int
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gpioirq_match(device_t parent, cfdata_t cf, void *aux)
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{
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struct gpio_attach_args *ga = aux;
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int npins;
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if (strcmp(ga->ga_dvname, cf->cf_name))
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return (0);
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if (ga->ga_offset == -1)
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return (0);
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npins = gpio_npins(ga->ga_mask);
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if (npins > 1)
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if (ga->ga_offset == -1)
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return (0);
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return (1);
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@ -85,18 +145,30 @@ gpioirq_attach(device_t parent, device_t self, void *aux)
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{
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struct gpioirq_softc *sc = device_private(self);
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struct gpio_attach_args *ga = aux;
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int npins = gpio_npins(ga->ga_mask);
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int mask = ga->ga_mask;
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int irqmode, flags;
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sc->sc_dev = self;
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sc->sc_parentdev = parent;
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sc->sc_opened = false;
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sc->sc_dying = false;
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sc->sc_readpoolname = NULL;
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/* Map pins */
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sc->sc_gpio = ga->ga_gpio;
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sc->sc_map.pm_map = sc->_map;
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/* We always map just 1 pin. */
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/* Determine our pin configuation. */
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sc->sc_npins = gpio_npins(mask);
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if (sc->sc_npins == 0) {
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sc->sc_npins = 1;
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mask = 0x1;
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}
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/* XXX - exit if more than allowed number of pins */
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if (gpio_pin_map(sc->sc_gpio, ga->ga_offset,
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npins ? ga->ga_mask : 0x1, &sc->sc_map)) {
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mask, &sc->sc_map)) {
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aprint_error(": can't map pins\n");
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return;
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}
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@ -109,40 +181,58 @@ gpioirq_attach(device_t parent, device_t self, void *aux)
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irqmode = ga->ga_flags & GPIOIRQ_FLAGS_IRQMODE;
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mutex_init(&sc->sc_lock, MUTEX_DEFAULT, IPL_VM);
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mutex_init(&sc->sc_dying_mutex, MUTEX_DEFAULT, IPL_VM);
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mutex_init(&sc->sc_read_mutex, MUTEX_DEFAULT, IPL_VM);
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cv_init(&sc->sc_cond_dying, "girqdie");
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cv_init(&sc->sc_condreadready,"girqrr");
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sc->sc_readpoolname = kmem_asprintf("girqread%d",device_unit(self));
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sc->sc_readpool = pool_cache_init(sizeof(struct gpioirq_read_q),0,0,0,sc->sc_readpoolname,NULL,IPL_VM,NULL,NULL,NULL);
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pool_cache_sethiwat(sc->sc_readpool,100);
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SIMPLEQ_INIT(&sc->sc_read_queue);
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if (!gpio_intr_str(sc->sc_gpio, &sc->sc_map, 0, irqmode,
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sc->sc_intrstr, sizeof(sc->sc_intrstr))) {
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aprint_error_dev(self, "failed to decode interrupt\n");
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return;
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}
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for(int apin = 0; apin < sc->sc_npins; apin++) {
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if (!gpio_intr_str(sc->sc_gpio, &sc->sc_map, apin, irqmode,
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sc->sc_intrs[apin].sc_intrstr, sizeof(sc->sc_intrs[apin].sc_intrstr))) {
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aprint_error_dev(self, "failed to decode interrupt\n");
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return;
|
||||
}
|
||||
|
||||
if (!gpio_pin_irqmode_issupported(sc->sc_gpio, &sc->sc_map, 0,
|
||||
irqmode)) {
|
||||
aprint_error_dev(self,
|
||||
"irqmode not supported: %s\n", sc->sc_intrstr);
|
||||
gpio_pin_unmap(sc->sc_gpio, &sc->sc_map);
|
||||
return;
|
||||
}
|
||||
if (!gpio_pin_irqmode_issupported(sc->sc_gpio, &sc->sc_map, apin,
|
||||
irqmode)) {
|
||||
aprint_error_dev(self,
|
||||
"irqmode not supported: %s\n", sc->sc_intrs[apin].sc_intrstr);
|
||||
gpio_pin_unmap(sc->sc_gpio, &sc->sc_map);
|
||||
return;
|
||||
}
|
||||
|
||||
flags = gpio_pin_get_conf(sc->sc_gpio, &sc->sc_map, 0);
|
||||
flags = (flags & ~(GPIO_PIN_OUTPUT|GPIO_PIN_INOUT)) |
|
||||
GPIO_PIN_INPUT;
|
||||
if (!gpio_pin_set_conf(sc->sc_gpio, &sc->sc_map, 0, flags)) {
|
||||
aprint_error_dev(sc->sc_dev, "pin not capable of input\n");
|
||||
gpio_pin_unmap(sc->sc_gpio, &sc->sc_map);
|
||||
return;
|
||||
}
|
||||
flags = gpio_pin_get_conf(sc->sc_gpio, &sc->sc_map, apin);
|
||||
flags = (flags & ~(GPIO_PIN_OUTPUT|GPIO_PIN_INOUT)) |
|
||||
GPIO_PIN_INPUT;
|
||||
if (!gpio_pin_set_conf(sc->sc_gpio, &sc->sc_map, apin, flags)) {
|
||||
aprint_error_dev(sc->sc_dev, "pin not capable of input\n");
|
||||
gpio_pin_unmap(sc->sc_gpio, &sc->sc_map);
|
||||
return;
|
||||
}
|
||||
|
||||
sc->sc_ih = gpio_intr_establish(sc->sc_gpio, &sc->sc_map, 0, IPL_VM,
|
||||
irqmode | GPIO_INTR_MPSAFE,
|
||||
gpioirq_intr, sc);
|
||||
if (sc->sc_ih == NULL) {
|
||||
aprint_error_dev(self,
|
||||
"unable to establish interrupt on %s\n", sc->sc_intrstr);
|
||||
gpio_pin_unmap(sc->sc_gpio, &sc->sc_map);
|
||||
return;
|
||||
/* These are static for each pin, so just stuff them in here,
|
||||
* so they don't need to be looked up again.
|
||||
*/
|
||||
sc->sc_intrs[apin].i_thispin_index = apin;
|
||||
sc->sc_intrs[apin].i_thispin_num = gpioirq_index_to_pin_num(sc,apin);
|
||||
sc->sc_intrs[apin].i_parentunit = gpioirq_parent_unit(sc);
|
||||
sc->sc_intrs[apin].sc = sc;
|
||||
|
||||
sc->sc_intrs[apin].sc_ih = gpio_intr_establish(sc->sc_gpio, &sc->sc_map, apin, IPL_VM,
|
||||
irqmode | GPIO_INTR_MPSAFE,
|
||||
gpioirq_intr, &sc->sc_intrs[apin]);
|
||||
if (sc->sc_intrs[apin].sc_ih == NULL) {
|
||||
aprint_error_dev(self,
|
||||
"unable to establish interrupt on %s\n", sc->sc_intrs[apin].sc_intrstr);
|
||||
gpio_pin_unmap(sc->sc_gpio, &sc->sc_map);
|
||||
return;
|
||||
}
|
||||
aprint_normal_dev(self, "interrupting on %s\n", sc->sc_intrs[apin].sc_intrstr);
|
||||
}
|
||||
aprint_normal_dev(self, "interrupting on %s\n", sc->sc_intrstr);
|
||||
|
||||
sc->sc_functional = true;
|
||||
}
|
||||
|
|
@ -150,33 +240,180 @@ gpioirq_attach(device_t parent, device_t self, void *aux)
|
|||
int
|
||||
gpioirq_intr(void *arg)
|
||||
{
|
||||
struct gpioirq_softc *sc = arg;
|
||||
struct gpioirq_iv *is = arg;
|
||||
struct gpioirq_softc *sc = is->sc;
|
||||
struct gpioirq_read_q *q;
|
||||
int val;
|
||||
|
||||
mutex_enter(&sc->sc_lock);
|
||||
|
||||
val = gpio_pin_read(sc->sc_gpio, &sc->sc_map, 0);
|
||||
val = gpio_pin_read(sc->sc_gpio, &sc->sc_map, is->i_thispin_index);
|
||||
|
||||
if (sc->sc_verbose)
|
||||
printf("%s: interrupt on %s --> %d\n",
|
||||
device_xname(sc->sc_dev), sc->sc_intrstr, val);
|
||||
device_xname(sc->sc_dev), sc->sc_intrs[is->i_thispin_index].sc_intrstr, val);
|
||||
|
||||
mutex_exit(&sc->sc_lock);
|
||||
|
||||
if (sc->sc_opened) {
|
||||
mutex_enter(&sc->sc_read_mutex);
|
||||
q = pool_cache_get(sc->sc_readpool,PR_NOWAIT);
|
||||
if (q != NULL) {
|
||||
q->thepin = is->i_thispin_num;
|
||||
q->parentunit = is->i_parentunit;
|
||||
q->theval = val;
|
||||
SIMPLEQ_INSERT_TAIL(&sc->sc_read_queue,q,read_q);
|
||||
cv_signal(&sc->sc_condreadready);
|
||||
} else {
|
||||
aprint_error("Could not allocate memory for read pool\n");
|
||||
}
|
||||
mutex_exit(&sc->sc_read_mutex);
|
||||
}
|
||||
|
||||
return (1);
|
||||
}
|
||||
|
||||
static int
|
||||
gpioirq_open(dev_t dev, int flags, int fmt, struct lwp *l)
|
||||
{
|
||||
struct gpioirq_softc *sc;
|
||||
|
||||
sc = device_lookup_private(&gpioirq_cd, minor(dev));
|
||||
if (!sc)
|
||||
return (ENXIO);
|
||||
|
||||
if (sc->sc_opened)
|
||||
return (EBUSY);
|
||||
|
||||
mutex_enter(&sc->sc_lock);
|
||||
sc->sc_opened = true;
|
||||
mutex_exit(&sc->sc_lock);
|
||||
|
||||
return (0);
|
||||
}
|
||||
|
||||
static int
|
||||
gpioirq_read(dev_t dev, struct uio *uio, int flags)
|
||||
{
|
||||
struct gpioirq_softc *sc;
|
||||
struct gpioirq_read_q *chp;
|
||||
int error = 0,any;
|
||||
uint8_t obuf[3];
|
||||
|
||||
sc = device_lookup_private(&gpioirq_cd, minor(dev));
|
||||
if (!sc)
|
||||
return (ENXIO);
|
||||
|
||||
while (uio->uio_resid > 0) {
|
||||
any = 0;
|
||||
error = 0;
|
||||
mutex_enter(&sc->sc_read_mutex);
|
||||
|
||||
while (any == 0) {
|
||||
chp = SIMPLEQ_FIRST(&sc->sc_read_queue);
|
||||
if (chp != NULL) {
|
||||
SIMPLEQ_REMOVE_HEAD(&sc->sc_read_queue, read_q);
|
||||
any = 1;
|
||||
break;
|
||||
} else {
|
||||
error = cv_wait_sig(&sc->sc_condreadready,&sc->sc_read_mutex);
|
||||
if (sc->sc_dying)
|
||||
error = EIO;
|
||||
if (error == 0)
|
||||
continue;
|
||||
break;
|
||||
}
|
||||
}
|
||||
|
||||
if (any == 1 && error == 0) {
|
||||
obuf[0] = (uint8_t)chp->parentunit;
|
||||
obuf[1] = (uint8_t)chp->thepin;
|
||||
obuf[2] = (uint8_t)chp->theval;
|
||||
pool_cache_put(sc->sc_readpool,chp);
|
||||
mutex_exit(&sc->sc_read_mutex);
|
||||
if ((error = uiomove(&obuf[0], 3, uio)) != 0) {
|
||||
break;
|
||||
}
|
||||
} else {
|
||||
mutex_exit(&sc->sc_read_mutex);
|
||||
if (error) {
|
||||
break;
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
if (sc->sc_dying) {
|
||||
mutex_enter(&sc->sc_dying_mutex);
|
||||
cv_signal(&sc->sc_cond_dying);
|
||||
mutex_exit(&sc->sc_dying_mutex);
|
||||
}
|
||||
return error;
|
||||
}
|
||||
|
||||
static int
|
||||
gpioirq_close(dev_t dev, int flags, int fmt, struct lwp *l)
|
||||
{
|
||||
struct gpioirq_softc *sc;
|
||||
struct gpioirq_read_q *q;
|
||||
|
||||
sc = device_lookup_private(&gpioirq_cd, minor(dev));
|
||||
|
||||
mutex_enter(&sc->sc_lock);
|
||||
while ((q = SIMPLEQ_FIRST(&sc->sc_read_queue)) != NULL) {
|
||||
SIMPLEQ_REMOVE_HEAD(&sc->sc_read_queue, read_q);
|
||||
pool_cache_put(sc->sc_readpool,q);
|
||||
}
|
||||
sc->sc_opened = false;
|
||||
mutex_exit(&sc->sc_lock);
|
||||
|
||||
return(0);
|
||||
}
|
||||
|
||||
int
|
||||
gpioirq_detach(device_t self, int flags)
|
||||
{
|
||||
struct gpioirq_softc *sc = device_private(self);
|
||||
struct gpioirq_read_q *q;
|
||||
|
||||
/* Clear the handler and disable the interrupt. */
|
||||
gpio_intr_disestablish(sc->sc_gpio, sc->sc_ih);
|
||||
for(int apin = 0;apin < sc->sc_npins;apin++) {
|
||||
gpio_intr_disestablish(sc->sc_gpio, sc->sc_intrs[apin].sc_ih);
|
||||
}
|
||||
|
||||
/* Release the pin. */
|
||||
gpio_pin_unmap(sc->sc_gpio, &sc->sc_map);
|
||||
|
||||
sc->sc_dying = true;
|
||||
|
||||
if (sc->sc_opened) {
|
||||
mutex_enter(&sc->sc_dying_mutex);
|
||||
mutex_enter(&sc->sc_read_mutex);
|
||||
cv_signal(&sc->sc_condreadready);
|
||||
mutex_exit(&sc->sc_read_mutex);
|
||||
/* In the worst case this will time out after 5 seconds.
|
||||
* It really should not take that long for the drain / whatever
|
||||
* to happen
|
||||
*/
|
||||
cv_timedwait_sig(&sc->sc_cond_dying,
|
||||
&sc->sc_dying_mutex, mstohz(5000));
|
||||
mutex_exit(&sc->sc_dying_mutex);
|
||||
cv_destroy(&sc->sc_condreadready);
|
||||
cv_destroy(&sc->sc_cond_dying);
|
||||
}
|
||||
|
||||
/* Drain any read pools */
|
||||
while ((q = SIMPLEQ_FIRST(&sc->sc_read_queue)) != NULL) {
|
||||
SIMPLEQ_REMOVE_HEAD(&sc->sc_read_queue, read_q);
|
||||
pool_cache_put(sc->sc_readpool,q);
|
||||
}
|
||||
|
||||
if (sc->sc_readpoolname != NULL) {
|
||||
kmem_free(sc->sc_readpoolname,strlen(sc->sc_readpoolname) + 1);
|
||||
}
|
||||
|
||||
mutex_destroy(&sc->sc_read_mutex);
|
||||
mutex_destroy(&sc->sc_lock);
|
||||
|
||||
return (0);
|
||||
}
|
||||
|
||||
|
|
@ -184,9 +421,11 @@ int
|
|||
gpioirq_activate(device_t self, enum devact act)
|
||||
{
|
||||
|
||||
struct gpioirq_softc *sc = device_private(self);
|
||||
|
||||
switch (act) {
|
||||
case DVACT_DEACTIVATE:
|
||||
/* We don't really need to do anything. */
|
||||
sc->sc_dying = true;
|
||||
return (0);
|
||||
default:
|
||||
return (EOPNOTSUPP);
|
||||
|
|
@ -203,26 +442,39 @@ static int
|
|||
gpioirq_modcmd(modcmd_t cmd, void *opaque)
|
||||
{
|
||||
int error = 0;
|
||||
#ifdef _MODULE
|
||||
int bmaj = -1, cmaj = -1;
|
||||
#endif
|
||||
|
||||
switch (cmd) {
|
||||
case MODULE_CMD_INIT:
|
||||
#ifdef _MODULE
|
||||
error = config_init_component(cfdriver_ioconf_gpioirq,
|
||||
cfattach_ioconf_gpioirq, cfdata_ioconf_gpioirq);
|
||||
if (error)
|
||||
if (error) {
|
||||
aprint_error("%s: unable to init component\n",
|
||||
gpioirq_cd.cd_name);
|
||||
return (error);
|
||||
}
|
||||
|
||||
error = devsw_attach("gpioirq", NULL, &bmaj,
|
||||
&gpioirq_cdevsw, &cmaj);
|
||||
if (error) {
|
||||
aprint_error("%s: unable to attach devsw\n",
|
||||
gpioirq_cd.cd_name);
|
||||
config_fini_component(cfdriver_ioconf_gpioirq,
|
||||
cfattach_ioconf_gpioirq, cfdata_ioconf_gpioirq);
|
||||
}
|
||||
#endif
|
||||
break;
|
||||
return (error);
|
||||
case MODULE_CMD_FINI:
|
||||
#ifdef _MODULE
|
||||
devsw_detach(NULL, &gpioirq_cdevsw);
|
||||
config_fini_component(cfdriver_ioconf_gpioirq,
|
||||
cfattach_ioconf_gpioirq, cfdata_ioconf_gpioirq);
|
||||
#endif
|
||||
break;
|
||||
return (0);
|
||||
default:
|
||||
error = ENOTTY;
|
||||
return (ENOTTY);
|
||||
}
|
||||
|
||||
return (error);
|
||||
}
|
||||
|
|
|
|||
|
|
@ -1,4 +1,4 @@
|
|||
/* $NetBSD: gpiovar.h,v 1.18 2018/05/19 13:59:06 thorpej Exp $ */
|
||||
/* $NetBSD: gpiovar.h,v 1.19 2023/11/06 00:35:05 brad Exp $ */
|
||||
/* $OpenBSD: gpiovar.h,v 1.3 2006/01/14 12:33:49 grange Exp $ */
|
||||
|
||||
/*
|
||||
|
|
@ -118,6 +118,7 @@ void * gpio_intr_establish(void *, struct gpio_pinmap *, int, int, int,
|
|||
void gpio_intr_disestablish(void *, void *);
|
||||
bool gpio_intr_str(void *, struct gpio_pinmap *, int, int,
|
||||
char *, size_t);
|
||||
int gpio_pin_to_pin_num(void *, struct gpio_pinmap *, int);
|
||||
|
||||
int gpio_lock(void *);
|
||||
void gpio_unlock(void *);
|
||||
|
|
|
|||
Loading…
Reference in New Issue