Add NS Geode PCI-ISA bridge GPIO support.
This commit is contained in:
jmcneill
parent
b77b366d41
commit
777503501e
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@ -1,4 +1,4 @@
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# $NetBSD: files.i386,v 1.270 2005/09/22 07:09:35 dyoung Exp $
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# $NetBSD: files.i386,v 1.271 2005/09/27 02:42:44 jmcneill Exp $
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#
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# new style config file for i386 architecture
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#
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@ -197,13 +197,17 @@ file arch/i386/pci/pceb.c pceb
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# PCI-ISA bridges
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device pcib: isabus
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attach pcib at pci
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file arch/i386/pci/pcib.c pcib | ichlpcib
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file arch/i386/pci/pcib.c pcib | ichlpcib | gscpcib
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# PCI-LPC bridges
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device ichlpcib: isabus, sysmon_wdog
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attach ichlpcib at pci
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file arch/i386/pci/ichlpcib.c ichlpcib
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device gscpcib: isabus, gpiobus
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attach gscpcib at pci
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file arch/i386/pci/gscpcib.c gscpcib
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# PCI-MCA bridges
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device pcmb: mcabus
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attach pcmb at pci
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@ -0,0 +1,202 @@
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/* $NetBSD: gscpcib.c,v 1.1 2005/09/27 02:42:44 jmcneill Exp $ */
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/* $OpenBSD: gscpcib.c,v 1.3 2004/10/05 19:02:33 grange Exp $ */
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/*
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* Copyright (c) 2004 Alexander Yurchenko <grange@openbsd.org>
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*
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* Permission to use, copy, modify, and distribute this software for any
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* purpose with or without fee is hereby granted, provided that the above
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* copyright notice and this permission notice appear in all copies.
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*
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* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
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* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
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* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
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* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
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* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
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* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
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* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
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*/
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/*
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* Special driver for the National Semiconductor Geode SC1100 PCI-ISA bridge
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* that attaches instead of pcib(4). In addition to the core pcib(4)
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* functionality this driver provides support for the GPIO interface.
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*/
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#include <sys/param.h>
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#include <sys/systm.h>
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#include <sys/device.h>
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#include <sys/gpio.h>
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#include <sys/kernel.h>
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#include <machine/bus.h>
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#include <dev/pci/pcireg.h>
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#include <dev/pci/pcivar.h>
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#include <dev/pci/pcidevs.h>
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#include <dev/gpio/gpiovar.h>
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#include <i386/pci/gscpcibreg.h>
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struct gscpcib_softc {
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struct device sc_dev;
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/* GPIO interface */
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bus_space_tag_t sc_gpio_iot;
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bus_space_handle_t sc_gpio_ioh;
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struct gpio_chipset_tag sc_gpio_gc;
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gpio_pin_t sc_gpio_pins[GSCGPIO_NPINS];
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};
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int gscpcib_match(struct device *, struct cfdata *, void *);
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void gscpcib_attach(struct device *, struct device *, void *);
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int gscpcib_gpio_pin_read(void *, int);
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void gscpcib_gpio_pin_write(void *, int, int);
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void gscpcib_gpio_pin_ctl(void *, int, int);
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/* arch/i386/pci/pcib.c */
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void pcibattach(struct device *, struct device *, void *);
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CFATTACH_DECL(gscpcib, sizeof(struct gscpcib_softc),
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gscpcib_match, gscpcib_attach, NULL, NULL);
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extern struct cfdriver gscpcib_cd;
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int
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gscpcib_match(struct device *parent, struct cfdata *match, void *aux)
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{
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struct pci_attach_args *pa = aux;
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if (PCI_CLASS(pa->pa_class) != PCI_CLASS_BRIDGE ||
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PCI_SUBCLASS(pa->pa_class) != PCI_SUBCLASS_BRIDGE_ISA)
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return (0);
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if (PCI_VENDOR(pa->pa_id) == PCI_VENDOR_NS &&
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PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_NS_SC1100_ISA)
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return (2); /* supersede pcib(4) */
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return (0);
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}
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void
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gscpcib_attach(struct device *parent, struct device *self, void *aux)
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{
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#ifndef SMALL_KERNEL
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struct gscpcib_softc *sc = (struct gscpcib_softc *)self;
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struct pci_attach_args *pa = aux;
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struct gpiobus_attach_args gba;
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pcireg_t gpiobase;
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int i;
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int gpio_present = 0;
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/* Map GPIO I/O space */
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gpiobase = pci_conf_read(pa->pa_pc, pa->pa_tag, GSCGPIO_BASE);
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sc->sc_gpio_iot = pa->pa_iot;
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if (bus_space_map(sc->sc_gpio_iot, PCI_MAPREG_IO_ADDR(gpiobase),
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GSCGPIO_SIZE, 0, &sc->sc_gpio_ioh)) {
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printf(": failed to map GPIO I/O space");
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goto corepcib;
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}
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/* Initialize pins array */
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for (i = 0; i < GSCGPIO_NPINS; i++) {
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sc->sc_gpio_pins[i].pin_num = i;
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sc->sc_gpio_pins[i].pin_caps = GPIO_PIN_INPUT |
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GPIO_PIN_OUTPUT | GPIO_PIN_OPENDRAIN |
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GPIO_PIN_PUSHPULL | GPIO_PIN_TRISTATE |
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GPIO_PIN_PULLUP;
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/* safe defaults */
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sc->sc_gpio_pins[i].pin_flags = GPIO_PIN_TRISTATE;
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sc->sc_gpio_pins[i].pin_state = GPIO_PIN_LOW;
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gscpcib_gpio_pin_ctl(sc, i, sc->sc_gpio_pins[i].pin_flags);
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gscpcib_gpio_pin_write(sc, i, sc->sc_gpio_pins[i].pin_state);
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}
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/* Create controller tag */
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sc->sc_gpio_gc.gp_cookie = sc;
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sc->sc_gpio_gc.gp_pin_read = gscpcib_gpio_pin_read;
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sc->sc_gpio_gc.gp_pin_write = gscpcib_gpio_pin_write;
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sc->sc_gpio_gc.gp_pin_ctl = gscpcib_gpio_pin_ctl;
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gba.gba_name = "gpio";
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gba.gba_gc = &sc->sc_gpio_gc;
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gba.gba_pins = sc->sc_gpio_pins;
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gba.gba_npins = GSCGPIO_NPINS;
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gpio_present = 1;
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corepcib:
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#endif /* !SMALL_KERNEL */
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/* Provide core pcib(4) functionality */
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pcibattach(parent, self, aux);
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#ifndef SMALL_KERNEL
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/* Attach GPIO framework */
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if (gpio_present)
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config_found(&sc->sc_dev, &gba, gpiobus_print);
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#endif /* !SMALL_KERNEL */
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}
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#ifndef SMALL_KERNEL
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static __inline void
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gscpcib_gpio_pin_select(struct gscpcib_softc *sc, int pin)
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{
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bus_space_write_4(sc->sc_gpio_iot, sc->sc_gpio_ioh, GSCGPIO_SEL, pin);
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}
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int
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gscpcib_gpio_pin_read(void *arg, int pin)
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{
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struct gscpcib_softc *sc = arg;
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int reg, shift;
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u_int32_t data;
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reg = (pin < 32 ? GSCGPIO_GPDI0 : GSCGPIO_GPDI1);
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shift = pin % 32;
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data = bus_space_read_4(sc->sc_gpio_iot, sc->sc_gpio_ioh, reg);
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return ((data >> shift) & 0x1);
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}
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void
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gscpcib_gpio_pin_write(void *arg, int pin, int value)
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{
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struct gscpcib_softc *sc = arg;
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int reg, shift;
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u_int32_t data;
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reg = (pin < 32 ? GSCGPIO_GPDO0 : GSCGPIO_GPDO1);
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shift = pin % 32;
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data = bus_space_read_4(sc->sc_gpio_iot, sc->sc_gpio_ioh, reg);
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if (value == 0)
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data &= ~(1 << shift);
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else if (value == 1)
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data |= (1 << shift);
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bus_space_write_4(sc->sc_gpio_iot, sc->sc_gpio_ioh, reg, data);
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}
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void
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gscpcib_gpio_pin_ctl(void *arg, int pin, int flags)
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{
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struct gscpcib_softc *sc = arg;
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u_int32_t conf;
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gscpcib_gpio_pin_select(sc, pin);
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conf = bus_space_read_4(sc->sc_gpio_iot, sc->sc_gpio_ioh,
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GSCGPIO_CONF);
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conf &= ~(GSCGPIO_CONF_OUTPUTEN | GSCGPIO_CONF_PUSHPULL |
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GSCGPIO_CONF_PULLUP);
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if ((flags & GPIO_PIN_TRISTATE) == 0)
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conf |= GSCGPIO_CONF_OUTPUTEN;
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if (flags & GPIO_PIN_PUSHPULL)
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conf |= GSCGPIO_CONF_PUSHPULL;
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if (flags & GPIO_PIN_PULLUP)
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conf |= GSCGPIO_CONF_PULLUP;
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bus_space_write_4(sc->sc_gpio_iot, sc->sc_gpio_ioh,
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GSCGPIO_CONF, conf);
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}
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#endif /* !SMALL_KERNEL */
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@ -0,0 +1,43 @@
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/* $NetBSD: gscpcibreg.h,v 1.1 2005/09/27 02:42:44 jmcneill Exp $ */
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/* $OpenBSD: gscpcibreg.h,v 1.1 2004/06/03 18:22:21 grange Exp $ */
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/*
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* Copyright (c) 2004 Alexander Yurchenko <grange@openbsd.org>
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*
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* Permission to use, copy, modify, and distribute this software for any
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* purpose with or without fee is hereby granted, provided that the above
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* copyright notice and this permission notice appear in all copies.
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*
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* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
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* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
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* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
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* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
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* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
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* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
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* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
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*/
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#ifndef _I386_PCI_GSCGPIOREG_H_
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#define _I386_PCI_GSCGPIOREG_H_
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#define GSCGPIO_NPINS 64
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#define GSCGPIO_BASE 0x10
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#define GSCGPIO_SIZE 64
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#define GSCGPIO_GPDO0 0x00
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#define GSCGPIO_GPDI0 0x04
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#define GSCGPIO_GPIEN0 0x08
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#define GSCGPIO_GPST0 0x0c
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#define GSCGPIO_GPDO1 0x10
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#define GSCGPIO_GPDI1 0x14
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#define GSCGPIO_GPIEN1 0x18
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#define GSCGPIO_GPST1 0x1c
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#define GSCGPIO_SEL 0x20
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#define GSCGPIO_CONF 0x24
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#define GSCGPIO_RESET 0x28
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#define GSCGPIO_CONF_OUTPUTEN (1 << 0)
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#define GSCGPIO_CONF_PUSHPULL (1 << 1)
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#define GSCGPIO_CONF_PULLUP (1 << 2)
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#endif /* !_I386_PCI_GSCGPIOREG_H_ */
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