From 77666e6c725c9c9b997becafbc61cfd657580cff Mon Sep 17 00:00:00 2001 From: matt Date: Wed, 9 May 2001 15:58:07 +0000 Subject: [PATCH] Populate dnard/dnard. --- sys/arch/dnard/dnard/autoconf.c | 334 ++ sys/arch/dnard/dnard/conf.c | 417 ++ sys/arch/dnard/dnard/db_ofw_machdep.c | 74 + sys/arch/dnard/dnard/dnard_machdep.c | 364 ++ sys/arch/dnard/dnard/fiq.S | 151 + sys/arch/dnard/dnard/fiq.h | 52 + sys/arch/dnard/dnard/hat.c | 200 + sys/arch/dnard/dnard/hat.h | 91 + sys/arch/dnard/dnard/ns87307.c | 363 ++ sys/arch/dnard/dnard/ns87307reg.h | 395 ++ sys/arch/dnard/dnard/profile.c | 719 ++++ sys/arch/dnard/dnard/scr.c | 4239 ++++++++++++++++++++ sys/arch/dnard/dnard/sequoia.c | 775 ++++ sys/arch/dnard/dnard/sequoia.h | 5130 +++++++++++++++++++++++++ 14 files changed, 13304 insertions(+) create mode 100644 sys/arch/dnard/dnard/autoconf.c create mode 100644 sys/arch/dnard/dnard/conf.c create mode 100644 sys/arch/dnard/dnard/db_ofw_machdep.c create mode 100644 sys/arch/dnard/dnard/dnard_machdep.c create mode 100644 sys/arch/dnard/dnard/fiq.S create mode 100644 sys/arch/dnard/dnard/fiq.h create mode 100644 sys/arch/dnard/dnard/hat.c create mode 100644 sys/arch/dnard/dnard/hat.h create mode 100644 sys/arch/dnard/dnard/ns87307.c create mode 100644 sys/arch/dnard/dnard/ns87307reg.h create mode 100644 sys/arch/dnard/dnard/profile.c create mode 100644 sys/arch/dnard/dnard/scr.c create mode 100644 sys/arch/dnard/dnard/sequoia.c create mode 100644 sys/arch/dnard/dnard/sequoia.h diff --git a/sys/arch/dnard/dnard/autoconf.c b/sys/arch/dnard/dnard/autoconf.c new file mode 100644 index 000000000000..ecd06ddcc8e0 --- /dev/null +++ b/sys/arch/dnard/dnard/autoconf.c @@ -0,0 +1,334 @@ +/* $NetBSD: autoconf.c,v 1.1 2001/05/09 15:58:07 matt Exp $ */ + +/* + * Copyright (c) 1994-1998 Mark Brinicombe. + * Copyright (c) 1994 Brini. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * 3. All advertising materials mentioning features or use of this software + * must display the following acknowledgement: + * This product includes software developed by Mark Brinicombe for + * the NetBSD project. + * 4. The name of the company nor the name of the author may be used to + * endorse or promote products derived from this software without specific + * prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. + * IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, + * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + * + * RiscBSD kernel project + * + * autoconf.c + * + * Autoconfiguration functions + * + * Created : 08/10/94 + */ + +#include "opt_md.h" + +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include +#include +#include +#include + +#include + +#include + +extern void startrtclock __P((void)); +extern int vga_ofbus_cnattach(int, bus_space_tag_t, bus_space_tag_t); + +extern char *boot_file; +extern char *boot_kernel; +struct device *booted_device; +int booted_partition; + +extern dev_t dumpdev; + +void dumpconf __P((void)); +void isa_intr_init __P((void)); + +/* + * Set up the root device from the boot args + */ +void +cpu_rootconf() +{ +#ifndef MEMORY_DISK_IS_ROOT + printf("boot device: %s\n", + booted_device != NULL ? booted_device->dv_xname : ""); +#endif + setroot(booted_device, booted_partition); +} + + +/* + * void cpu_configure() + * + * Configure all the root devices + * The root devices are expected to configure their own children + */ + +void +cpu_configure() +{ + int node; + struct ofbus_attach_args aa; + + /* + * Configure all the roots. + */ + + sequoiaInit(); + startrtclock(); + + /* + * Since the ICU is not standard on the ARM we don't know + * if we have one until we find a bridge. + * Since various PCI interrupts could be routed via the ICU + * (for PCI devices in the bridge) we need to set up the ICU + * now so that these interrupts can be established correctly + * i.e. This is a hack. + */ +#if 0 +#include "isa.h" +#if NISA > 0 && !defined(SHARK) + isa_intr_init(); +#endif +#endif + + /* + * Walk the OFW device tree and configure found devices. + */ + + if (!(node = OF_peer(0))) + panic("No OFW root"); + aa.oba_busname = "ofw"; + aa.oba_phandle = node; + if (!config_rootfound("ofbus", &aa)) + panic("ofw root ofbus not configured"); + + /* Debugging information */ +#ifndef TERSE + printf("ipl_bio=%08x ipl_net=%08x ipl_tty=%08x ipl_imp=%08x\n", + irqmasks[IPL_BIO], irqmasks[IPL_NET], irqmasks[IPL_TTY], + irqmasks[IPL_IMP]); + printf("ipl_audio=%08x ipl_imp=%08x ipl_high=%08x ipl_serial=%08x\n", + irqmasks[IPL_AUDIO], irqmasks[IPL_CLOCK], irqmasks[IPL_HIGH], + irqmasks[IPL_SERIAL]); +#endif + + /* Time to start taking interrupts so lets open the flood gates .... */ + (void)spl0(); +} + +void +device_register(struct device *dev, void *aux) +{ + static struct device *parent; +#if NSD > 0 || NCD > 0 + static struct device *scsipidev; +#endif + static char *boot_component; + struct ofbus_attach_args *oba; + const char *cd_name = dev->dv_cfdata->cf_driver->cd_name; + char name[64]; + int i; + + if (boot_component == NULL) { + char *cp; + boot_component = boot_file; + if (boot_component == NULL) + return; + cp = strrchr(boot_component, ':'); + if (cp != NULL) { + *cp++ = '\0'; + if (cp[0] == '\\') + cp++; + boot_kernel = cp; + } + } + + if (booted_device != NULL + || boot_component == NULL + || boot_component[0] == '\0') + return; + + if (!strcmp(cd_name, "ofbus") || !strcmp(cd_name, "ofisa")) { + oba = aux; + } else if (parent == NULL) { + return; + } else if (parent == dev->dv_parent + && !strcmp(parent->dv_cfdata->cf_driver->cd_name, "ofisa")) { + struct ofisa_attach_args *aa = aux; + oba = &aa->oba; +#if NWD > 0 || NSD > 0 || NCD > 0 + } else if (parent == dev->dv_parent + && !strcmp(parent->dv_cfdata->cf_driver->cd_name, "wdc")) { +#if NSD > 0 || NCD > 0 + if (!strcmp(cd_name, "atapibus")) { + scsipidev = dev; + return; + } +#endif +#if NWD > 0 + if (!strcmp(cd_name, "wd")) { + struct ata_atapi_attach *aa = aux; + char *cp = strchr(boot_component, '@'); + if (cp != NULL + && aa->aa_drv_data->drive == strtoul(cp+1, NULL, 16) + && aa->aa_channel == 0) { + booted_device = dev; + return; + } + } + return; +#endif /* NWD > 0 */ +#if NSD > 0 || NCD > 0 + } else if (scsipidev == dev->dv_parent + && (!strcmp(cd_name, "sd") || !strcmp(cd_name, "cd"))) { + struct scsipibus_attach_args *sa = aux; + char *cp = strchr(boot_component, '@'); + if (cp != NULL + && sa->sa_sc_link->type == BUS_ATAPI + && sa->sa_sc_link->scsipi_atapi.channel == 0 + && sa->sa_sc_link->scsipi_atapi.drive == strtoul(cp+1, NULL, 16)) { + booted_device = dev; + } + return; +#endif /* NSD > 0 || NCD > 0 */ +#endif /* NWD > 0 || NSD > 0 || NCD > 0 */ + } else { + return; + } + (void) of_packagename(oba->oba_phandle, name, sizeof name); + i = strlen(name); + if (!strncmp(name, &boot_component[1], i) + && (boot_component[i+1] == '/' || boot_component[i+1] == '\0')) { + boot_component += i + 1; + if (boot_component[0] == '/') { + parent = dev; + } else { + booted_device = dev; + } + } +} + +#include "ofb.h" +#include "vga_ofbus.h" +#include "com.h" + +#if (NCOM > 0) +#ifndef CONSPEED +#define CONSPEED 9600 +#endif +#ifndef CONMODE +#define CONMODE ((TTYDEF_CFLAG & ~(CSIZE | CSTOPB | PARENB)) | CS8) /* 8N1 */ +#endif + +int comcnmode = CONMODE; +#endif /* (NCOM > 0) */ + +void +cninit(void) +{ + int chosen, stdin, stdout, node; + char type[16], name[16]; + + chosen = OF_finddevice("/chosen"); + if (chosen == 0) + goto nocons; + + if (OF_getprop(chosen, "stdout", &stdout, sizeof(stdout)) + != sizeof(stdout)) + goto nocons; + + node = OF_instance_to_package(stdout); + bzero(type, sizeof(type)); + if (OF_getprop(node, "device_type", type, sizeof(type)) == -1) + goto nocons; + + if (strcmp(type, "display") == 0) { +#if NOFB > 0 + if (!ofb_cnattach()) + goto dokbd; +#endif +#if NVGA_OFBUS > 0 + if (!vga_ofbus_cnattach(node, &isa_io_bs_tag, &isa_mem_bs_tag)) + goto dokbd; +#endif + return; + dokbd: + + /* + * We must determine which keyboard type we have. + */ + if (OF_getprop(chosen, "stdin", &stdin, sizeof(stdin)) + != sizeof(stdin)) { + printf("WARNING: no `stdin' property in /chosen\n"); + return; + } + + node = OF_instance_to_package(stdin); + bzero(name, sizeof(name)); + OF_getprop(node, "name", name, sizeof(name)); + if (strcmp(name, "keyboard") != 0) { + printf("WARNING: stdin is not a keyboard: %s\n", name); + return; + } + +#if (NPCKBC > 0) + pckbc_cnattach(&isa_io_bs_tag, IO_KBD, KBCMDP, PCKBC_KBD_SLOT); +#endif + return; + } + +#if NCOM > 0 + if (strcmp(type, "serial") == 0) { + int regs[3]; + int freq; + if (OF_getprop(node, "reg", regs, sizeof(regs)) != sizeof(regs)) + goto nocom; + if (OF_getprop(node, "clock-frequency", &freq, sizeof(freq)) + != sizeof(freq)) + goto nocom; + if (!comcnattach(&isa_io_bs_tag, regs[1], CONSPEED, freq, + comcnmode)) + return; + nocom: + panic("can't init serial console (hanlde=%#x)", node); + return; + } +#endif + +nocons: + return; +} diff --git a/sys/arch/dnard/dnard/conf.c b/sys/arch/dnard/dnard/conf.c new file mode 100644 index 000000000000..d1c1f4d0ca3d --- /dev/null +++ b/sys/arch/dnard/dnard/conf.c @@ -0,0 +1,417 @@ +/* $NetBSD: conf.c,v 1.1 2001/05/09 15:58:07 matt Exp $ */ + +/* + * Copyright (c) 1994-1998 Mark Brinicombe. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * 3. All advertising materials mentioning features or use of this software + * must display the following acknowledgement: + * This product includes software developed by Mark Brinicombe + * for the NetBSD Project. + * 4. The name of the company nor the name of the author may be used to + * endorse or promote products derived from this software without specific + * prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. + * IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, + * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + * + * RiscBSD kernel project + * + * conf.c + * + * Character and Block Device configuration + * Console configuration + * + * Defines the structures cdevsw and constab + * + * Created : 17/09/94 + */ + +#include "opt_footbridge.h" + +#include +#include +#include +#include +#include +#include +#include + +#include + +#include "wd.h" +#include "md.h" +#include "sd.h" +#include "st.h" +#include "cd.h" +#include "vnd.h" +#include "ccd.h" +#include "raid.h" + +/* Block devices */ + +struct bdevsw bdevsw[] = { + bdev_lkm_dummy(), /* 0: */ + bdev_swap_init(1, sw), /* 1: swap pseudo-device */ + bdev_lkm_dummy(), /* 2: */ + bdev_lkm_dummy(), /* 3: */ + bdev_lkm_dummy(), /* 4: */ + bdev_lkm_dummy(), /* 5: */ + bdev_lkm_dummy(), /* 6: */ + bdev_lkm_dummy(), /* 7: */ + bdev_lkm_dummy(), /* 8: */ + bdev_lkm_dummy(), /* 9: */ + bdev_lkm_dummy(), /* 10: */ + bdev_lkm_dummy(), /* 11: */ + bdev_lkm_dummy(), /* 12: */ + bdev_lkm_dummy(), /* 13: */ + bdev_lkm_dummy(), /* 14: */ + bdev_lkm_dummy(), /* 15: */ + bdev_disk_init(NWD, wd), /* 16: Internal IDE disk */ + bdev_lkm_dummy(), /* 17: */ + bdev_disk_init(NMD, md), /* 18: memory disk */ + bdev_disk_init(NVND,vnd), /* 19: vnode disk driver */ + bdev_lkm_dummy(), /* 20: */ + bdev_disk_init(NCCD,ccd), /* 21: concatenated disk driver */ + bdev_lkm_dummy(), /* 22: */ + bdev_lkm_dummy(), /* 23: */ + bdev_disk_init(NSD,sd), /* 24: SCSI disk */ + bdev_tape_init(NST,st), /* 25: SCSI tape (??) */ + bdev_disk_init(NCD,cd), /* 26: SCSI cdrom */ + bdev_lkm_dummy(), /* 27: */ + bdev_lkm_dummy(), /* 28: */ + bdev_lkm_dummy(), /* 29: */ + bdev_lkm_dummy(), /* 30: */ + bdev_lkm_dummy(), /* 31: */ + bdev_lkm_dummy(), /* 32: */ + bdev_lkm_dummy(), /* 33: */ + bdev_lkm_dummy(), /* 34: */ + bdev_lkm_dummy(), /* 35: */ + bdev_lkm_dummy(), /* 36: */ + bdev_lkm_dummy(), /* 37: */ + bdev_lkm_dummy(), /* 38: */ + bdev_lkm_dummy(), /* 39: */ + bdev_lkm_dummy(), /* 40: */ + bdev_lkm_dummy(), /* 41: */ + bdev_lkm_dummy(), /* 42: */ + bdev_lkm_dummy(), /* 43: */ + bdev_lkm_dummy(), /* 44: */ + bdev_lkm_dummy(), /* 45: */ + bdev_lkm_dummy(), /* 46: */ + bdev_lkm_dummy(), /* 47: */ + bdev_lkm_dummy(), /* 48: */ + bdev_lkm_dummy(), /* 49: */ + bdev_lkm_dummy(), /* 50: */ + bdev_lkm_dummy(), /* 51: */ + bdev_lkm_dummy(), /* 52: */ + bdev_lkm_dummy(), /* 53: */ + bdev_lkm_dummy(), /* 54: */ + bdev_lkm_dummy(), /* 55: */ + bdev_lkm_dummy(), /* 56: */ + bdev_lkm_dummy(), /* 57: */ + bdev_lkm_dummy(), /* 58: */ + bdev_lkm_dummy(), /* 59: */ + bdev_lkm_dummy(), /* 60: */ + bdev_lkm_dummy(), /* 61: */ + bdev_lkm_dummy(), /* 62: */ + bdev_lkm_dummy(), /* 63: */ + bdev_lkm_dummy(), /* 64: */ + bdev_lkm_dummy(), /* 65: */ + bdev_lkm_dummy(), /* 66: */ + bdev_lkm_dummy(), /* 67: */ + bdev_lkm_dummy(), /* 68: */ + bdev_lkm_dummy(), /* 69: */ + bdev_lkm_dummy(), /* 70: */ + bdev_disk_init(NRAID,raid), /* 71: RAIDframe disk driver */ + bdev_lkm_dummy(), /* 72: */ +}; + +int nblkdev = sizeof(bdevsw) / sizeof(bdevsw[0]); + +#include "i4b.h" +#include "i4bctl.h" +#include "i4btrc.h" +#include "i4brbch.h" +#include "i4btel.h" +cdev_decl(i4b); +cdev_decl(i4bctl); +cdev_decl(i4btrc); +cdev_decl(i4brbch); +cdev_decl(i4btel); + +#include "pty.h" +#define ptstty ptytty +#define ptsioctl ptyioctl +#define ptctty ptytty +#define ptcioctl ptyioctl +#include "com.h" +#include "lpt.h" +#include "bpfilter.h" +#include "tun.h" +#include "audio.h" +#include "midi.h" +#include "sequencer.h" +#include "ipfilter.h" +#include "rnd.h" +#include "profiler.h" +#include "ofcons.h" +#include "ofrom.h" +#include "ofrtc.h" /* XXX not used for anything?! */ +#include "scr.h" +#include "joy.h" +#include "vcoda.h" /* coda file system */ +#include "wsdisplay.h" +#include "wskbd.h" +#include "wsmouse.h" +#include "wsmux.h" +#include "scsibus.h" +#include "openfirm.h" + +/* Character devices */ + +struct cdevsw cdevsw[] = { + cdev_mm_init(1, mm), /* 0: /dev/{null,mem,kmem,...} */ + cdev_swap_init(1, sw), /* 1: /dev/drum (swap pseudo-device) */ + cdev_cn_init(1, cn), /* 2: virtual console */ + cdev_ctty_init(1,ctty), /* 3: controlling terminal */ + cdev_tty_init(NOFCONS,ofcons_), /* 4: Openfirmware console */ + cdev_log_init(1,log), /* 5: /dev/klog */ + cdev_ptc_init(NPTY,ptc), /* 6: pseudo-tty master */ + cdev_tty_init(NPTY,pts), /* 7: pseudo-tty slave */ + cdev_lpt_init(NLPT,lpt), /* 8: parallel printer */ + cdev_lkm_dummy(), /* 9: qms driver */ + cdev_lkm_dummy(), /* 10: simple beep device */ + cdev_lkm_dummy(), /* 11: kbd device */ + cdev_tty_init(NCOM,com), /* 12: serial port */ + cdev_lkm_dummy(), /* 13: */ + cdev_lkm_dummy(), /* 14: */ + cdev_lkm_dummy(), /* 15: */ + cdev_disk_init(NWD, wd), /* 16: ST506/ESDI/IDE disk */ + cdev_lkm_dummy(), /* 17: floppy diskette */ + cdev_disk_init(NMD, md), /* 18: memory disk driver */ + cdev_disk_init(NVND,vnd), /* 19: vnode disk driver */ + cdev_lkm_dummy(), /* 20: */ + cdev_disk_init(NCCD,ccd), /* 21: concatenated disk driver */ + cdev_lkm_dummy(), /* 22: */ + cdev_lkm_dummy(), /* 23: */ + cdev_disk_init(NSD,sd), /* 24: SCSI disk */ + cdev_tape_init(NST,st), /* 25: SCSI tape */ + cdev_disk_init(NCD,cd), /* 26: SCSI CD-ROM */ + cdev_lkm_dummy(), /* 27: SCSI autochanger */ + cdev_lkm_dummy(), /* 28: SCSI unknown */ + cdev_lkm_dummy(), /* 29: SCSI scanner */ + cdev_lkm_dummy(), /* 30: */ + cdev_lkm_dummy(), /* 31: */ + cdev_bpftun_init(NBPFILTER,bpf),/* 32: Berkeley packet filter */ + cdev_bpftun_init(NTUN,tun), /* 33: network tunnel */ + cdev_fd_init(1,filedesc), /* 34: file descriptor pseudo-device */ + cdev_lkm_init(NLKM,lkm), /* 35: loadable module driver */ + cdev_audio_init(NAUDIO,audio), /* 36: generic audio I/O */ + cdev_lkm_dummy(), /* 37: vidcconsole device */ + cdev_lkm_dummy(), /* 38: removed cpu device */ + cdev_lkm_dummy(), /* 39: reserved */ + cdev_lkm_dummy(), /* 40: PS2 mouse driver */ + cdev_lkm_dummy(), /* 41: reserved */ + cdev_lkm_dummy(), /* 42: IIC bus driver */ + cdev_lkm_dummy(), /* 43: RTC driver */ + cdev_lkm_dummy(), /* 44: reserved */ + cdev_lkm_dummy(), /* 45: reserved */ + cdev_ipf_init(NIPFILTER,ipl), /* 46: ip-filter device */ + cdev_lkm_dummy(), /* 47: reserved */ + cdev_lkm_dummy(), /* 48: reserved */ + cdev_mm_init(NOFROM, ofrom), /* 49: ofrom */ + cdev_tty_init(NSCR,scr), /* 50: Smart card reader */ + cdev_notdef(), /* 51: reserved */ + cdev_rnd_init(NRND,rnd), /* 52: random source pseudo-device */ + cdev_prof_init(NPROFILER, prof), /* 53: fiq Profiler*/ + cdev_lkm_dummy(), /* 54: FOOTBRIDGE console */ + cdev_lkm_dummy(), /* 55: Reserved for bypass device */ + cdev_joy_init(NJOY,joy), /* 56: ISA joystick */ + cdev_midi_init(NMIDI,midi), /* 57: MIDI I/O */ + cdev_midi_init(NSEQUENCER,sequencer), /* 58: sequencer I/O */ + cdev_vc_nb_init(NVCODA,vc_nb_), /* 59: coda file system psdev */ + cdev_wsdisplay_init(NWSDISPLAY, wsdisplay), /* 60: frame buffers, etc. */ + cdev_mouse_init(NWSKBD, wskbd), /* 61: keyboards */ + cdev_mouse_init(NWSMOUSE, wsmouse), /* 62: mice */ + cdev_lkm_dummy(), /* 63: reserved */ + cdev_lkm_dummy(), /* 64: USB controller */ + cdev_lkm_dummy(), /* 65: USB generic HID */ + cdev_lkm_dummy(), /* 66: USB printer */ + cdev_lkm_dummy(), /* 67: reserved */ + cdev_lkm_dummy(), /* 68: reserved */ + cdev_lkm_dummy(), /* 69: reserved */ + cdev_scsibus_init(NSCSIBUS,scsibus), /* 70: SCSI bus */ + cdev_disk_init(NRAID,raid), /* 71: RAIDframe disk driver */ + cdev_lkm_dummy(), /* 72: USB generic driver */ + cdev_mouse_init(NWSMUX,wsmux), /* 73: ws multiplexor */ + cdev_lkm_dummy(), /* 74: USB tty */ + cdev_lkm_dummy(), /* 75: Diamond Rio 500 */ + cdev_lkm_dummy(), /* USB scanner */ + cdev_openfirm_init(NOPENFIRM,openfirm),/* 77: openfirmware */ + cdev_lkm_dummy(), /* 78: i4b main device */ + cdev_lkm_dummy(), /* 79: i4b control device */ + cdev_lkm_dummy(), /* 80: i4b raw b-channel access */ + cdev_lkm_dummy(), /* 81: i4b trace device */ + cdev_lkm_dummy(), /* 82: i4b phone device */ + +}; + +int nchrdev = sizeof(cdevsw) / sizeof(cdevsw[0]); + +int mem_no = 0; /* major device number of memory special file */ + +/* + * Swapdev is a fake device implemented + * in sw.c used only internally to get to swstrategy. + * It cannot be provided to the users, because the + * swstrategy routine munches the b_dev and b_blkno entries + * before calling the appropriate driver. This would horribly + * confuse, e.g. the hashing routines. Instead, /dev/drum is + * provided as a character (raw) device. + */ +dev_t swapdev = makedev(1, 0); + +/* + * Returns true if dev is /dev/mem or /dev/kmem. + */ +int +iskmemdev(dev) + dev_t dev; +{ + return (major(dev) == mem_no && minor(dev) < 2); +} + +/* + * Returns true if dev is /dev/zero. + */ +int +iszerodev(dev) + dev_t dev; +{ + return (major(dev) == mem_no && minor(dev) == 3); +} + + +static int chrtoblktbl[] = { +/* XXXX This needs to be dynamic for LKMs. */ + /*VCHR*/ /*VBLK*/ + /* 0 */ NODEV, + /* 1 */ 1, + /* 2 */ NODEV, + /* 3 */ NODEV, + /* 4 */ NODEV, + /* 5 */ NODEV, + /* 6 */ NODEV, + /* 7 */ NODEV, + /* 8 */ NODEV, + /* 9 */ NODEV, + /* 10 */ NODEV, + /* 11 */ NODEV, + /* 12 */ NODEV, + /* 13 */ NODEV, + /* 14 */ NODEV, + /* 15 */ NODEV, + /* 16 */ 16, + /* 17 */ 17, + /* 18 */ 18, + /* 19 */ 19, + /* 20 */ NODEV, + /* 21 */ 21, + /* 22 */ NODEV, + /* 23 */ NODEV, + /* 24 */ 24, + /* 25 */ 25, + /* 26 */ 26, + /* 27 */ NODEV, + /* 28 */ NODEV, + /* 29 */ NODEV, + /* 30 */ NODEV, + /* 31 */ NODEV, + /* 32 */ NODEV, + /* 33 */ NODEV, + /* 34 */ NODEV, + /* 35 */ NODEV, + /* 36 */ NODEV, + /* 37 */ NODEV, + /* 38 */ NODEV, + /* 39 */ NODEV, + /* 40 */ NODEV, + /* 41 */ NODEV, + /* 42 */ NODEV, + /* 43 */ NODEV, + /* 44 */ NODEV, + /* 45 */ NODEV, + /* 46 */ NODEV, + /* 47 */ NODEV, + /* 48 */ NODEV, + /* 49 */ NODEV, + /* 50 */ NODEV, + /* 51 */ NODEV, + /* 52 */ NODEV, + /* 53 */ NODEV, + /* 54 */ NODEV, + /* 55 */ NODEV, + /* 56 */ NODEV, + /* 57 */ NODEV, + /* 58 */ NODEV, + /* 59 */ NODEV, + /* 60 */ NODEV, + /* 61 */ NODEV, + /* 62 */ NODEV, + /* 63 */ NODEV, + /* 64 */ NODEV, + /* 65 */ NODEV, + /* 66 */ NODEV, + /* 67 */ NODEV, + /* 68 */ NODEV, + /* 69 */ NODEV, + /* 70 */ NODEV, + /* 71 */ 71, + /* 72 */ NODEV, + /* 73 */ NODEV, + /* 74 */ NODEV, + /* 75 */ NODEV, + /* 76 */ NODEV, + /* 77 */ NODEV, + /* 78 */ NODEV, + /* 79 */ NODEV, + /* 80 */ NODEV, + /* 81 */ NODEV, + /* 82 */ NODEV, +}; + +/* + * Convert a character device number to a block device number. + */ + +dev_t +chrtoblk(dev) + dev_t dev; +{ + int blkmaj; + + if (major(dev) >= nchrdev) + return (NODEV); + + blkmaj = chrtoblktbl[major(dev)]; + if (blkmaj == NODEV) + return (NODEV); + return (makedev(blkmaj, minor(dev))); +} diff --git a/sys/arch/dnard/dnard/db_ofw_machdep.c b/sys/arch/dnard/dnard/db_ofw_machdep.c new file mode 100644 index 000000000000..ffbf597ef215 --- /dev/null +++ b/sys/arch/dnard/dnard/db_ofw_machdep.c @@ -0,0 +1,74 @@ +/* $NetBSD: db_ofw_machdep.c,v 1.1 2001/05/09 15:58:07 matt Exp $ */ + +/* + * Copyright (c) 1996 Mark Brinicombe + * + * Mach Operating System + * Copyright (c) 1991,1990 Carnegie Mellon University + * All Rights Reserved. + * + * Permission to use, copy, modify and distribute this software and its + * documentation is hereby granted, provided that both the copyright + * notice and this permission notice appear in all copies of the + * software, derivative works or modified versions, and any portions + * thereof, and that both notices appear in supporting documentation. + * + * CARNEGIE MELLON ALLOWS FREE USE OF THIS SOFTWARE IN ITS "AS IS" + * CONDITION. CARNEGIE MELLON DISCLAIMS ANY LIABILITY OF ANY KIND FOR + * ANY DAMAGES WHATSOEVER RESULTING FROM THE USE OF THIS SOFTWARE. + * + * Carnegie Mellon requests users of this software to return to + * + * Software Distribution Coordinator or Software.Distribution@CS.CMU.EDU + * School of Computer Science + * Carnegie Mellon University + * Pittsburgh PA 15213-3890 + * + * any improvements or extensions that they make and grant Carnegie the + * rights to redistribute these changes. + */ + +#include +#include +#include +#include + +#include + +#include +#include +#include + +#include + +void +db_of_boot_cmd(addr, have_addr, count, modif) + db_expr_t addr; + int have_addr; + db_expr_t count; + char *modif; +{ + OF_boot(""); +} + + +void +db_of_enter_cmd(addr, have_addr, count, modif) + db_expr_t addr; + int have_addr; + db_expr_t count; + char *modif; +{ + OF_enter(); +} + + +void +db_of_exit_cmd(addr, have_addr, count, modif) + db_expr_t addr; + int have_addr; + db_expr_t count; + char *modif; +{ + OF_exit(); +} diff --git a/sys/arch/dnard/dnard/dnard_machdep.c b/sys/arch/dnard/dnard/dnard_machdep.c new file mode 100644 index 000000000000..97c8699adcc0 --- /dev/null +++ b/sys/arch/dnard/dnard/dnard_machdep.c @@ -0,0 +1,364 @@ +/* $NetBSD: dnard_machdep.c,v 1.1 2001/05/09 15:58:07 matt Exp $ */ + +/* + * Copyright 1997 + * Digital Equipment Corporation. All rights reserved. + * + * This software is furnished under license and may be used and + * copied only in accordance with the following terms and conditions. + * Subject to these conditions, you may download, copy, install, + * use, modify and distribute this software in source and/or binary + * form. No title or ownership is transferred hereby. + * + * 1) Any source code used, modified or distributed must reproduce + * and retain this copyright notice and list of conditions as + * they appear in the source file. + * + * 2) No right is granted to use any trade name, trademark, or logo of + * Digital Equipment Corporation. Neither the "Digital Equipment + * Corporation" name nor any trademark or logo of Digital Equipment + * Corporation may be used to endorse or promote products derived + * from this software without the prior written permission of + * Digital Equipment Corporation. + * + * 3) This software is provided "AS-IS" and any express or implied + * warranties, including but not limited to, any implied warranties + * of merchantability, fitness for a particular purpose, or + * non-infringement are disclaimed. In no event shall DIGITAL be + * liable for any damages whatsoever, and in particular, DIGITAL + * shall not be liable for special, indirect, consequential, or + * incidental damages or damages for lost profits, loss of + * revenue or loss of use, whether such damages arise in contract, + * negligence, tort, under statute, in equity, at law or otherwise, + * even if advised of the possibility of such damage. + */ + +/* + * Kernel setup for the SHARK Configuration + */ + +#include "opt_ddb.h" + +#include +#include +#include +#include +#include +#include +#include +#include + +#include + +#include + +#include +#include +#include + +#include +#include +#include +#include +#include +#include + +#include "opt_ipkdb.h" + +#include +#include +#include +#include +#include +#include + +#include "wd.h" +#include "cd.h" +#include "sd.h" + +#if NWD > 0 || NSD > 0 || NCD > 0 +#include +#endif +#if NSD > 0 || NCD > 0 +#include +#include +#include +#endif + +/* + * Imported variables + */ +extern pv_addr_t irqstack; +extern pv_addr_t undstack; +extern pv_addr_t abtstack; +extern pv_addr_t kernelstack; +extern u_int data_abort_handler_address; +extern u_int prefetch_abort_handler_address; +extern u_int undefined_handler_address; + +/* + * Imported routines + */ +extern void parse_mi_bootargs __P((char *args)); +extern void data_abort_handler __P((trapframe_t *frame)); +extern void prefetch_abort_handler __P((trapframe_t *frame)); +extern void undefinedinstruction_bounce __P((trapframe_t *frame)); +extern void consinit __P((void)); +#ifdef DDB +extern void db_machine_init __P((void)); +#endif +int ofbus_match __P((struct device *, struct cfdata *, void *)); +void ofbus_attach __P((struct device *, struct device *, void *)); + + +/* + * Exported variables + */ +char *boot_args = NULL; +char *boot_file = NULL; +char *boot_kernel = NULL; +#ifndef PMAP_STATIC_L1S +int max_processes = 64; /* Default number */ +#endif /* !PMAP_STATIC_L1S */ + +int ofw_handleticks = 0; /* set to TRUE by cpu_initclocks */ + +/* + * For faster cache cleaning we need two 16K banks of virtual address + * space that NOTHING else will access and then we alternate the cache + * cleaning between the two banks. + * The cache cleaning code requires requires 2 banks aligned + * on total size boundry so the banks can be alternated by + * xorring the size bit (assumes the bank size is a power of 2) + */ +extern unsigned int sa110_cache_clean_addr; +extern unsigned int sa110_cache_clean_size; + +struct cfattach ofbus_root_ca = { + sizeof(struct device), ofbus_match, ofbus_attach +}; + + +/* + * Exported routines + */ +/* Move to header file? */ +extern void cpu_reboot __P((int, char *)); +extern vaddr_t initarm __P((ofw_handle_t)); + +/* Local routines */ +static void process_kernel_args __P((void)); + + +/**************************************************************/ + + +/* + * void cpu_reboot(int howto, char *bootstr) + * + * Reboots the system, in evsent of: + * - reboot system call + * - panic + */ + +void +cpu_reboot(howto, bootstr) + int howto; + char *bootstr; +{ + /* Just call OFW common routine. */ + ofw_boot(howto, bootstr); + + OF_boot("not reached -- stupid compiler"); +} + +/* + * vaddr_t initarm(ofw_handle_t handle) + * + * Initial entry point on startup for a GENERIC OFW + * system. Called with MMU on, running in the OFW + * client environment. + * + * Major tasks are: + * - read the bootargs out of OFW; + * - take over memory management from OFW; + * - set-up the stacks + * - set-up the exception handlers + * + * Return the new stackptr (va) for the SVC frame. + * + */ +vaddr_t +initarm(ofw_handle) + ofw_handle_t ofw_handle; +{ + vaddr_t pclean; + vaddr_t isa_io_physaddr, isa_mem_physaddr; + vaddr_t isa_io_virtaddr, isa_mem_virtaddr; + vaddr_t isadmaphysbufs; + fiqhandler_t fiqhandler; + extern void shark_fiq __P((void)); + extern void shark_fiq_end __P((void)); + + /* Don't want to get hit with interrupts 'til we're ready. */ + (void)disable_interrupts(I32_bit | F32_bit); + + set_cpufuncs(); + + /* XXX - set these somewhere else? -JJK */ + boothowto = 0; + + /* Init the OFW interface. */ + /* MUST do this before invoking any OFW client services! */ + ofw_init(ofw_handle); + + /* Configure ISA stuff: must be done before consinit */ + ofw_configisa(&isa_io_physaddr, &isa_mem_physaddr); + + /* Map-in ISA I/O and memory space. */ + /* XXX - this should be done in the isa-bus attach routine! -JJK */ + isa_mem_virtaddr = ofw_map(isa_mem_physaddr, NBPD, 0); + isa_io_virtaddr = ofw_map(isa_io_physaddr, NBPD, 0); + + /* Set-up the ISA system: must be done before consinit */ + isa_init(isa_io_virtaddr, isa_mem_virtaddr); + + /* Initialize the console (which will call into OFW). */ + /* This will allow us to see panic messages and other printf output. */ + consinit(); + + /* Get boot info and process it. */ + ofw_getbootinfo(&boot_file, &boot_args); + process_kernel_args(); + + ofw_configisadma(&isadmaphysbufs); + isa_dma_init(); + + /* allocate a cache clean space */ + if ((pclean = ofw_getcleaninfo()) != -1) { + sa110_cache_clean_addr = ofw_map(pclean, 0x4000 * 2, + PT_B | PT_C); + sa110_cache_clean_size = 0x4000; + } + + /* Configure memory. */ + ofw_configmem(); + + /* + * Set-up stacks. + * The kernel stack for SVC mode will be updated on return + * from this routine. + */ + set_stackptr(PSR_IRQ32_MODE, irqstack.pv_va + NBPG); + set_stackptr(PSR_UND32_MODE, undstack.pv_va + NBPG); + set_stackptr(PSR_ABT32_MODE, abtstack.pv_va + NBPG); + + /* Set-up exception handlers. */ + + /* + * Take control of selected vectors from OFW. + * We take: undefined, swi, pre-fetch abort, data abort, addrexc, + * irq, fiq + * OFW retains: reset + */ + { + int our_vecnums[] = {1, 2, 3, 4, 5, 6, 7}; + unsigned int *vectors = (unsigned int *)0; + extern unsigned int page0[]; + int i; + + for (i = 0; i < (sizeof(our_vecnums) / sizeof(int)); i++) { + int vecnum = our_vecnums[i]; + + /* Copy both the instruction and the data word + * for the vector. + * The latter is needed to support branching + * arbitrarily far. + */ + vectors[vecnum] = page0[vecnum]; + vectors[vecnum + 8] = page0[vecnum + 8]; + } + + /* Sync the first 16 words of memory */ + cpu_cache_syncI_rng(0, 64); + } + + data_abort_handler_address = (u_int)data_abort_handler; + prefetch_abort_handler_address = (u_int)prefetch_abort_handler; + undefined_handler_address = + (u_int)undefinedinstruction_bounce; /* why is this needed? -JJK */ + + /* Initialise the undefined instruction handlers. */ + undefined_init(); + + /* Now for the SHARK-specific part of the FIQ set-up */ + fiqhandler.fh_func = shark_fiq; + fiqhandler.fh_size = (char *)shark_fiq_end - (char *)shark_fiq; + fiqhandler.fh_mask = 0x01; /* XXX ??? */ + fiqhandler.fh_r8 = isa_io_virtaddr; + fiqhandler.fh_r9 = 0; /* no routine right now */ + fiqhandler.fh_r10 = 0; /* no arg right now */ + fiqhandler.fh_r11 = 0; /* scratch */ + fiqhandler.fh_r12 = 0; /* scratch */ + fiqhandler.fh_r13 = 0; /* must set a stack when r9 is set! */ + + if (fiq_claim(&fiqhandler)) + panic("Cannot claim FIQ vector.\n"); + +#ifdef DDB + printf("ddb: "); + db_machine_init(); + { + struct exec *kernexec = (struct exec *)KERNEL_BASE; + extern int end; + extern char *esym; + + ddb_init(kernexec->a_syms, &end, esym); + } + if (boothowto & RB_KDB) + Debugger(); +#endif + + /* Return the new stackbase. */ + return(kernelstack.pv_va + USPACE_SVC_STACK_TOP); +} + + +/* + * Set various globals based on contents of boot_args + * + * Note that this routine must NOT trash boot_args, as + * it is scanned by later routines. + */ +static void +process_kernel_args(void) +{ +#ifdef RB_QUIET + int bool; +#endif + +#if defined(RB_QUIET) && defined(BOOT_QUIETLY) + boothowto |= RB_QUIET; +#endif + + /* Process all the generic ARM boot options */ + parse_mi_bootargs(boot_args); + +#ifdef RB_QUIET + if (get_bootconf_option(args, "noquiet", BOOTOPT_TYPE_BOOLEAN, &bool)) { + if (!bool) + boothowto |= RB_QUIET; + else + boothowto &= ~RB_QUIET; + } + if (get_bootconf_option(args, "quiet", BOOTOPT_TYPE_BOOLEAN, &bool)) { + if (bool) + boothowto |= RB_QUIET; + else + boothowto &= ~RB_QUIET; + } +#endif + + /* Check for ofwgencfg-specific args here. */ +} + diff --git a/sys/arch/dnard/dnard/fiq.S b/sys/arch/dnard/dnard/fiq.S new file mode 100644 index 000000000000..355642f3982a --- /dev/null +++ b/sys/arch/dnard/dnard/fiq.S @@ -0,0 +1,151 @@ +/* $NetBSD: fiq.S,v 1.1 2001/05/09 15:58:07 matt Exp $ */ + +/* + * Copyright 1997 + * Digital Equipment Corporation. All rights reserved. + * + * This software is furnished under license and may be used and + * copied only in accordance with the following terms and conditions. + * Subject to these conditions, you may download, copy, install, + * use, modify and distribute this software in source and/or binary + * form. No title or ownership is transferred hereby. + * + * 1) Any source code used, modified or distributed must reproduce + * and retain this copyright notice and list of conditions as + * they appear in the source file. + * + * 2) No right is granted to use any trade name, trademark, or logo of + * Digital Equipment Corporation. Neither the "Digital Equipment + * Corporation" name nor any trademark or logo of Digital Equipment + * Corporation may be used to endorse or promote products derived + * from this software without the prior written permission of + * Digital Equipment Corporation. + * + * 3) This software is provided "AS-IS" and any express or implied + * warranties, including but not limited to, any implied warranties + * of merchantability, fitness for a particular purpose, or + * non-infringement are disclaimed. In no event shall DIGITAL be + * liable for any damages whatsoever, and in particular, DIGITAL + * shall not be liable for special, indirect, consequential, or + * incidental damages or damages for lost profits, loss of + * revenue or loss of use, whether such damages arise in contract, + * negligence, tort, under statute, in equity, at law or otherwise, + * even if advised of the possibility of such damage. + */ + +/* + * fiq.S + * + * Low level fiq handlers + * + * Created : 19/05/97 + */ + +#include +#include +#include +#include + +sp .req r13 +lr .req r14 +pc .req r15 + + .text + +/* this variable is used to detect when it is necessary to unwedge the + sequoia SMI/PMI edge detect logic. *sigh* */ +Lfiqs_happened: + .word _C_LABEL(fiqs_happened) +Lsequoia_index_cache: + .word _C_LABEL(sequoia_index_cache) + + .data + .global _C_LABEL(fiqs_happened) +_C_LABEL(fiqs_happened): + .word 0 + + .text + + .global _C_LABEL(shark_fiq) + .global _C_LABEL(shark_fiq_end) + +/* + * r8 - VAM_IO_DATA = address of IO space in virtual memory + * r9 - C routine to call (0 => no routine) + * r10 - argument (0 => pass PMI reason register) + * r11 - scratch + * r12 - scratch + * r13 - stack for C routine call + */ + +_C_LABEL(shark_fiq): + /* clear the FIQ immediately */ + /* do the FIQ/SMI clear here to avoid synchronization problems! + both the chip enable (caused by the ISA register read) and + the sequoia bit clear must be done. do it in that order so + the sequoia port accesses will clear the chip enable caused + by accessing FIQ_CLEAR_IOPORT + */ + /* set up to read/write the power management status register */ + ldr r11, Lsequoia_index_cache + ldr r12, [r11] + + /* see if the index is properly set. unfortunately, the common + case will probably be that the FIQ handler (e.g. smartcard) + talks to the sequoia, so the index will need to be set. */ + cmp r12, #PMC_PMSR_REG + movne r12, #PMC_PMSR_REG +#ifdef STRH + strneh r12, [r8, #SEQUOIA_INDEX] +#else + .word 0x11c8c2b4 +#endif + strne r12, [r11] + + /* set SMIACT by changing the power management mode to sleep */ + mov r12, #PMMD_SLEEP +#ifdef STRH + strh r12, [r8, #SEQUOIA_DATA] +#else + .word 0xe1c8c2b6 +#endif + + /* get the PMI reason register, if desired */ + cmp r10, #0 +#ifdef LDRH + ldreqh r10, [r8, #SEQUOIA_DATA] +#else + .word 0x01d8a2b6 /* ldrh r10, [r8, #0x26] */ +#endif + + /* simultaneously clear the PMI reason bits and clear SMIACT */ + mov r12, #PMMD_ON + orr r12, r12, #PMSR_M_PMISRC +#ifdef STRH + strh r12, [r8, #SEQUOIA_DATA] +#else + .word 0xe1c8c2b6 +#endif + + ldr r12, Lfiqs_happened + ldr r11, [r12] + add r11, r11, #1 + str r11, [r12] + + cmp r9, #0 + subeqs pc, lr, #4 /* no routine => return from trap */ + + /* assume that the C routine follows the ARM procedure call standard. + save only user registers and let the C code save the rest. + r0-r3, r12, r14 clobbered. other regs should be restored + by C code. + */ + stmfd sp!, {r0-r3, lr} /* save user registers */ + mov r0, r10 /* pass the PMI reason register */ + mov lr, pc /* call C routine */ + mov pc, r9 + ldmfd sp!, {r0-r3, lr} /* restore user registers */ + subs pc, lr, #4 /* return from trap */ +_C_LABEL(shark_fiq_end): + +/* End of fiq.S */ diff --git a/sys/arch/dnard/dnard/fiq.h b/sys/arch/dnard/dnard/fiq.h new file mode 100644 index 000000000000..d4f587eca464 --- /dev/null +++ b/sys/arch/dnard/dnard/fiq.h @@ -0,0 +1,52 @@ +/* $NetBSD: fiq.h,v 1.1 2001/05/09 15:58:07 matt Exp $ */ + +/* + * Copyright 1997 + * Digital Equipment Corporation. All rights reserved. + * + * This software is furnished under license and may be used and + * copied only in accordance with the following terms and conditions. + * Subject to these conditions, you may download, copy, install, + * use, modify and distribute this software in source and/or binary + * form. No title or ownership is transferred hereby. + * + * 1) Any source code used, modified or distributed must reproduce + * and retain this copyright notice and list of conditions as + * they appear in the source file. + * + * 2) No right is granted to use any trade name, trademark, or logo of + * Digital Equipment Corporation. Neither the "Digital Equipment + * Corporation" name nor any trademark or logo of Digital Equipment + * Corporation may be used to endorse or promote products derived + * from this software without the prior written permission of + * Digital Equipment Corporation. + * + * 3) This software is provided "AS-IS" and any express or implied + * warranties, including but not limited to, any implied warranties + * of merchantability, fitness for a particular purpose, or + * non-infringement are disclaimed. In no event shall DIGITAL be + * liable for any damages whatsoever, and in particular, DIGITAL + * shall not be liable for special, indirect, consequential, or + * incidental damages or damages for lost profits, loss of + * revenue or loss of use, whether such damages arise in contract, + * negligence, tort, under statute, in equity, at law or otherwise, + * even if advised of the possibility of such damage. + */ + +/* + * fiq.h + * + * Low level fiq handlers + * + * Created : 20/05/97 + */ + +#ifndef _FIQ_H_ + +#include + +/* FIQ_CLEAR_IOPORT can be anywhere, as long as it is harmless. + IO_TIMER2 seems pretty harmless on SHARK. */ +#define FIQ_CLEAR_IOPORT IO_TIMER2 + +#endif /* _FIQ_H_ */ diff --git a/sys/arch/dnard/dnard/hat.c b/sys/arch/dnard/dnard/hat.c new file mode 100644 index 000000000000..0b3d2cdd8f19 --- /dev/null +++ b/sys/arch/dnard/dnard/hat.c @@ -0,0 +1,200 @@ +/* $NetBSD: hat.c,v 1.1 2001/05/09 15:58:07 matt Exp $ */ + +/* + * Copyright 1997 + * Digital Equipment Corporation. All rights reserved. + * + * This software is furnished under license and may be used and + * copied only in accordance with the following terms and conditions. + * Subject to these conditions, you may download, copy, install, + * use, modify and distribute this software in source and/or binary + * form. No title or ownership is transferred hereby. + * + * 1) Any source code used, modified or distributed must reproduce + * and retain this copyright notice and list of conditions as + * they appear in the source file. + * + * 2) No right is granted to use any trade name, trademark, or logo of + * Digital Equipment Corporation. Neither the "Digital Equipment + * Corporation" name nor any trademark or logo of Digital Equipment + * Corporation may be used to endorse or promote products derived + * from this software without the prior written permission of + * Digital Equipment Corporation. + * + * 3) This software is provided "AS-IS" and any express or implied + * warranties, including but not limited to, any implied warranties + * of merchantability, fitness for a particular purpose, or + * non-infringement are disclaimed. In no event shall DIGITAL be + * liable for any damages whatsoever, and in particular, DIGITAL + * shall not be liable for special, indirect, consequential, or + * incidental damages or damages for lost profits, loss of + * revenue or loss of use, whether such damages arise in contract, + * negligence, tort, under statute, in equity, at law or otherwise, + * even if advised of the possibility of such damage. + */ + +/* + * hat.c + * + * implementation of high-availability timer on SHARK + * + * Created : 19/05/97 + */ +#include +#include +#include +#include +#include + +#include +#include +#include +#include + +#include +#include + +#include +#include +#include + +extern int fiq_getregs __P((fiqhandler_t *)); +extern int fiq_setregs __P((fiqhandler_t *)); + +static int hatOn = 0; + +/* interface to high-availability timer */ + +static void hatClkCount(int count); +static void hatEnableSWTCH(); + +static void (*hatWedgeFn)(int); + +int hatClkOff(void) +{ + fiqhandler_t fiqhandler; + u_int16_t seqReg; + + if (!hatOn) return -1; + hatOn = 0; + hatWedgeFn = NULL; + + /* disable the SWTCH pin */ + + sequoiaRead(PMC_PMCMCR2_REG, &seqReg); + sequoiaWrite(PMC_PMCMCR2_REG, seqReg | (PMCMCR2_M_SWTCHEN)); + + /* turn off timer 2 */ + outb(ATSR_REG1_REG, + inb(ATSR_REG1_REG) & ~((REG1_M_TMR2EN) | (REG1_M_SPKREN))); + + fiq_getregs(&fiqhandler); + + /* get rid of the C routine and stack */ + fiqhandler.fh_r9 = 0; + fiqhandler.fh_r13 = 0; + + fiq_setregs(&fiqhandler); + isa_dmathaw(&isa_chipset_tag); /* XXX */ + + return 0; +} + + +int hatClkOn(int count, void (*hatFn)(int), int arg, + unsigned char *stack, void (*wedgeFn)(int)) +{ + fiqhandler_t fiqhandler; + u_int16_t seqReg; + + if (hatOn) return -1; + + hatWedgeFn = wedgeFn; + + isa_dmafreeze(&isa_chipset_tag); /* XXX */ + + fiq_getregs(&fiqhandler); + + /* set the C routine and stack */ + fiqhandler.fh_r9 = (u_int)hatFn; + fiqhandler.fh_r10 = (u_int)arg; + fiqhandler.fh_r13 = (u_int)stack; + + fiq_setregs(&fiqhandler); + + /* no debounce on SWTCH */ + sequoiaRead(PMC_DBCR_REG, &seqReg); + sequoiaWrite(PMC_DBCR_REG, seqReg | DBCR_M_DBDIS0); + + hatEnableSWTCH(); /* enable the SWTCH -> PMI logic */ + + /* turn on timer 2 */ + outb(ATSR_REG1_REG, + inb(ATSR_REG1_REG) | (REG1_M_TMR2EN) | (REG1_M_SPKREN)); + + /* start timer 2 running */ + hatClkCount(count); + + /* enable the SWTCH pin */ + sequoiaRead(PMC_PMCMCR2_REG, &seqReg); + sequoiaWrite(PMC_PMCMCR2_REG, seqReg | (PMCMCR2_M_SWTCHEN)); + + hatOn = 1; + return 0; +} + + +int hatClkAdjust(int count) +{ + if (!hatOn) return -1; + + hatClkCount(count); + hatEnableSWTCH(); + + return 0; +} + +static void +hatEnableSWTCH() +{ + u_int16_t seqReg; + + /* SWTCH input causes PMI, not automatic switch to standby mode! */ + /* clearing bit 9 is bad news. seems to enable PMI from secondary + activity timeout! */ + /* first setting, then clearing this bit seems to unwedge the edge + detect logic in the sequoia */ + + sequoiaRead(PMC_PMIMCR_REG, &seqReg); + sequoiaWrite(PMC_PMIMCR_REG, seqReg | (PMIMCR_M_IMSKSWSTBY)); + sequoiaWrite(PMC_PMIMCR_REG, seqReg & ~(PMIMCR_M_IMSKSWSTBY)); +} + +void hatUnwedge() +{ + static int lastFiqsHappened = -1; + extern int fiqs_happened; + + if (!hatOn) return; + + if (lastFiqsHappened == fiqs_happened) { + hatEnableSWTCH(); + if (hatWedgeFn) (*hatWedgeFn)(fiqs_happened); + } else { + lastFiqsHappened = fiqs_happened; + } +} + +static void hatClkCount(int count) +{ + u_int savedints; + + savedints = disable_interrupts(I32_bit); + + outb(TIMER_MODE, TIMER_SEL2|TIMER_RATEGEN|TIMER_16BIT); + outb(TIMER_CNTR2, count % 256); + outb(TIMER_CNTR2, count / 256); + + restore_interrupts(savedints); +} + diff --git a/sys/arch/dnard/dnard/hat.h b/sys/arch/dnard/dnard/hat.h new file mode 100644 index 000000000000..c62a903c4be8 --- /dev/null +++ b/sys/arch/dnard/dnard/hat.h @@ -0,0 +1,91 @@ +/* $NetBSD: hat.h,v 1.1 2001/05/09 15:58:07 matt Exp $ */ + +/* + * Copyright 1997 + * Digital Equipment Corporation. All rights reserved. + * + * This software is furnished under license and may be used and + * copied only in accordance with the following terms and conditions. + * Subject to these conditions, you may download, copy, install, + * use, modify and distribute this software in source and/or binary + * form. No title or ownership is transferred hereby. + * + * 1) Any source code used, modified or distributed must reproduce + * and retain this copyright notice and list of conditions as + * they appear in the source file. + * + * 2) No right is granted to use any trade name, trademark, or logo of + * Digital Equipment Corporation. Neither the "Digital Equipment + * Corporation" name nor any trademark or logo of Digital Equipment + * Corporation may be used to endorse or promote products derived + * from this software without the prior written permission of + * Digital Equipment Corporation. + * + * 3) This software is provided "AS-IS" and any express or implied + * warranties, including but not limited to, any implied warranties + * of merchantability, fitness for a particular purpose, or + * non-infringement are disclaimed. In no event shall DIGITAL be + * liable for any damages whatsoever, and in particular, DIGITAL + * shall not be liable for special, indirect, consequential, or + * incidental damages or damages for lost profits, loss of + * revenue or loss of use, whether such damages arise in contract, + * negligence, tort, under statute, in equity, at law or otherwise, + * even if advised of the possibility of such damage. + */ + +/* + * hat.h + * + * interface to high-availability timer on SHARK + * + * Created : 19/05/97 + */ + +/* interface to high-availability timer. + DO NOT CALL ANY OF THESE FUNCTIONS FROM CODE CALLED BY THE FIQ! + (e.g. hatFn) +*/ + +/* hatClkOff(): turn off HAT clock. + + returns: 0 => success -1 => error +*/ +int hatClkOff(void); + +/* hatClkOn(): turn on HAT clock. + + count = count for ISA TIMER 2, which generates HAT clock + hatFn = function to be called on every HAT FIQ. + arg = argument to pass to hatFn. + if (arg == 0) + then the FIQ handler will pass the contents of + sequoia register 001H, including the PMI source bits + otherwise the FIQ handler will not load the register and + will pass arg directly + stack = stack for hatFn + wedgeFn = function called when the HAT wedges and needs to be restarted. + the argument is the total number of FIQs received by the system. + (wraps at 32-bits). + + returns: 0 => success -1 => error +*/ +int hatClkOn(int count, void (*hatFn)(int), int arg, + unsigned char *stack, void (*wedgeFn)(int)); + +/* hatClkAdjust: adjusts the speed of the HAT. + + count = new count for ISA TIMER 2 + + returns: 0 => success -1 => error +*/ +int hatClkAdjust(int count); + +/* hatUnwedge: call this function periodically (slower than the frequency + of the HAT) to unwedge the HAT, if necessary. +*/ +void hatUnwedge(); + +/* HAT_MIN_FREQ: should be a power of 2. Call hatUnwedge() no more + often than HAT_MIN_FREQ. HMF should be a power of 2. +*/ +#define HAT_MIN_FREQ 64 diff --git a/sys/arch/dnard/dnard/ns87307.c b/sys/arch/dnard/dnard/ns87307.c new file mode 100644 index 000000000000..9892f9c5948e --- /dev/null +++ b/sys/arch/dnard/dnard/ns87307.c @@ -0,0 +1,363 @@ +/* $NetBSD: ns87307.c,v 1.1 2001/05/09 15:58:07 matt Exp $ */ + +/* + * Copyright 1997 + * Digital Equipment Corporation. All rights reserved. + * + * This software is furnished under license and may be used and + * copied only in accordance with the following terms and conditions. + * Subject to these conditions, you may download, copy, install, + * use, modify and distribute this software in source and/or binary + * form. No title or ownership is transferred hereby. + * + * 1) Any source code used, modified or distributed must reproduce + * and retain this copyright notice and list of conditions as + * they appear in the source file. + * + * 2) No right is granted to use any trade name, trademark, or logo of + * Digital Equipment Corporation. Neither the "Digital Equipment + * Corporation" name nor any trademark or logo of Digital Equipment + * Corporation may be used to endorse or promote products derived + * from this software without the prior written permission of + * Digital Equipment Corporation. + * + * 3) This software is provided "AS-IS" and any express or implied + * warranties, including but not limited to, any implied warranties + * of merchantability, fitness for a particular purpose, or + * non-infringement are disclaimed. In no event shall DIGITAL be + * liable for any damages whatsoever, and in particular, DIGITAL + * shall not be liable for special, indirect, consequential, or + * incidental damages or damages for lost profits, loss of + * revenue or loss of use, whether such damages arise in contract, + * negligence, tort, under statute, in equity, at law or otherwise, + * even if advised of the possibility of such damage. + */ + +/* +**++ +** +** FACILITY: +** +** ns87307 SuperIO chip configuration functions. +** +** ABSTRACT: +** +** This file contains routines to configure the National Semiconductor +** PC87307VUL SuperIO chip. +** +** AUTHORS: +** +** John Court, Digital Equipment Corporation. +** +** CREATION DATE: +** +** 16/4/1997 +** +**-- +*/ + +#include "opt_ddb.h" + +#include +#include +#include + +#include +#include + +#include +#include + + + + + + + + + +/* +**++ +** FUNCTION NAME: +** +** i87307KbdConfig +** +** FUNCTIONAL DESCRIPTION: +** +** This function configures the Keyboard controller logical +** device on the ns87307 SuperIO hardware. It sets up the addresses +** of the data and command ports and configures the irq number and +** triggering for the device. It then activates the device. +** +** FORMAL PARAMETERS: +** +** iot +** kbdBase +** irqNum +** +** IMPLICIT INPUTS: +** +** None. +** +** IMPLICIT OUTPUTS: +** +** None. +** +** function value or completion codes +** +** TRUE configuration of the kdb device was successful. +** FALSE configuration of the kdb device failed. +** +** SIDE EFFECTS: +** +** None. +**-- +*/ +int +i87307KbdConfig(bus_space_tag_t iot, + u_int kbdBase, + u_int irqNum ) +{ + u_int configured = FALSE; + bus_space_handle_t ioh; + + + if (!(bus_space_map( iot, CONNSIOADDR, NSIO_NPORTS, 0 , &ioh ))) + { + NSIO_SELECT_DEV( iot, ioh, NSIO_DEV_KBC ); + NSIO_DEACTIVATE_DEV( iot, ioh ); + NSIO_CONFIG_IRQ( iot, ioh, irqNum, NSIO_IRQ_LEVEL | NSIO_IRQ_HIGH ); + NSIO_CONFIG_KBCDATA( iot, ioh, kbdBase ); + NSIO_CONFIG_KBCCMD(iot, ioh, kbdBase+4); + NSIO_WRITE_REG( iot, ioh, NSIO_KBC_CFG, 0x80 ); + NSIO_ACTIVATE_DEV( iot, ioh ); + NSIO_CONFIG_KBCDEBUG( iot, ioh ); + + /* unmap the space so can probe later + */ + bus_space_unmap( iot, ioh, NSIO_NPORTS ); + + configured = TRUE; + } + + return (configured); +} /* End i87307KbdConfig() */ + + + +/* +**++ +** FUNCTION NAME: +** +** i87307MouseConfig +** +** FUNCTIONAL DESCRIPTION: +** +** This function configures the Mouse logical device on the ns87307 +** SuperIO chip. It sets up only the interrupt parameters since the +** mouse shares the device ports with the Keyboard. It also activates +** the device. +** +** FORMAL PARAMETERS: +** +** iot +** irqNum +** +** IMPLICIT INPUTS: +** +** None. +** +** IMPLICIT OUTPUTS: +** +** None. +** +** function value or completion codes +** +** TRUE configuration of the kdb device was successful. +** FALSE configuration of the kdb device failed. +** +** SIDE EFFECTS: +** +** None. +**-- +*/ +int +i87307MouseConfig(bus_space_tag_t iot, + u_int irqNum ) +{ + u_int configured; + bus_space_handle_t ioh; + + configured = FALSE; /* be a pessimist */ + + if (!(bus_space_map( iot, CONNSIOADDR, NSIO_NPORTS, 0 , &ioh ))) + { + /* Now do the mouse logical device IRQ settup. + */ + NSIO_SELECT_DEV( iot, ioh, NSIO_DEV_MOUSE ); + NSIO_DEACTIVATE_DEV( iot, ioh ); + NSIO_CONFIG_IRQ( iot, ioh, irqNum, NSIO_IRQ_LEVEL | NSIO_IRQ_HIGH); + NSIO_ACTIVATE_DEV( iot, ioh ); + NSIO_CONFIG_DEBUG( iot, ioh ); + /* unmap the space so can probe later + */ + bus_space_unmap( iot, ioh, NSIO_NPORTS ); + + configured = TRUE; + } + + + return (configured); +} /* End i87307MouseConfig() */ + + + +/* +**++ +** FUNCTION NAME: +** +** i87307PrinterConfig +** +** FUNCTIONAL DESCRIPTION: +** +** This function configures the Parrel logical device on the ns87307 +** SuperIO chip. +** the device. +** +** FORMAL PARAMETERS: +** +** iot +** irqNum +** +** IMPLICIT INPUTS: +** +** None. +** +** IMPLICIT OUTPUTS: +** +** None. +** +** function value or completion codes +** +** TRUE configuration of the kdb device was successful. +** FALSE configuration of the kdb device failed. +** +** SIDE EFFECTS: +** +** None. +**-- +*/ +int +i87307PrinterConfig(bus_space_tag_t iot, + u_int irqNum ) +{ + u_int configured = FALSE; + bus_space_handle_t ioh; + + u_char value; + + if (!(bus_space_map( iot, CONNSIOADDR, NSIO_NPORTS, 0 , &ioh ))) + { + /* select the printer */ + NSIO_SELECT_DEV( iot, ioh, NSIO_DEV_LPT ); + NSIO_DEACTIVATE_DEV( iot, ioh ); + + value = NSIO_LPT_TRISTATE_DISABLE | + NSIO_LPT_CLOCK_DISABLE | + NSIO_LPT_REPORT_SPP | + NSIO_LPT_REG403_DISABLE | + NSIO_LPT_SPP_EXTENDED; + NSIO_WRITE_REG( iot, ioh, NSIO_CFG_REG0, value); + + /* set the type of interupt */ + value = NSIO_IRQ_HIGH | + NSIO_IRQ_LEVEL; + NSIO_CONFIG_IRQ( iot, ioh, irqNum,value); + + /* activate the device */ + NSIO_ACTIVATE_DEV( iot, ioh ); + + + /* unmap the space so can probe later */ + bus_space_unmap( iot, ioh, NSIO_NPORTS ); + + configured = TRUE; + } + + + return (configured); +} /* End i87307PrinterConfig() */ + + + +/* +**++ +** FUNCTION NAME: +** +** nsioConfigPrint +** +** FUNCTIONAL DESCRIPTION: +** +** This function prints out the irq, iobase etc, for the +** currently selected logical device. It is intended to +** be used for debugging only. +** +** FORMAL PARAMETERS: +** +** sc pointer to the nsio's softc structure +** +** IMPLICIT INPUTS: +** +** None. +** +** IMPLICIT OUTPUTS: +** +** None. +** +** function value or completion codes +** +** None +** +** SIDE EFFECTS: +** +** None. +** +**-- +*/ +//#ifdef DDB +void nsioConfigPrint(bus_space_tag_t nsioIot, + bus_space_handle_t nsioIoh ) +{ + u_char dev; + u_char activate; + u_char iorange; + u_char iobaseh; + u_char iobasel; + u_char irq; + u_char irqType; + u_char dma1; + u_char dma2; + u_char reg0; + + NSIO_READ_REG( nsioIot, nsioIoh, NSIO_CFG_LOGDEV, dev ); + NSIO_READ_REG( nsioIot, nsioIoh, NSIO_CFG_ACTIVATE, activate ); + NSIO_READ_REG( nsioIot, nsioIoh, NSIO_CFG_IORNGCHK, iorange ); + NSIO_READ_REG( nsioIot, nsioIoh, NSIO_CFG_IOBASEH, iobaseh ); + NSIO_READ_REG( nsioIot, nsioIoh, NSIO_CFG_IOBASEL, iobasel ); + NSIO_READ_REG( nsioIot, nsioIoh, NSIO_CFG_IRQ, irq ); + NSIO_READ_REG( nsioIot, nsioIoh, NSIO_CFG_IRQTYPE, irqType ); + NSIO_READ_REG( nsioIot, nsioIoh, NSIO_CFG_DMA1, dma1 ); + NSIO_READ_REG( nsioIot, nsioIoh, NSIO_CFG_DMA2, dma2 ); + NSIO_READ_REG( nsioIot, nsioIoh, NSIO_CFG_REG0, reg0 ); + + printf("nsio config for logical device %d\n", dev ); + printf("activate: %x\n",activate); + printf("iorange: %x\n",iorange); + printf("iobase: %x\n",(iobaseh << 8) | iobasel); + printf("irq: %x\n",irq); + printf("irqtype: %x\n",irqType); + printf("dma1: %x\n",dma1); + printf("dma2: %x\n",dma2) ; + printf("reg0: %x\n",reg0); +} +//#endif diff --git a/sys/arch/dnard/dnard/ns87307reg.h b/sys/arch/dnard/dnard/ns87307reg.h new file mode 100644 index 000000000000..886dba858131 --- /dev/null +++ b/sys/arch/dnard/dnard/ns87307reg.h @@ -0,0 +1,395 @@ +/* $NetBSD: ns87307reg.h,v 1.1 2001/05/09 15:58:07 matt Exp $ */ + +/* + * Copyright 1997 + * Digital Equipment Corporation. All rights reserved. + * + * This software is furnished under license and may be used and + * copied only in accordance with the following terms and conditions. + * Subject to these conditions, you may download, copy, install, + * use, modify and distribute this software in source and/or binary + * form. No title or ownership is transferred hereby. + * + * 1) Any source code used, modified or distributed must reproduce + * and retain this copyright notice and list of conditions as + * they appear in the source file. + * + * 2) No right is granted to use any trade name, trademark, or logo of + * Digital Equipment Corporation. Neither the "Digital Equipment + * Corporation" name nor any trademark or logo of Digital Equipment + * Corporation may be used to endorse or promote products derived + * from this software without the prior written permission of + * Digital Equipment Corporation. + * + * 3) This software is provided "AS-IS" and any express or implied + * warranties, including but not limited to, any implied warranties + * of merchantability, fitness for a particular purpose, or + * non-infringement are disclaimed. In no event shall DIGITAL be + * liable for any damages whatsoever, and in particular, DIGITAL + * shall not be liable for special, indirect, consequential, or + * incidental damages or damages for lost profits, loss of + * revenue or loss of use, whether such damages arise in contract, + * negligence, tort, under statute, in equity, at law or otherwise, + * even if advised of the possibility of such damage. + */ + +/* +**++ +** +** FACILITY: +** +** ns87307.h +** +** ABSTRACT: +** +** +** +** AUTHORS: +** +** Patrick Crilly Digital Equipment Corporation. +** +** CREATION DATE: +** +** 25-February-1997 +** +**-- +*/ + +#ifndef _NS87307REG_H +#define _NS87307REG_H + +/* +** Define TRUE/FALSE if not already defined. It +** annoys me that C doesn't do this in a standard +** header. +*/ +#ifndef TRUE +#define TRUE 1 +#define FALSE 0 +#endif + +/* +** Macro for debugging +*/ +#define NSIODEBUG +#ifdef NSIODEBUG +#define nsioDebug(x) printf x +#else +#define nsioDebug(x) +#endif + +/* +** Base address of chip. Used to configure console +** devices. +*/ +#ifndef CONNSIOADDR +#define CONNSIOADDR 0x15c +#endif + +/* +** Base Register Offsets +*/ +#define NSIO_OFFSET_INDEX 0x00 /* Index register */ +#define NSIO_OFFSET_DATA 0x01 /* Data register */ + +/* +** Number of io ports +*/ +#define NSIO_NPORTS 2 /* Number of io ports */ + +/* +** Card Configuration Registers +*/ + +#define NSIO_CFG_LOGDEV 0x07 /* Select logical device */ +#define NSIO_CFG_SID 0x20 /* Chip SID register */ + +/* +** Logical Device Configuration Registers +*/ + +#define NSIO_CFG_ACTIVATE 0x30 /* activate register */ +#define NSIO_CFG_IORNGCHK 0x31 /* I/O range check register */ +#define NSIO_CFG_IOBASEH 0x60 /* IO port base bits 15-8 */ +#define NSIO_CFG_IOBASEL 0x61 /* IO port base bits 7-0 */ +#define NSIO_CFG_IRQ 0x70 /* Interrupt Request Level */ +#define NSIO_CFG_IRQTYPE 0x71 /* Interrupt Request Type */ +#define NSIO_CFG_DMA1 0x74 /* DMA channel for DMA 0 */ +#define NSIO_CFG_DMA2 0x75 /* DMA channel for DMA 1 */ +#define NSIO_CFG_REG0 0xF0 /* First configuration register */ + +/* +** KBC Configuration Registers +*/ +#define NSIO_KBC_DATAH 0x60 /* kbc data address bits 15-8 */ +#define NSIO_KBC_DATAL 0x61 /* kbc data address bits 7-0 */ +#define NSIO_KBC_CMDH 0x62 /* kbc cmd address bits 15-8 */ +#define NSIO_KBC_CMDL 0x63 /* kbc cmd address bits 7-0 */ +#define NSIO_KBC_CFG 0xF0 /* kbc Super I/O cfg register */ + +/* +** Chip SID defines +*/ +#define NSIO_CHIP_ID_MASK 0xFC /* Mask to obtain chip id */ +#define NSIO_CHIP_ID 0xC0 /* ns87307 chip id */ + +/* +** Interrupt Type Masks +*/ +#define NSIO_IRQ_LEVEL 0x01 /* Trigger, level = 1 edge = 0 */ +#define NSIO_IRQ_HIGH 0x02 /* Int level, high = 1 low = 0 */ +#define NSIO_IRQ_LOW 0x00 + +/* +** IO Range check bit masks +*/ +#define NSIO_RNGCHK_ENABLE 0x02 /* Enable IO range checking */ +#define NSIO_RNGCHK_USE55 0x01 /* Set to read 0x55 */ + +/* +** Logical Devices +*/ +#define NSIO_DEV_KBC 0 /* keyboard controller */ +#define NSIO_DEV_MOUSE 1 /* mouse controller */ +#define NSIO_DEV_RTC 2 /* real-time clock */ +#define NSIO_DEV_FDC 3 /* floppy disk controller */ +#define NSIO_DEV_LPT 4 /* parallel port */ +#define NSIO_DEV_USI 5 /* USI = UART + inafred */ +#define NSIO_DEV_UART 6 /* UART */ +#define NSIO_DEV_GPIO 7 /* gerneral purpose I/O */ +#define NSIO_DEV_PWR 8 /* power management */ + + + +/* +** PARREL PORT CONFIGURATION +*/ + +#define NSIO_LPT_TRISTATE_DISABLE (0 << 0) /* tri-state when inactive */ +#define NSIO_LPT_TRISTATE_ENABLE (1 << 0) /* tri-state when inactive */ + +#define NSIO_LPT_CLOCK_DISABLE (0 << 1) /* report ecp mode */ +#define NSIO_LPT_CLOCK_ENABLE (1 (( 1) /* ecp/epp timeout function when active */ + + /* bit 2 reserved */ + +#define NSIO_LPT_REPORT_ECP (0 << 3) /* report ecp mode */ +#define NSIO_LPT_REPORT_SPP (1 << 3) /* report spp mode */ + +#define NSIO_LPT_REG403_DISABLE (0 << 4) /* dont respond to reg 403 */ +#define NSIO_LPT_REG403_ENABLE (1 << 4) /* respond to reg 403 */ + +#define NSIO_LPT_SPP_NORMAL (0x0<< 5) +#define NSIO_LPT_SPP_EXTENDED (0x1<< 5) +#define NSIO_LPT_EPP_V_1_7 (0x2<< 5) +#define NSIO_LPT_EPP_V_1_9 (0x3<< 5) +#define NSIO_LPT_ECP_NO_EPP (0x4<< 5) + /* bit7-5 0x5 reserved */ + /* bit7-5 0x6 reserved */ +#define NSIO_LPT_ECP_AND_EPP4 (0x7<< 5) + +/* +** As there are two devices which can be used for serial +** communication, set up defines so it's easy to configure +** the logical devices used for serial communication. +*/ +#define NSIO_DEV_COM0 NSIO_DEV_UART +#define NSIO_DEV_COM1 NSIO_DEV_USI + +/*---------------------------------------------------------------------------*/ +/* Macros used to configure logical devices */ +/*---------------------------------------------------------------------------*/ + +/* +** NSIO_READ_REG +** +** Read a configuration register. Use the currently +** selected logical device. +** +** sc pointer to nsio devices softc +** reg index of register to read +** value value read from register +*/ +#define NSIO_READ_REG( iot, ioh, reg, value ) \ +{ \ + bus_space_write_1(iot, ioh, NSIO_OFFSET_INDEX, reg ); \ + value = bus_space_read_1( iot, ioh, NSIO_OFFSET_DATA ); \ +} + +/* +** NSIO_WRITE_REG +** +** Write to a configuration register. Use the currently +** selected logical device. +** +** sc pointer to nsio devices softc +** reg index of register to read +** value value read from register +*/ +#define NSIO_WRITE_REG( iot, ioh, reg, value ) \ +{ \ + bus_space_write_1(iot, ioh, NSIO_OFFSET_INDEX, reg ); \ + bus_space_write_1( iot, ioh, NSIO_OFFSET_DATA, value ); \ +} + +/* +** NSIO_SELECT_DEV +** +** Select logDev as the current the logical device +** +** sc pointer to nsio devices softc +** reg index of register to read +** logDev logical device to select +*/ +#define NSIO_SELECT_DEV( iot, ioh, logDev ) \ + NSIO_WRITE_REG( iot, ioh, NSIO_CFG_LOGDEV, logDev ) + +/* +** NSIO_CONFIG_IRQ +** +** Set the irq number and triggering for the currently +** selected logical device. If irqNum is unknown +** the number won't be set and the device will be left +** with it's default value. +** +** sc pointer to nsio devices softc +** irqNum irq number to set +** irqType trigger flags e.g. edge/level, high/low +*/ +#define NSIO_CONFIG_IRQ( iot, ioh, irqNum, irqType ) \ +{ \ + if ( irqNum != IRQUNK ) \ + { \ + NSIO_WRITE_REG( iot, ioh, NSIO_CFG_IRQ, irqNum ); \ + } \ + NSIO_WRITE_REG( iot, ioh, NSIO_CFG_IRQTYPE, irqType ); \ +} + +/* +** NSIO_CONFIG_KBCCMD +** +** Set the io base for the currently selected logical device. +** +** sc pointer to nsio devices softc +** ioBase address to set io base to +*/ +#define NSIO_CONFIG_IOBASE( iot, ioh, ioBase ) \ +{ \ + NSIO_WRITE_REG( iot, ioh, NSIO_CFG_IOBASEH, \ + (unsigned char)(((ioBase) >> 8) & 0xff) ); \ + NSIO_WRITE_REG( iot, ioh, NSIO_CFG_IOBASEL, \ + (unsigned char)(((ioBase) & 0xff ) ); \ +} + +/* +** NSIO_CONFIG_KBCDATA +** +** Set the data base for the keyboard. The keyboard +** controller must be the currently selected logical device. +** +** sc pointer to nsio devices softc +** dataBase address to set data base to +*/ + +#define NSIO_CONFIG_KBCDATA( iot, ioh, dataBase ) \ +{ \ + NSIO_WRITE_REG( iot, ioh, NSIO_KBC_DATAH, \ + (unsigned char)(((dataBase) >> 8) & 0xff) ); \ + NSIO_WRITE_REG( iot, ioh, NSIO_KBC_DATAL, \ + (unsigned char)((dataBase) & 0xff ) ); \ +} + +/* +** NSIO_CONFIG_KBCCMD +** +** Set the command base for the keyboard. The keyboard +** controller must be the currently selected logical device. +** +** sc pointer to nsio devices softc +** cmdBase address to set command base to +*/ + +#define NSIO_CONFIG_KBCCMD( iot, ioh, cmdBase ) \ +{ \ + NSIO_WRITE_REG( iot, ioh, NSIO_KBC_CMDH, \ + (unsigned char)(((cmdBase) >> 8) & 0xff) ); \ + NSIO_WRITE_REG( iot, ioh, NSIO_KBC_CMDL, \ + (unsigned char)((cmdBase) & 0xff ) ); \ +} + +/* +** NSIO_ACTIVATE_DEV +** +** Activate the currently selected logical device. +** +** sc pointer to nsio devices softc +*/ + +#define NSIO_ACTIVATE_DEV( iot, ioh ) \ +{ \ + NSIO_WRITE_REG( iot, ioh, NSIO_CFG_ACTIVATE, (0x01) ); \ +} + +/* +** NSIO_DEACTIVATE_DEV +** +** Deactivate the currently selected logical device. +** +** sc pointer to nsio devices softc +*/ + +#define NSIO_DEACTIVATE_DEV( iot, ioh ) \ +{ \ + NSIO_WRITE_REG( iot, ioh, NSIO_CFG_ACTIVATE, (0x00) ); \ +} + + +/* +** NSIO_CONFIG_DEBUG +** +** Print out configuration information for the device +** +** sc pointer to nsio devices softc +*/ +#ifdef DDB +#define NSIO_CONFIG_DEBUG( iot, ioh ) \ +{ \ + /* nsioConfigPrint( iot, ioh ); */ \ +} +#else +#define NSIO_CONFIG_DEBUG( iot, ioh ) +#endif + +/* +** NSIO_CONFIG_KBCDEBUG +** +** Print out configuration information for the keyboard device +** +** sc pointer to nsio devices softc +*/ +#ifdef DDB +#define NSIO_CONFIG_KBCDEBUG( iot, ioh ) \ +{ \ + u_char cmdL; \ + u_char cmdH; \ + /* nsioConfigPrint( iot, ioh ); */ \ + NSIO_READ_REG( iot, ioh, NSIO_KBC_CMDH, cmdH ); \ + NSIO_READ_REG( iot, ioh, NSIO_KBC_CMDH, cmdL ); \ + printf("kbc command: %x\n", (((u_short)(cmdH)) << 8)| cmdL ); \ +} +#else +#define NSIO_CONFIG_KBCDEBUG( iot, ioh ) +#endif + +/* Functions to help configure the ns87307 logical devices. +*/ +int i87307KbdConfig __P((bus_space_tag_t iot, + u_int comBase, + u_int irqNum )); +int i87307MouseConfig __P((bus_space_tag_t iot, + u_int irqNum )); + + +void nsioConfigPrint(bus_space_tag_t nsioIot, bus_space_handle_t nsioIoh ); + +#endif /* _NS87307REG_H */ diff --git a/sys/arch/dnard/dnard/profile.c b/sys/arch/dnard/dnard/profile.c new file mode 100644 index 000000000000..e5fbec44dc89 --- /dev/null +++ b/sys/arch/dnard/dnard/profile.c @@ -0,0 +1,719 @@ +/* $NetBSD: profile.c,v 1.1 2001/05/09 15:58:07 matt Exp $ */ + +/* + * Copyright 1997 + * Digital Equipment Corporation. All rights reserved. + * + * This software is furnished under license and may be used and + * copied only in accordance with the following terms and conditions. + * Subject to these conditions, you may download, copy, install, + * use, modify and distribute this software in source and/or binary + * form. No title or ownership is transferred hereby. + * + * 1) Any source code used, modified or distributed must reproduce + * and retain this copyright notice and list of conditions as + * they appear in the source file. + * + * 2) No right is granted to use any trade name, trademark, or logo of + * Digital Equipment Corporation. Neither the "Digital Equipment + * Corporation" name nor any trademark or logo of Digital Equipment + * Corporation may be used to endorse or promote products derived + * from this software without the prior written permission of + * Digital Equipment Corporation. + * + * 3) This software is provided "AS-IS" and any express or implied + * warranties, including but not limited to, any implied warranties + * of merchantability, fitness for a particular purpose, or + * non-infringement are disclaimed. In no event shall DIGITAL be + * liable for any damages whatsoever, and in particular, DIGITAL + * shall not be liable for special, indirect, consequential, or + * incidental damages or damages for lost profits, loss of + * revenue or loss of use, whether such damages arise in contract, + * negligence, tort, under statute, in equity, at law or otherwise, + * even if advised of the possibility of such damage. + */ + +/* + * The fiq based profiler. + */ + +#include "profiler.h" + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include +#include +#include + +#define PROFILER_DEBUG 1 + +#define countPerTick 500 /* TIMER_FREQ/10000 10 kHz timer */ + +/* Processor Status Defines */ +#define STATUS_MODE_MASK 0x1f +#define USER_MODE 0x10 +#define FIQ_MODE 0x11 +#define IRQ_MODE 0x12 +#define SVC_MODE 0x13 +#define ABORT_MODE 0x17 +#define UNDEF_MODE 0x1b +#define SYS_MODE 0x1f + +/* software controller + */ +struct profiler_sc +{ + int state; +#define PROF_OPEN 0x01 +#define PROF_PROFILING 0x02 +} prof_sc; + +/* + * GLOBAL DATA + */ + +/* I need my own stack space for the hat */ +#define HATSTACKSIZE 1024 /* size of stack used during a FIQ */ +static unsigned char hatStack[HATSTACKSIZE]; /* actual stack used + * during a FIQ + */ +/* Pointer to the list of hash tables. + * A backup table is created for every table malloced, this + * is used so that we don't miss samples while copying the + * data out. Thus the actual number of tables in the array is twice + * what nhashTables says. + */ +struct profHashTable *profTable; +struct profHashTable *phashTables[2]; +int nhashTables; + +/* + * FORWARD DECLARATIONS + */ +static void profFiq(int x); +static void profHatWedge(int nFIQs); +void profStop(void); +void profStart(struct profStartInfo *); +static void profEnter(struct profHashTable * , unsigned int); +void displayTable(struct profHashTable * ); + + +void +profilerattach(n) + int n; +{ + /* reset the profiler state */ + prof_sc.state = 0; +} + +/* + * Open the profiling devicee. + * Returns + * ENXIO for illegal minor device + * ie. if the minor device number is not 0. + * EBUSY if file is open by another process. + * EROFS if attempt to open in write mode. + */ +int +profopen(dev, flag, mode, p) + dev_t dev; + int flag; + int mode; + struct proc *p; +{ + + /* check that the minor number is correct. */ + if (minor(dev) >= NPROFILER) + { + return ENXIO; + } + + /* check that the device is not already open. */ + if (prof_sc.state && PROF_OPEN) + { + return EBUSY; + } + + /* check that the flag is set to read only. */ + if (!(flag && FWRITE)) + { + return EROFS; + } + /* flag the device as open. */ + prof_sc.state |= PROF_OPEN; + nhashTables = 0; + phashTables[0] = phashTables[1] = NULL; + return 0; +} + +/* + * Close the descriptor. + * + */ +int +profclose(dev, flag, mode, p) + dev_t dev; + int flag; + int mode; + struct proc *p; +{ + /* clear the state, and stop profiling if + * it is happening. + */ + profStop(); + prof_sc.state &= ~PROF_OPEN; + return 0; +} + +int +profread(dev, uio, flags) + dev_t dev; + struct uio *uio; + int flags; +{ + int error; + int real, backup; + + /* must be profiling to read */ + if (!(prof_sc.state & PROF_PROFILING)) + { + error = EINVAL; + } + else + { + if (uio->uio_resid != sizeof(struct profHashHeader) + + profTable->hdr.tableSize * sizeof(struct profHashEntry)) + { + printf("profile read size is incorrect!"); + error = EINVAL; + } + else + { + /* first work out which table is currently being used. + */ + if (profTable == phashTables[0]) + { + real = 0; + backup = 1; + } + else + { + if (profTable == phashTables[1]) + { + real = 1; + backup = 0; + } + else + { + panic("profiler lost buffer\n"); + } + } + /* now initialise the backup copy before switching over. + */ + memset(phashTables[backup]->entries, 0, + profTable->hdr.tableSize * sizeof(struct profHashEntry)); + + + /* now initialise the header */ + phashTables[backup]->hdr.tableSize = phashTables[real]->hdr.tableSize; + phashTables[backup]->hdr.entries = phashTables[backup]->hdr.last + = phashTables[real]->hdr.entries; + phashTables[backup]->hdr.samples = 0; + phashTables[backup]->hdr.missed = 0; + phashTables[backup]->hdr.fiqs = 0; + phashTables[backup]->hdr.pid = phashTables[real]->hdr.pid; + phashTables[backup]->hdr.mode = phashTables[real]->hdr.mode; + + /* ok now swap over. + * I don't worry about locking the fiq while I change + * this, at this point it won't matter which table the + * fiq reads. + */ + profTable = phashTables[backup]; + + /* don't want to send the pointer, + * make assumption that table follows the header. + */ + if ( (error = uiomove(phashTables[real], + sizeof(struct profHashHeader), uio)) + != 0) + { + printf("uiomove failed error is %d\n", error); + } + else + { + if ( (error = uiomove(phashTables[real]->entries, + phashTables[real]->hdr.tableSize * + sizeof(struct profHashEntry), uio)) + != 0) + { + printf("uiomove failed error is %d\n", error); + } + } + } + } + return error; +} + +/* + * PROFIOSTART Start Profiling + * PROFIOSTOP Stop Profiling + */ +static int profcount = 0; +static int ints = 0; +int +profioctl(dev, cmd, data, flag, p) + dev_t dev; + u_long cmd; + caddr_t data; + int flag; + struct proc *p; +{ + int error = 0; + struct profStartInfo *info = (struct profStartInfo *) data; + + switch (cmd) + { + case PROFIOSTART : + profStart(info); + break; + case PROFIOSTOP : + profStop(); + break; + default : + error = EINVAL; + break; + } + return error; +} + +/* start profiling, returning status information in the + * profStartInfo structure. + * + * presumes pid is running, does no checks here. + */ +void +profStart(struct profStartInfo *info) +{ + unsigned int savedInts; + char *buffer; + + /* can't already be sampling */ + if ( prof_sc.state & PROF_PROFILING ) + { + info->status = ALREADY_SAMPLING; + return ; + } + + /* sanity check that the table sizes are logical */ + if (info->entries > info->tableSize) + { + info->status = BAD_TABLE_SIZE; + return ; + } + + /* now sanity check that we are sampling either the + * kernel or a pid or both. + */ + if ( !(info->mode & SAMPLE_MODE_MASK) ) + { + info->status = ILLEGAL_COMMAND; + return ; + } + + /* alloc two hash tables. */ + buffer = malloc(sizeof(struct profHashTable) + + info->tableSize * sizeof(struct profHashEntry), + M_DEVBUF, M_NOWAIT); + if ( (buffer == NULL) ) + { + info->status = NO_MEMORY; + return; + } + phashTables[0] = (struct profHashTable *) buffer; + phashTables[0]->entries = (struct profHashEntry *) + ( buffer + sizeof(struct profHashTable)); + + buffer = malloc(sizeof(struct profHashTable) + + info->tableSize * sizeof(struct profHashEntry), + M_DEVBUF, M_NOWAIT); + if ( (buffer == NULL) ) + { + free(phashTables[0], M_DEVBUF); + info->status = NO_MEMORY; + return; + } + phashTables[1] = (struct profHashTable *) buffer; + phashTables[1]->entries = (struct profHashEntry *) + ( buffer + sizeof(struct profHashTable)); + + memset(phashTables[0]->entries, 0, + info->tableSize * sizeof(struct profHashEntry)); + memset(phashTables[1]->entries, 0, + info->tableSize * sizeof(struct profHashEntry)); + + /* now initialise the header */ + profTable = phashTables[0]; + profTable->hdr.tableSize = info->tableSize; + profTable->hdr.entries = profTable->hdr.last = info->entries; + profTable->hdr.samples = 0; + profTable->hdr.missed = 0; + profTable->hdr.fiqs = 0; + profTable->hdr.pid = info->pid; + profTable->hdr.mode = info->mode; + + /* now let the pigeons loose. */ + savedInts = disable_interrupts(I32_bit | F32_bit); + prof_sc.state |= PROF_PROFILING; + hatClkOn(countPerTick, + profFiq, + (int)&prof_sc, + hatStack + HATSTACKSIZE - sizeof(unsigned), + profHatWedge); + restore_interrupts(savedInts); +} + +void +profStop(void) +{ + unsigned int savedInts; + int spl; + + savedInts = disable_interrupts(I32_bit | F32_bit); + hatClkOff(); + restore_interrupts(savedInts); + + spl = splbio(); + /* only free the buffer's if we were profiling, + * who cares if we were not, won't alert any one. + */ + if (prof_sc.state & PROF_PROFILING) + { + /* now free both buffers. */ + free(phashTables[0], M_DEVBUF); + free(phashTables[1], M_DEVBUF); + } + phashTables[0] = phashTables[1] = NULL; + prof_sc.state &= ~PROF_PROFILING; + splx(spl); + +} + +/* +**++ +** FUNCTIONAL DESCRIPTION: +** +** profFiq +** +** This is what the HAT clock calls. This call drives +** the timeout queues, which in turn drive the state machines +** +** Be very carefully when calling a timeout as the function +** that is called may in turn do timeout/untimeout calls +** before returning +** +** FORMAL PARAMETERS: +** +** int x - not used +** +** IMPLICIT INPUTS: +** +** nill +** +** IMPLICIT OUTPUTS: +** +** nill +** +** FUNCTION VALUE: +** +** nill +** +** SIDE EFFECTS: +** +** a timeout may be called if it is due +**-- +*/ +static void +profFiq(int x) +{ + int i; + int *ip; /* the fiq stack pointer */ + unsigned int spsr, stacklr; /* the link register, off the stack. */ + + + /* get the link register and see where we came from. + * We do this by getting the stack pointer using, + * an inline assembler instruction and then going 9 + * words up to get the return address from the fiq. + * + * NOTE: the stack will change if more local variables + * are added so beware of modifications to this + * function. + * the fiq.S handler puts the following on the stack + * stmfd sp!, {r0-r3, lr} + * then this function does + * mov ip, sp + * stmfd sp!, {r4, fp, ip, lr, pc} + * or some variant of this. + * + * instead of using sp we can use ip, the saved stack pointer + * and be done with the chance of sp changing around on us. + * + * so by the time we get here we have a stack that looks like. + * (see pg 4-23, ARM programming Techniques doco for description + * on stm instructions.) + * lr-fiq (we want this one). + * r3-fiq + * r2-fiq + * r1-fiq + * ip--> r0-fiq + * pc-prof + * lr-prof + * ip-prof + * fp-prof + * sp--> r4-prof + * the sp by the time we get to it will point to r4 at the + * bottom of the stack. So we go 9 up to get the lr we want. + * or even better we have ip pointing to r0 and we can go 4 up + * to get the saved link register. + * + * We are safer this way because fiq.S is coded assembler, we are + * at the mercy of the assembler for our stack. + * + */ + asm("mov %0, ip" : "=r" (ip) : ); + stacklr = *(ip+4); + + /* get the spsr register + */ + asm("mrs %0, spsr" : "=r" (spsr) : ); + + /* now check whether we want this sample. + * NB. We place kernel and user level samples in the + * same table. + */ + if ( (profTable->hdr.mode & SAMPLE_PROC) && + ((spsr & STATUS_MODE_MASK) == USER_MODE) ) + { + if ( curproc->p_pid == profTable->hdr.pid ) + { + profEnter(profTable, stacklr-4); + } + } + + if ( profTable->hdr.mode & SAMPLE_KERN ) + { + if ( ((spsr & STATUS_MODE_MASK) == SVC_MODE)/* || + ((spsr & STATUS_MODE_MASK) == IRQ_MODE)*/ ) + { + /* Note: the link register will be two instructions, + * ahead of the "blamed" instruction. This is actually + * a most likely case and might not actually highlight the + * exact cause of problems, some post processing intelligence + * will be required to make use of this data. + */ + profEnter(profTable, stacklr-4); + } + } + /* increment the samples counter */ + profTable->hdr.fiqs++; +} + +/* +**++ +** FUNCTIONAL DESCRIPTION: +** +** profHatWedge +** +** Called if the HAT timer becomes clogged/wedged. Not +** used by this driver, we let upper layers recover +** from this condition +** +** FORMAL PARAMETERS: +** +** int nFIQs - not used +** +** IMPLICIT INPUTS: +** +** nill +** +** IMPLICIT OUTPUTS: +** +** nill +** +** FUNCTION VALUE: +** +** nill +** +** SIDE EFFECTS: +** +** nill +**-- +*/ +static void +profHatWedge(int nFIQs) +{ + #ifdef PROFILER_DEBUG + printf("profHatWedge: nFIQ = %d\n",nFIQs); + #endif +} + +/* Enter the data in the table. + * + * To reduce the time taken to find samples with time + * an eviction algorithm is implemented. + * When a new entry in the overflow area is required + * the first entry in the hash table is copied there + * and the new entry placed as the hash table entry. The + * displaced entry will then be the first entry accessed in + * the table. + */ +static void +profEnter(struct profHashTable *table, unsigned int lr) +{ + unsigned int entries, hashShift, index, count; + struct profHashEntry *sample; + struct profHashEntry *first; + struct profHashEntry *prev; + struct profHashEntry tmpEntry; + int tmpIndex; + + /* work out how many bits + * are required to hash the given size. + */ + entries = table->hdr.entries - 1; + hashShift = 0; + do + { + entries = entries << 1; + hashShift ++; + } while (!(entries & 0x80000000)); + + /* enter the pc in the table. */ + /* remove redundant bits. + * and save the count offset bits + */ + lr = lr >> REDUNDANT_BITS; + count = lr & COUNT_BIT_MASK; + lr = lr >> COUNT_BITS; + + /* this is easier than working out how + * many bits to or, based on the hashShift. + * maybe it would be better to work out at + * the start and save time during the fiq. + */ + index = (lr << hashShift) >> hashShift; + + first = sample = &table->entries[index]; + /* now loop until we either find the entry + * or the next free space. + */ + while ( (sample->pc != lr) && (table->hdr.last < table->hdr.tableSize) ) + { + if (sample->pc == 0) + { + /* go ahead and stick it in */ + sample->pc = lr; + } + else + { + if (sample->next != 0) + { + /* move along and continue */ + prev = sample; + sample = &table->entries[sample->next]; + } + else + { + /* create a new entry if available */ + if (table->hdr.last < table->hdr.tableSize) + { + sample = &table->entries[table->hdr.last]; + /* copy the first sample into the new + * field. + */ + memcpy(sample, first, sizeof(struct profHashEntry)); + /* now update the new entry in the first position. + */ + first->pc = lr; + first->next = table->hdr.last; + first->counts[0] = 0; + first->counts[1] = 0; + first->counts[2] = 0; + first->counts[3] = 0; + table->hdr.last++; + /* update the sample pointer so that we + * can insert the count. + */ + sample = first; + } + } + } + } + + /* check if we need to do an eviction. */ + if (sample != first) + { + /* copy the sample out of the table. */ + memcpy(&tmpEntry, sample, sizeof(struct profHashEntry)); + /* remove the sample from the chain. */ + tmpIndex = prev->next; + prev->next = sample->next; + /* now insert it at the beginning. */ + memcpy(sample, first, sizeof(struct profHashEntry)); + memcpy(first, &tmpEntry, sizeof(struct profHashEntry)); + /* now make the new first entry point to the old + * first entry. + */ + first->next = tmpIndex; + } + + /* must now check the lr + * to see if the table is full. + */ + if (sample->pc == lr) + { + /* update the count */ + sample->counts[count]++; + table->hdr.samples++; + } + else + { + table->hdr.missed++; + } +} + +void +displayTable(struct profHashTable *table) +{ + int i; + struct profHashEntry *sample; + char buff[100] = ".............................................\n"; + + for (i=0; i < table->hdr.tableSize; i++) + { + sample = &table->entries[i]; + if ((i * table->hdr.tableSize) >= table->hdr.entries) + { + printf("%s", buff); + buff[0] = '\0'; + } + printf("i = %d, pc = 0x%x, next = %d, counts %d %d %d %d\n", + i, sample->pc, sample->next, sample->counts[0], + sample->counts[1], sample->counts[2], sample->counts[3]); + } + return; +} diff --git a/sys/arch/dnard/dnard/scr.c b/sys/arch/dnard/dnard/scr.c new file mode 100644 index 000000000000..eb6e965a7d5b --- /dev/null +++ b/sys/arch/dnard/dnard/scr.c @@ -0,0 +1,4239 @@ +/* $NetBSD: scr.c,v 1.1 2001/05/09 15:58:07 matt Exp $ */ + +/* + * Copyright 1997 + * Digital Equipment Corporation. All rights reserved. + * + * This software is furnished under license and may be used and + * copied only in accordance with the following terms and conditions. + * Subject to these conditions, you may download, copy, install, + * use, modify and distribute this software in source and/or binary + * form. No title or ownership is transferred hereby. + * + * 1) Any source code used, modified or distributed must reproduce + * and retain this copyright notice and list of conditions as + * they appear in the source file. + * + * 2) No right is granted to use any trade name, trademark, or logo of + * Digital Equipment Corporation. Neither the "Digital Equipment + * Corporation" name nor any trademark or logo of Digital Equipment + * Corporation may be used to endorse or promote products derived + * from this software without the prior written permission of + * Digital Equipment Corporation. + * + * 3) This software is provided "AS-IS" and any express or implied + * warranties, including but not limited to, any implied warranties + * of merchantability, fitness for a particular purpose, or + * non-infringement are disclaimed. In no event shall DIGITAL be + * liable for any damages whatsoever, and in particular, DIGITAL + * shall not be liable for special, indirect, consequential, or + * incidental damages or damages for lost profits, loss of + * revenue or loss of use, whether such damages arise in contract, + * negligence, tort, under statute, in equity, at law or otherwise, + * even if advised of the possibility of such damage. + */ + +/* +**++ +** +** FACILITY: +** +** Driver for smart card +** +** ABSTRACT: +** +** The driver provides access to a Smart Card for the DNARD. +** +** There is no Smart Card silicon. Several i/o pins +** connect to the pads on the Smart Card, and the driver is +** is responsible for driving the signals in accordance with +** ISO 7816-3 (the Smart Card spec) +** +** This driver puts a high load on the system due to the need +** to interrupt at a high rate (up to 50 Khz) during bit detection. +** +** +** The driver is dived into the standard top half ioctl, and bottom +** half interupt. The interrupt is FIQ, which requires its own stack. +** disable_interrupts and restore_interrupts must be used to protect from +** a FIQ. Since splxxx functions do not use this, the bottom half cannot +** use any standard functions (ie like wakeup, timeout, etc. +** Thus the communication from the bottom half +** to the top half uses a "done" bit called masterDone. This bit +** is set by the master state machine when all bottom half work is +** complete. The top half checks/sleeps on this masterDone bit. +** +** The FIQ is driven by Timer 2 (T2)in the sequoia. All times are +** referenced to T2 counts. +** +** The bottom half is done as a several linked state machines. +** The top level machine is the maserSM (ie master State Machine). This +** machine calls mid level protocol machines, ie ATRSM (Answer To Reset +** State Machine), t0SendSM (T=0 Send State Machine), and t0RecvSM (T=0 Recv +** State Machine). These mid level protocol machines in turn call low level +** bit-bashing machines, ie coldResetSM, t0SendByteSM, T0RecvByteSM. +** +** Smart Cards are driven in a command/response mode. Ie you issue a command +** to the Smart Card and it responds. This command/response mode is reflected +** in the structure of the driver. Ie the ioctl gets a command, it +** gives it to the bottom half to execute and goes to sleep. The bottom half +** executes the command and gets the response to from the card and then +** notifies the top half that it has completed. Commands usually complete +** in under a second. +** +** +** +** AUTHORS: +** +** E. J. Grohn +** Digital Equipment Corporation. +** +** CREATION DATE: +** +** 27-July-97 +** +**-- +*/ + +/* +** +** INCLUDE FILES +** +*/ + +#include "opt_ddb.h" + +#include +#include +#include +/* #include */ +/* #include */ +#include +/* #include */ +#include +/* #include */ +/* #include */ +#include +/* #include */ +#include +#include +#include +#include + + +/* SCR_DEBUG is the master switch for turning on debugging */ +//#define SCR_DEBUG 1 +#ifdef SCR_DEBUG + #define KERNEL_DEBUG + #ifdef DDB + #define DEBUGGER printf("file = %s, line = %d\n",__FILE__,__LINE__);Debugger() + #else + #define DEBUGGER panic("file = %s, line = %d\n",__FILE__,__LINE__); + #endif +#else + #define DEBUGGER +#endif + + +#include +//#include +#include +#include +#include +#include + + + + +/* +** +** MACRO DEFINITIONS +** +*/ + + +#define scr_lcr scr_cfcr + +/* +** Macro to extract the minor device number from the device Identifier +*/ +#define SCRUNIT(x) (minor(x)) + +/* +** Macros to clear/set/test bit flags. +*/ +#define SET(t, f) (t) |= (f) +#define CLR(t, f) (t) &= ~(f) +#define ISSET(t, f) ((t) & (f)) +#define ISCLR(t, f) ( ((t) & (f)) == 0) + + +/* +** some macros to assist in debugging +*/ +#ifdef SCR_DEBUG + #define KERNEL_DEBUG + #define ASSERT(f) do { if (!(f)) { DEBUGGER;} }while(0) + #define TOGGLE_TEST_PIN() scrToggleTestPin() + #define INVALID_STATE_CMD(sc,state,cmd) invalidStateCmd(sc,state,cmd,__LINE__); +#else + #define ASSERT(f) + #define TOGGLE_TEST_PIN() + //#define INVALID_STATE_CMD(sc,state,cmd) panic("scr: invalid state/cmd, sc = %X, state = %X, cmd = %X, line = %d\n",sc,state,cmd,__LINE__); + #define INVALID_STATE_CMD(sc,state,cmd) sc->bigTrouble = TRUE; + +#endif + +#ifndef FALSE + #define FALSE 0 +#endif + +#ifndef TRUE + #define TRUE 1 +#endif + + + + + +/* +** The first and last bytes of the debug control variables is reserved for +** the standard KERN_DEBUG_xxx macros, so we can tailor the middle two bytes +*/ +#define SCRPROBE_DEBUG_INFO 0x00000100 +#define SCRATTACH_DEBUG_INFO 0x00000200 +#define SCROPEN_DEBUG_INFO 0x00000400 +#define SCRCLOSE_DEBUG_INFO 0x00000800 +#define SCRREAD_DEBUG_INFO 0x00001000 +#define SCRWRITE_DEBUG_INFO 0x00002000 +#define SCRIOCTL_DEBUG_INFO 0x00004000 +#define MASTER_SM_DEBUG_INFO 0x00008000 +#define COLD_RESET_SM_DEBUG_INFO 0x00010000 +#define ATR_SM_DEBUG_INFO 0x00020000 +#define T0_RECV_BYTE_SM_DEBUG_INFO 0x00040000 +#define T0_SEND_BYTE_SM_DEBUG_INFO 0x00080000 +#define T0_RECV_SM_DEBUG_INFO 0x00100000 +#define T0_SEND_SM_DEBUG_INFO 0x00200000 + + +int scrdebug = //SCRPROBE_DEBUG_INFO | + //SCRATTACH_DEBUG_INFO | + //SCROPEN_DEBUG_INFO | + //SCRCLOSE_DEBUG_INFO | + //SCRREAD_DEBUG_INFO | + //SCRWRITE_DEBUG_INFO | + //SCRIOCTL_DEBUG_INFO | + //MASTER_SM_DEBUG_INFO | + //COLD_RESET_SM_DEBUG_INFO| + //ATR_SM_DEBUG_INFO | + //T0_RECV_BYTE_SM_DEBUG_INFO | + //T0_SEND_BYTE_SM_DEBUG_INFO | + //T0_RECV_SM_DEBUG_INFO | + //T0_SEND_SM_DEBUG_INFO | + 0; + + + + + + +/* +** the bottom half of the driver is done as several linked state machines +** below are all the states of the machines, and the commands that are +** sent to each machine +*/ + +/* commands to Master State Machine from ioctl */ +#define mcOn 0x0100 /* ioctl on */ +#define mcT0DataSend 0x0102 /* ioctl send */ +#define mcT0DataRecv 0x0103 /* ioctl recv */ + +/* commands to Master State Machine from lower state machines */ +#define mcColdReset 0x0105 /* cold reset finished */ +#define mcATR 0x0106 /* ATR has finished */ +#define mcT0Send 0x0108 /* T0 send finished */ +#define mcT0Recv 0x010a /* T0 recv finished */ + +/* states in Master state machine (ms = Master State) */ +#define msIdleOff 0x0200 /* in idle state, card powered off */ +#define msColdReset 0x0201 /* turning on power, clock, reset */ +#define msATR 0x0202 /* getting ATR sequence from card */ +#define msIdleOn 0x0203 /* idle, put card powered on */ +#define msT0Send 0x0204 /* sending T0 data */ +#define msT0Recv 0x0205 /* recving T0 data */ + + + + +/* commands to T0 send state machine */ +#define t0scStart 0x0300 /* start */ +#define t0scTWorkWaiting 0x0301 /* work waiting timeout */ + +/* states in T0 send state machine */ +#define t0ssIdle 0x0400 /* idle state */ +#define t0ssSendHeader 0x0401 /* send 5 header bytes */ +#define t0ssRecvProcedure 0x0402 /* wait for procedure byte */ +#define t0ssSendByte 0x0403 /* send 1 byte */ +#define t0ssSendData 0x0404 /* send all bytes */ +#define t0ssRecvSW1 0x0405 /* wait for sw1 */ +#define t0ssRecvSW2 0x0406 /* wait for sw2 */ + + + + + +/* commands to T0 recv state machine */ +#define t0rcStart 0x0500 /* start */ +#define t0rcTWorkWaiting 0x0501 /* work waiting timeout */ + +/* states in T0 recv state machine */ +#define t0rsIdle 0x0600 /* idle state */ +#define t0rsSendHeader 0x0601 /* send 5 header bytes */ +#define t0rsRecvProcedure 0x0602 /* wait for procedure byte */ +#define t0rsRecvByte 0x0603 /* recv 1 byte */ +#define t0rsRecvData 0x0604 /* recv all bytes */ +#define t0rsRecvSW1 0x0605 /* wait for sw1 */ +#define t0rsRecvSW2 0x0606 /* wait for sw2 */ + + + +/* commands to Cold Reset state machine */ +#define crcStart 0x0900 /* start */ +#define crcT2 0x0902 /* timeout T2 ISO 7816-3, P6, Figure 2 */ + +/* states in cold reset state machine */ +#define crsIdle 0x0a00 /* idle */ +#define crsT2Wait 0x0a01 /* wait for T2 ISO 7816-3.P6. Figure 2 */ + + + + + +/* commands to Answer To Reset (ATR) state machine */ +#define atrcStart 0x0b00 /* start */ +#define atrcT3 0x0b04 /* got T3 timeout */ +#define atrcTWorkWaiting 0x0b05 /* work waiting timeout */ + +/* states in Answer To Reset (ATR) state machine */ +#define atrsIdle 0x0c00 /* idle */ +#define atrsTS 0x0c01 /* looking for TS, (initial bytes) */ +#define atrsT0 0x0c02 /* looking for T0, (format bytes) */ +#define atrsTABCD 0x0c03 /* looking for TAx (interface bytes)*/ +#define atrsTK 0x0c04 /* looking for TK (history bytes) */ +#define atrsTCK 0x0c05 /* looking for TCK (check bytes */ + + +/* commands to T0 Recv Byte state machine */ +#define t0rbcStart 0x0d00 /* start */ +#define t0rbcAbort 0x0d01 /* abort */ +#define t0rbcTFindStartEdge 0x0d02 /* start bit edge search */ +#define t0rbcTFindStartMid 0x0d03 /* start bit mid search */ +#define t0rbcTClockData 0x0d04 /* data bit search */ +#define t0rbcTErrorStart 0x0d05 /* start to send error */ +#define t0rbcTErrorStop 0x0d06 /* stop sending error */ + +/* states in T0 Recv Byte state machine */ +#define t0rbsIdle 0x0e00 /* idle */ +#define t0rbsFindStartEdge 0x0e01 /* looking for start bit */ +#define t0rbsFindStartMid 0x0e02 /* looking for start bit */ +#define t0rbsClockData 0x0e03 /* looking for data bits */ +#define t0rbsSendError 0x0e04 /* output error bit */ + + + + +/* commands to T0 Send Byte state machine */ +#define t0sbcStart 0x0f00 /* start the machine */ +#define t0sbcAbort 0x0f01 /* abort the machine */ +#define t0sbcTGuardTime 0x0f02 /* guard time finished */ +#define t0sbcTClockData 0x0f03 /* clock time finished */ +#define t0sbcTError 0x0f04 /* start to send error */ +#define t0sbcTResend 0x0f05 /* if parity error, then wait unfill we can re-send */ + + + +/* states in T0 Send Byte state machine */ +#define t0sbsIdle 0x1000 /* idle */ +#define t0sbsWaitGuardTime 0x1001 /* wait for guard time to finish */ +#define t0sbsClockData 0x1002 /* clocking out data & parity */ +#define t0sbsWaitError 0x1003 /* waiting for error indicator */ +#define t0sbsWaitResend 0x1004 /* waiting to start re-send if error */ + + + + +/* +** generic middle level state machine commands +** sent by T0 Send Byte & T0 recv Byte to T0 Send and T0 Recv +*/ +#define gcT0RecvByte 0x1100 /* receive finished */ +#define gcT0RecvByteErr 0x1101 /* receive got error */ +#define gcT0SendByte 0x1102 /* send finished */ +#define gcT0SendByteErr 0x1103 /* send got error */ + + + + + + +/* +** +** below are definitions associated with Smart Card +** +*/ + + +/* +** Frequency of clock sent to card +** NCI's card is running at 1/2 freq, so in debug we can make +** use of this to toggle more debug signals and still be within +** interrupt time budget +*/ +#ifdef SCR_DEBUG + #define CARD_FREQ_DEF (3579000/2) +#else + #define CARD_FREQ_DEF (3579000) +#endif + + + +/* byte logic level and msb/lsb coding */ +#define CONVENTION_UNKOWN 0 +#define CONVENTION_INVERSE 1 +#define CONVENTION_DIRECT 2 +#define CONVENIONT_INVERSE_ID 0x3f +#define CONVENTION_DIRECT_FIX 0x3b +#define CONVENTION_DIRECT_ID 0x23 + + +/* macros that help us set the T2 count for bit bashing */ +#define CLK_COUNT_START (((372 * TIMER_FREQ) / sc->cardFreq) /5) +#define CLK_COUNT_DATA (((372 * TIMER_FREQ) / sc->cardFreq) ) +#define START_2_DATA 5 + +/* default settings to use if not specified in ATR */ +#define N_DEFAULT 0 /* guard time default */ +#define Fi_DEFAULT 372 /* clock rate conversion default */ +#define Di_DEFAULT 1 /* bit rate adjustment factor */ +#define Wi_DEFAULT 10 /* waiting time */ + + +/* table for clock rate adjustment in ATR */ +int FI2Fi[16] = {372, 372, 558, 744,1116,1488,1860, 0, + 0, 512, 768,1024,1536,2048, 0, 0}; + +/* table for bit rate adjustment in ATR*/ +int DI2Di[16] = { 0, 1, 2, 4, 8, 16, 32, 0, + 12, 20, 0, 0, 0, 0, 0, 0}; + +/* values of atrY in the ATR sequence*/ +#define ATR_Y_TA 0x10 +#define ATR_Y_TB 0x20 +#define ATR_Y_TC 0x40 +#define ATR_Y_TD 0x80 + +/* T0,T1,etc information in ATR sequence*/ +#define PROTOCOL_T0 0x0001 /* bit 0 for T0 */ +#define PROTOCOL_T1 0x0002 /* bit 1 for T1 */ +#define PROTOCOL_T2 0x0004 /* bit 2 for T2*/ +#define PROTOCOL_T3 0x0008 /* bit 3 for T3*/ +/* etc */ + + +/* timeouts for various places - see ISO 7816-3 */ +#define T_t2 ((300 * TIMER_FREQ) / sc->cardFreq) +#define T_t3 ((40000 * (TIMER_FREQ/1024)) / (sc->cardFreq/1024)) +#define T_WORK_WAITING (((960 * sc->Wi * sc->Fi ) / (sc->cardFreq/1024)) * (TIMER_FREQ/1024)) +#define PARITY_ERROR_MAX 3 /* maximum parity errors on 1 byte before giving up */ + +/* +** its possible for the HAT to wedge. If that happens, all timing is sick, so +** we use timeout below (driven of system sleeps) as a "watchdog" +*/ +#define MAX_FIQ_TIME 5 /* maximum time we are willing to run the FIQ */ + + +/* used to decode T0 commands */ +#define CMD_BUF_INS_OFF 1 /* offset to INS in header */ +#define CMD_BUF_DATA_LEN_OFF 4 /* offset to data length in header */ + + +/* +** +** DATA STRUCTURES +** +*/ +typedef unsigned char BYTE; + +/* our soft c structure */ +struct scr_softc +{ + struct device dev; + int open; + + /* configuration information */ + int status; /* status to be returned */ + int cardFreq; /* freq supplied to card */ + int convention; /* ie direct or inverse */ + int protocolType; /* bit 0 indicates T0, bit 1 indicates T1,etc */ + int N; /* guard time */ + int Fi; /* clock rate */ + int Di; /* bit rate adjustment */ + int Wi; /* work waiting time */ + int clkCountStartRecv; /* count for clock start bits on recv */ + int clkCountDataRecv; /* count for clock data bits on recv*/ + int clkCountDataSend; /* count for clock data bits on send */ + + /* state machines */ + int masterS ; + int t0RecvS; + int t0SendS; + int coldResetS; + int ATRS; + int t0RecvByteS; + int t0SendByteS; + + /* extra stuff kept for t0send state machine */ + int commandCount; /* number of command bytes sent */ + int dataCount; /* number of data bytes send/recv */ + int dataMax; /* max number of data bytes to send/recv */ + + /* extra stuff kept for t0RecvByteS, t0SendByteS machines */ + void (*t0ByteParent) __P((struct scr_softc *,int)); /* state machine that is controlling this SM */ + int shiftBits; /* number of bits shifted */ + BYTE shiftByte; /* intermediate value of bit being shifted */ + BYTE dataByte; /* actual value of byte */ + int shiftParity; /* value of parity */ + int shiftParityCount; /* number of retries due to parity error */ + + /* extra stuff kept for ATR machine */ + int atrY; /* indicates if TA,TB,TC,TD is to follow */ + int atrK; /* number of historical characters*/ + int atrKCount; /* progressive could of historical characters*/ + int atrTABCDx; /* the 'i' in TA(i), TB(i), TC(i) and TD(i) */ + int atrFi; /* value of Fi */ + int atrDi; /* value of Di */ + + int masterDone; /* flag used by bottom half to tell top half its done */ + int bigTrouble; /* david/jim, remove this when the dust settles */ + + /* pointers used by ioctl */ + ScrOn * pIoctlOn; /* pointer to on ioctl data */ + ScrT0 * pIoctlT0; /* pointer to T0 ioctl data */ +}; + +/* number of devices */ +static int devices = 0; + +/* used as reference for tsleep */ +static int tsleepIdent; + + +/* +** only 1 device is using the hat at any one time +** variable below must be acquired using splhigh before using the hat +*/ +static int hatLock = FALSE; + + + + +/* +** data structures associated with our timeout queue that we run for the +** bottom half of the driver +*/ + +/* timeout callout structure */ +typedef struct callout_t +{ + struct callout_t *c_next; /* next callout in queue */ + struct scr_softc *c_sc; /* soft c */ + int c_arg; /* function argument */ + void (*c_func) __P((struct scr_softc*,int)); /* function to call */ + int c_time; /* ticks to the event */ +}Callout; + +/* actual callout array */ +#define SCR_CLK_CALLOUT_COUNT 10 +static Callout scrClkCalloutArray[SCR_CLK_CALLOUT_COUNT]; + +/* callout lists */ +static Callout *scrClkCallFree; /* free queue */ +static Callout scrClkCallTodo; /* todo queue */ + +/* +** information kept for the clock/FIQ that drives our timeout queue +*/ +static int scrClkEnable = 0; /* true if clock enabled */ +static void myHatWedge(int nFIQs); /* callback that informs us if FIQ has wedged */ +static int scrClkCount; /* number used to set t2 that drives FIQ */ + +#define HATSTACKSIZE 1024 /* size of stack used during a FIQ */ +static unsigned char hatStack[HATSTACKSIZE]; /* actual stack used during a FIQ */ + + + + + + + + + + + + +/* +** +** FUNCTIONAL PROTOTYPES +** +*/ + +/* +** +** functions in top half of driver +** +*/ + +/* configure routines */ +int scrprobe __P((struct device *, void *, void *)); +void scrattach __P((struct device *, struct device *, void *)); + +/* driver entry points routines */ +int scropen __P((dev_t dev, int flag, int mode, struct proc *p)); +int scrclose __P((dev_t dev, int flag, int mode, struct proc *p)); +int scrread __P((dev_t dev, struct uio *uio, int flag)); +int scrwrite __P((dev_t dev, struct uio *uio, int flag)); +int scrioctl __P((dev_t dev, u_long cmd, caddr_t data, int flag, struct proc *p)); +void scrstop __P((struct tty *tp, int flag)); + +static void initStates __P((struct scr_softc * sc)); + + + + +/* +** +** functions in bottom half of driver +** +*/ + +/* top level state machine */ +static void masterSM __P((struct scr_softc * sc,int cmd)); + +/* mid level state machines, ie protocols */ +static void t0SendSM __P((struct scr_softc * sc,int cnd)); +static void t0RecvSM __P((struct scr_softc * sc,int cnd)); +static void ATRSM __P((struct scr_softc * sc,int cnd)); + +/* low level state machines, ie bash hardware bits */ +static void coldResetSM __P((struct scr_softc * sc,int cnd)); + +static void t0SendByteSM __P((struct scr_softc * sc,int cnd)); +static void t0RecvByteSM __P((struct scr_softc * sc,int cnd)); + +static void cardOff __P((struct scr_softc * sc)); + +/* +** functions used for our own timeout routines. +** we cannot use system ones as we are running at a spl level +** that can interrupt the system timeout routines +*/ +static void scrClkInit __P((void)); +static void scrClkStart __P((struct scr_softc* sc,int countPerTick)); +static void scrClkAdj __P((int count)); +static void scrClkStop __P((void)); +static void hatClkIrq __P((int count)); + +static void scrTimeout __P((void (*func)(struct scr_softc*,int), struct scr_softc*, int arg, int count)); +static void scrUntimeout __P((void (*func)(struct scr_softc*,int), struct scr_softc*, int arg)); + + +/* debug functions */ +#ifdef SCR_DEBUG + static void invalidStateCmd __P((struct scr_softc* sc,int state,int cmd, int line)); + static char * getText __P((int x)); +#endif + + + +/* Declare the cdevsw and bdevsw entrypoint routines +*/ +cdev_decl(scr); +bdev_decl(scr); + + +struct cfattach scr_ca = +{ + sizeof(struct scr_softc), (cfmatch_t)scrprobe, scrattach +}; + +extern struct cfdriver scr_cd; + + +/* +**++ +** FUNCTIONAL DESCRIPTION: +** +** scrProbe +** +** This is the probe routine for the Smart Card. Because the +** Smart Card is hard wired, there is no probing to peform. The +** function ensures that a succesfull problem occurs only once. +** +** FORMAL PARAMETERS: +** +** parent - input : pointer to the parent device +** match - not used +** aux - output : pointer to an isa_attach_args structure. +** +** IMPLICIT INPUTS: +** +** none. +** +** IMPLICIT OUTPUTS: +** +** none. +** +** FUNCTION VALUE: +** +** 0 - Probe failed to find the requested device. +** 1 - Probe successfully talked to the device. +** +** SIDE EFFECTS: +** +** none. +**-- +*/ +int scrprobe(parent, match, aux) + struct device *parent; + void *match; + void *aux; +{ + struct isa_attach_args *ia = aux; + int rv = 0; + + KERN_DEBUG (scrdebug, SCRPROBE_DEBUG_INFO,("scrprobe: called, name = %s\n", + parent->dv_cfdata->cf_driver->cd_name)); + + if (strcmp(parent->dv_cfdata->cf_driver->cd_name, "ofisascr") == 0 && + devices == 0) + { + /* set "devices" to ensure that we respond only once */ + devices++; + + /* tell the caller that we are not using any resource */ + ia->ia_iosize = -1; + ia->ia_irq = -1; + ia->ia_msize = 0; + rv = 1; + + + KERN_DEBUG (scrdebug, SCRPROBE_DEBUG_INFO,("scrprobe: successful \n")); + + } + + + return (rv); + +} /* End scrprobe() */ + + +/* +**++ +** FUNCTIONAL DESCRIPTION: +** +** scrattach +** +** Initialize the clock and state machines +** +** FORMAL PARAMETERS: +** +** parent - input : pointer to my parents device structure. +** self - output : pointer to my softc with device structure at front. +** aux - input : pointer to the isa_attach_args structure. +** +** IMPLICIT INPUTS: +** +** nill +** +** IMPLICIT OUTPUTS: +** +** scrconsinit - clock callout functions set +** state machines all at idle +** +** FUNCTION VALUE: +** +** none. +** +** SIDE EFFECTS: +** +** none. +**-- +*/ +void scrattach(parent, self, aux) + struct device *parent; + struct device *self; + void *aux; +{ + struct scr_softc *sc = (void *)self; + + printf("\n"); + if (!strcmp(parent->dv_cfdata->cf_driver->cd_name, "ofisascr")) + { + KERN_DEBUG (scrdebug, SCRATTACH_DEBUG_INFO,("scrattach: called \n")); + + /* set initial state machine values */ + scrClkInit(); + initStates(sc); + sc->open = FALSE; + } + + else + { + panic("scrattach: not on an ISA bus, attach impossible"); + } /* End else we aren't on ISA and we can't handle it */ + + + return; +} /* End scrattach() */ + + +/* +**++ +** FUNCTIONAL DESCRIPTION: +** +** initStates +** +** sets the state of all machines to idle +** +** FORMAL PARAMETERS: +** +** sc - Pointer to the softc structure. +** +** IMPLICIT INPUTS: +** +** nill +** +** IMPLICIT OUTPUTS: +** +** nill +** +** FUNCTION VALUE: +** +** nill +** +** SIDE EFFECTS: +** +** nill +**-- +*/ +static void initStates(struct scr_softc * sc) +{ + sc->masterS = msIdleOff; + sc->t0RecvS = t0rsIdle; + sc->t0SendS = t0ssIdle; + sc->coldResetS = crsIdle; + sc->ATRS = atrsIdle; + sc->t0RecvByteS = t0rbsIdle; + sc->t0SendByteS = t0sbsIdle; +} + + + +/* +**++ +** FUNCTIONAL DESCRIPTION: +** +** scrOpen +** +** Opens the driver. We only let the device be opened +** once for security reasons +** +** FORMAL PARAMETERS: +** +** dev - input : Device identifier consisting of major and minor numbers. +** flag - input : Indicates if this is a blocking I/O call. +** mode - not used. +** p - input : Pointer to the proc structure of the process +** performing the open. +** +** IMPLICIT INPUTS: +** +** none. +** +** IMPLICIT OUTPUTS: +** +** none. +** +** FUNCTION VALUE: +** +** ENXIO - invalid device specified for open. +** EBUSY - The unit is already open +** +** SIDE EFFECTS: +** +** none. +**-- +*/ +int scropen(dev, flag, mode, p) + dev_t dev; + int flag; + int mode; +struct proc *p; +{ + int unit = SCRUNIT(dev); + struct scr_softc *sc; + + KERN_DEBUG (scrdebug, SCROPEN_DEBUG_INFO, + ("scropen: called with minor device %d and flag 0x%x\n", + unit, flag)); + + /* Sanity check the minor device number we have been instructed + ** to open and set up our softc structure pointer. + */ + if (unit >= scr_cd.cd_ndevs) + { + KERN_DEBUG (scrdebug, SCROPEN_DEBUG_INFO,("\t scropen, return ENXIO\n")); + return (ENXIO); + } + sc = scr_cd.cd_devs[unit]; + if (!sc) + { + KERN_DEBUG (scrdebug, SCROPEN_DEBUG_INFO,("\t scropen, return ENXIO\n")); + return (ENXIO); + } + + + // david,jim - remove ifdef this when NCI can cope with only 1 open +#if 0 + if (sc->open) + { + + KERN_DEBUG (scrdebug, SCROPEN_DEBUG_INFO,("\t scropen, return EBUSY\n")); + return (EBUSY); + } + + + /* set all initial conditions */ + sc->open = TRUE; +#endif + + KERN_DEBUG (scrdebug, SCROPEN_DEBUG_INFO,("scropen: success \n")); + /* Now invoke the line discipline open routine + */ + + return 0; + +} /* End scropen() */ + + +/* +**++ +** FUNCTIONAL DESCRIPTION: +** +** This function closed the driver +** +** FORMAL PARAMETERS: +** +** dev - input : Device identifier consisting of major and minor numbers. +** flag - Not used. +** mode - Not used. +** p - Not used. +** +** IMPLICIT INPUTS: +** +** scr_cd - used to locate the softc structure for the device unit +** identified by dev. +** +** IMPLICIT OUTPUTS: +** +** The device is put into an idle state. +** +** FUNCTION VALUE: +** +** 0 - Always returns success. +** +** SIDE EFFECTS: +** +** none. +**-- +*/ +int scrclose(dev, flag, mode, p) + dev_t dev; + int flag; + int mode; + struct proc *p; +{ +#if 0 + int unit = SCRUNIT(dev); + struct scr_softc *sc = scr_cd.cd_devs[unit]; +#endif + + KERN_DEBUG (scrdebug, SCRCLOSE_DEBUG_INFO, + ("scrclose: called for minor device %d flag 0x%x\n", + SCRUNIT(dev), flag)); + + // david,jim - remove ifdef this when NCI can cope with only 1 open +#if 0 + /* Check we are open in the first place + */ + if (sc->open) + { + /* put everything in the idle state */ + scrClkInit(); + initStates(sc); + sc->open = FALSE; + + } + + + else + { + KERN_DEBUG (scrdebug, SCRCLOSE_DEBUG_INFO,("\t scrclose, device not open\n")); + } +#endif + + KERN_DEBUG (scrdebug, SCRCLOSE_DEBUG_INFO,("scrclose exiting\n")); + return(0); +} + + + +/* +**++ +** FUNCTIONAL DESCRIPTION: +** +** scrwrite +** +** not supported +** +** FORMAL PARAMETERS: +** +** dev - input : Device identifier consisting of major and minor numbers. +** uio - input : Pointer to the user I/O information (ie. write data). +** flag - input : Information on how the I/O should be done (eg. blocking +** or non-blocking). +** +** IMPLICIT INPUTS: +** +** +** IMPLICIT OUTPUTS: +** +** none +** +** FUNCTION VALUE: +** +** Returns ENODEV +** +** SIDE EFFECTS: +** +** none +**-- +*/ +int +scrwrite(dev, uio, flag) +dev_t dev; +struct uio *uio; +int flag; +{ + return ENODEV; +} + + + +/* +**++ +** FUNCTIONAL DESCRIPTION: +** +** scrread +** +** not supported +** +** FORMAL PARAMETERS: +** +** dev - input : Device identifier consisting of major and minor numbers. +** uio - input : Pointer to the user I/O information (ie. read buffer). +** flag - input : Information on how the I/O should be done (eg. blocking +** or non-blocking). +** +** IMPLICIT INPUTS: +** +** +** IMPLICIT OUTPUTS: +** +** none +** +** FUNCTION VALUE: +** +** Returns ENODEV +** +** SIDE EFFECTS: +** +** none +**-- +*/ +int +scrread(dev, uio, flag) +dev_t dev; +struct uio *uio; +int flag; +{ + return ENODEV; +} + + + + + +/* +**++ +** FUNCTIONAL DESCRIPTION: +** +** scrstop +** +** should not be called +** +** FORMAL PARAMETERS: +** +** tp - Pointer to our tty structure. +** flag - Ignored. +** +** IMPLICIT INPUTS: +** +** none. +** +** IMPLICIT OUTPUTS: +** +** none. +** +** FUNCTION VALUE: +** +** none. +** +** SIDE EFFECTS: +** +** none. +**-- +*/ +void scrstop(tp, flag) + struct tty *tp; + int flag; +{ + panic("scrstop: not implemented"); +} + + + + +/* +**++ +** FUNCTIONAL DESCRIPTION: +** +** tty +** +** should not be called +** +** FORMAL PARAMETERS: +** +** dev - input : Device identifier consisting of major and minor numbers. +** +** IMPLICIT INPUTS: +** +** +** IMPLICIT OUTPUTS: +** +** none +** +** FUNCTION VALUE: +** +** null +** +** SIDE EFFECTS: +** +** none. +**-- +*/ +struct tty * scrtty(dev) + dev_t dev; +{ + panic("scrtty: not implemented"); + return NULL; +} + + + + + +/* +**++ +** FUNCTIONAL DESCRIPTION: +** +** This routine is responsible for performing I/O controls. +** +** There are 4 commands. Status, On, T0 and Off. +** +** Status checks to see if the card is inserted. This command +** does not use the state machines +** +** On turns the card on and gets the ATR sequence from the card. +** This command does use the state machines +** +** T0 is used to read and write the card. This command does use +** the state machines +** +** Off turns the card off. This command does not use the state +** machines. +** +** +** FORMAL PARAMETERS: +** +** dev - input : Device identifier consisting of major and minor numbers. +** cmd - input : The requested IOCTL command to be performed. +** See scrio.h for details +** +** +** Bit Position { 3322222222221111111111 +** { 10987654321098765432109876543210 +** Meaning | DDDLLLLLLLLLLLLLGGGGGGGGCCCCCCCC +** +** D - Command direction, in/out/both. +** L - Command argument length. +** G - Command group, 't' used for tty. +** C - Actual command enumeration. +** +** data - input/output : Direction depends on the command. +** flag - input : Not used by us but passed to line discipline and ttioctl +** p - input : pointer to proc structure of user. +** +** IMPLICIT INPUTS: +** +** none. +** +** IMPLICIT OUTPUTS: +** +** sc->masterS state of master state machine +** +** +** FUNCTION VALUE: +** +** ENOTTY if not correct ioctl +** +** +** SIDE EFFECTS: +** +**-- +*/ +int +scrioctl(dev, cmd, data, flag, p) + dev_t dev; + u_long cmd; + caddr_t data; + int flag; +struct proc *p; +{ + int unit = SCRUNIT(dev); + struct scr_softc* sc = scr_cd.cd_devs[unit]; + + int error = 0; /* error value returned */ + int masterDoneRetries= 0; /* nuber of times we looked at masterDone */ + int done; /* local copy of masterDone */ + + ScrStatus * pIoctlStatus; /* pointer to status ioctl */ + ScrOff * pIoctlOff; /* pointer to off ioctl */ + + u_int savedInts; /* saved interrupts */ + int s; /* saved spl value */ + + + + KERN_DEBUG (scrdebug, SCRIOCTL_DEBUG_INFO, + ("scrioctl: called for device 0x%x, command 0x%lx, " + "flag 0x%x\n", + unit, cmd, flag)); + + + + switch (cmd) + { + /* + ** get the status of the card, ie is it in, in but off, in and on + */ + case SCRIOSTATUS: + pIoctlStatus = (ScrStatus*)data; + if (scrGetDetect()) + { + savedInts = disable_interrupts(I32_bit | F32_bit); + if (sc->masterS == msIdleOn) + { + pIoctlStatus->status = CARD_ON; + } + else + { + ASSERT(sc->masterS == msIdleOff); + pIoctlStatus->status = CARD_INSERTED; + } + restore_interrupts(savedInts); + } + + else + { + pIoctlStatus->status = CARD_REMOVED; + } + break; + + + + /* + ** turn the card on and get the ATR sequence + */ + case SCRIOON: + sc->pIoctlOn = (ScrOn*)data; + // acquire the hat lock. + while (1) + { + s = splhigh(); + if(!hatLock) + { + hatLock = TRUE; + splx(s); + break; + } + splx(s); + + tsleep(&tsleepIdent ,PZERO,"hat", 1); + } + + + // check to see if the card is in + if(!scrGetDetect()) + { + initStates(sc); + cardOff(sc); + // do not call scrClkInit() as it is idle already + sc->pIoctlOn->status = ERROR_CARD_REMOVED; + } + + + // check to see if we are already on + else if(sc->masterS == msIdleOn) + { + sc->pIoctlOn->status = ERROR_CARD_ON; + } + + // card was in, card is off, so lets start it + else + { + // set up the top half + sc->masterDone = FALSE; + sc->bigTrouble = FALSE; /* david/jim, remove this when the dust settles */ + + + + // start bottom half + scrClkStart (sc,400); + savedInts = disable_interrupts(I32_bit | F32_bit); + masterSM(sc,mcOn); + restore_interrupts(savedInts); + + + + // see if bottom half done + while (1) + { + // check that we have not looped too many times + if(masterDoneRetries >= MAX_FIQ_TIME * HZ) + { +//printf("MAX_FIQ_TIME reached \n"); + // big problems, so reset bottom + savedInts = disable_interrupts(I32_bit | F32_bit); + scrClkInit(); + initStates(sc); + cardOff(sc); + sc->status = ERROR_CARD_REMOVED; + sc->masterDone = TRUE; + restore_interrupts(savedInts); + // dont stop clock, done at bottom of case + } + masterDoneRetries ++; + + // get done bit + savedInts = disable_interrupts(I32_bit | F32_bit); + done = sc->masterDone; + restore_interrupts(savedInts); + + // see if all done + if(done) + { + break; + } + + + // wait for a while + tsleep(&tsleepIdent ,PZERO,"hat", 1); + } + + + // stop bottom half + scrClkStop(); + + + /* need to fix up count bits in non hat interrupt time, so */ + if (sc->status == ERROR_OK) + { + sc->clkCountStartRecv = CLK_COUNT_START; + sc->clkCountDataRecv = sc->clkCountStartRecv * START_2_DATA; + sc->clkCountDataSend = CLK_COUNT_DATA; + } + + + + /* takes while to turn off all lines, so keep out of hat */ + if (sc->masterS != msIdleOn) + { + cardOff(sc); + } + // get the status back from the state machine + sc->pIoctlOn->status = sc->status; + + + } + + + // release the hat lock. + s = splhigh(); + ASSERT(hatlock); + hatLock = FALSE; + splx(s); + + // david,jim hack to stop ioctl memcpy problem, to be removed when problem fixed ejg + if (sc->pIoctlOn->status != ERROR_OK) + { + sc->pIoctlOn->atrLen = 0; + } + break; + + + /* + ** turn the card off + */ + case SCRIOOFF: + pIoctlOff = (ScrOff*)data; + // card off does not requires any state processing, so do work here + initStates(sc); + cardOff(sc); + // do not call scrClkInit() as it is idle already + pIoctlOff->status = ERROR_OK; + break; + + + /* + ** do a T0 read or write + */ + case SCRIOT0: + sc->pIoctlT0 = (ScrT0*)data; + + // acquire the hat lock. + while (1) + { + s = splhigh(); + if(!hatLock) + { + hatLock = TRUE; + splx(s); + break; + } + splx(s); + + tsleep(&tsleepIdent ,PZERO,"hat", 1); + } + + // check to see if the card is in + if(!scrGetDetect()) + { + initStates(sc); + cardOff(sc); + // do not call scrClkInit() as it is idle already + sc->pIoctlT0->status = ERROR_CARD_REMOVED; + } + + + // check to see if card is off + else if(sc->masterS == msIdleOff) + { + sc->pIoctlT0->status = ERROR_CARD_OFF; + } + + // card was in, card is on, lets do command + else + + { + // set up the top half + sc->masterDone = FALSE; + sc->bigTrouble = FALSE; /* david/jim, remove this when the dust settles */ + + // start bottom half + scrClkStart (sc,sc->clkCountDataSend); + savedInts = disable_interrupts(I32_bit | F32_bit); + if (sc->pIoctlT0->writeBuffer) + { + masterSM(sc,mcT0DataSend); + } + else + { + masterSM(sc,mcT0DataRecv); + } + restore_interrupts(savedInts); + + + // see if bottom half done + while (1) + { + // check that we have not looped too many times + if(masterDoneRetries >= MAX_FIQ_TIME * HZ) + { +//printf("MAX_FIQ_TIME reached \n"); + // big problems, so reset bottom + savedInts = disable_interrupts(I32_bit | F32_bit); + scrClkInit(); + initStates(sc); + cardOff(sc); + sc->status = ERROR_CARD_REMOVED; + sc->masterDone = TRUE; + restore_interrupts(savedInts); + } + masterDoneRetries ++; + + + // get done bit + savedInts = disable_interrupts(I32_bit | F32_bit); + done = sc->masterDone; + restore_interrupts(savedInts); + + + // see if all done + if(done) + { + break; + } + + + // wait for a while + tsleep(&tsleepIdent ,PZERO,"hat", 1); + } + + // stop bottom half + scrClkStop(); + + + + // get the status back from the state machine + sc->pIoctlT0->status = sc->status; + } + + + // release the hat lock. + s = splhigh(); + hatLock = FALSE; + splx(s); + + + + // david, jim hack to stop ioctl memcpy problem, to be removed when problem fixed ejg + if (sc->pIoctlT0->status != ERROR_OK) + { + sc->pIoctlT0->dataLen = 0; + } + break; + + default: + KERN_DEBUG (scrdebug, SCRIOCTL_DEBUG_INFO,("\t scrioctl: unknown command, ENOTTY \n")); + error = ENOTTY; + break; + } + + + + KERN_DEBUG (scrdebug, SCRIOCTL_DEBUG_INFO, + ("scrioctl: exiting with sc->status %d\n", error)); + return (error); +} /* End scrioctl */ + + + + + + +/* +** +** All functions below this point are the bottom half of the driver +** +** All are called during a FIQ, except for some functions in masterSM which +** provides the interface between the bottom half and top half of +** the driver (nb masterDone() helps masterSM() out with this interface +** between top and bottom parts of the driver. +** +*/ + + +/* +**++ +** FUNCTIONAL DESCRIPTION: +** +** masterSM +** +** This state machine implements the top level state control It +** receives commands to turn the card on, and do T0 reads and T0 writes +** from the scrioctl. It then calls mid level state machine to action +** these commands. +** +** This machine is the only machine to keep state between scrioctl calls. +** Between calls, the state will be either msIdleOff, or msIdleOn. msIdleOff +** indicates that no signals are applied to the card. msidleOn indicates that +** power and clock are supplied to the card, and that the card has performed +** a successful ATR sequence. +** +** This routine gets called during FIQ interrupts and from scrioctl. It is a +** requirement that the scrioctl disables interrupts before calling this function. +** +** NB:- there is no way for the machine to get from msIdleOn to msIdleOff. Since +** this is just a mater of turning all signals off and resetting state machines, +** scrioctl takes a shortcut and resets everything itself. Ie it hits everything +** with a big hammer!! +** +** FORMAL PARAMETERS: +** +** sc - Pointer to the softc structure. +** cmd - command to the state machine, can be from ioctl, or mid level SM +** +** IMPLICIT INPUTS: +** +** sc->masterS state of this machine +** sc->pIoctlT0 pointer to T0 ioctl +** +** IMPLICIT OUTPUTS: +** +** +** FUNCTION VALUE: +** +** nill +** +** SIDE EFFECTS: +** +** power and clock applied to card if successful ATR +**-- +*/ +static void masterSM(struct scr_softc * sc,int cmd) +{ + + if (sc->bigTrouble) return; // david,jim , remove this when dust settles + + switch (sc->masterS) + { + case msIdleOff: + switch (cmd) + { + case mcOn: + if (scrGetDetect()) + { + /* + ** the card is off, and we want it on + */ + + /* set initial values */ + sc->status = 0; + sc->convention = CONVENTION_UNKOWN; + sc->protocolType = 0; + sc->N = N_DEFAULT; + sc->Fi = Fi_DEFAULT; + sc->Di = Di_DEFAULT; + sc->Wi = Wi_DEFAULT; + sc->cardFreq = CARD_FREQ_DEF; + sc->clkCountStartRecv = CLK_COUNT_START; + sc->clkCountDataRecv = sc->clkCountStartRecv * START_2_DATA; + sc->clkCountDataSend = CLK_COUNT_DATA; + + /* get coldResetSM to turn on power, clock, reset */ + sc->masterS = msColdReset; + coldResetSM(sc,crcStart); + } + else + { + /* card not inserted, so just set status and give up */ + sc->status = ERROR_CARD_REMOVED; + sc->masterDone = TRUE; + } + break; + + default: + INVALID_STATE_CMD(sc,sc->masterS,cmd); + break; + } + break; + + case msColdReset: + switch (cmd) + { + case mcColdReset: + /* + ** coldResetSM has turned on power, clock , reset + ** tell ATRSM to get the ATR sequence from the card + */ + sc->masterS = msATR; + ATRSM(sc,atrcStart); + break; + + default: + INVALID_STATE_CMD(sc,sc->masterS,cmd); + break; + } + break; + + case msATR: + switch (cmd) + { + case mcATR: + /* + ** ATRSM has tried to get ATR sequence, so give + ** back results to scrioctl. ATR sequence data + ** was copied directly into ioctl data area, so + ** no need to copy data + */ + if(sc->status == ERROR_OK) + { + sc->masterS = msIdleOn; + } + else + { + sc->masterS = msIdleOff; + } + sc->masterDone = TRUE; + break; + + + default: + INVALID_STATE_CMD(sc,sc->masterS,cmd); + break; + } + break; + + case msIdleOn: + switch (cmd) + { + // nb there is no command to go to the IdleOff state. This + // is a reset of the state machine, so is done in ioctl + + case mcT0DataSend: + /* + ** card is on, and we want to T0 Send, so + ** as t0SendSM to do work + */ + sc->status = ERROR_OK; + sc->masterS = msT0Send; + t0SendSM(sc,t0scStart); + break; + + case mcT0DataRecv: + /* + ** card is on, and we want to T0 Recv, so + ** as t0RecvSM to do work + */ + sc->status = ERROR_OK; + sc->masterS = msT0Recv; + t0RecvSM(sc,t0rcStart); + break; + + default: + INVALID_STATE_CMD(sc,sc->masterS,cmd); + break; + } + + break; + + case msT0Send: + switch (cmd) + { + case mcT0Send: + /* + ** t0SendSM has tried to send , so lets give back results + */ + sc->masterS = msIdleOn; + sc->masterDone = TRUE; + break; + + default: + INVALID_STATE_CMD(sc,sc->masterS,cmd); + break; + } + break; + + case msT0Recv: + switch (cmd) + { + case mcT0Recv: + /* + ** t0RecvSM has tried to recv , so lets give back results + ** data was written directly into ioctl data area, so we + ** do not need to copy any data + */ + sc->pIoctlT0->dataLen = sc->dataCount; + sc->masterS = msIdleOn; + sc->masterDone = TRUE; + break; + + default: + INVALID_STATE_CMD(sc,sc->masterS,cmd); + break; + } + break; + + default: + INVALID_STATE_CMD(sc,sc->masterS,cmd); + break; + + } +} + + + + +/* +**++ +** FUNCTIONAL DESCRIPTION: +** +** t0SendSM +** +** This is the T=0 Send State Machine. It is responsible +** for performing the send part of the ISO 7816-3 T=0 +** protocol. It is mid level protocol state machine. +** +** Once started, this machine is driven entirely via the +** FIQ/timeout structure . +** +** +** +** FORMAL PARAMETERS: +** +** sc - Pointer to the softc structure. +** cmd - command to this machine +** +** IMPLICIT INPUTS: +** +** sc->t0SendS state of this machine +** sc->pIoctlT0->command command to send to card +** sc->pIoctlT0->data data to send to card +** +** IMPLICIT OUTPUTS: +** +** sc->status error status from this machine +** sc->pIoctlT0->sw1 command status from card +** sc->pIoctlT0->sw2 command status from card +** sc->status error status from this machine +** +** FUNCTION VALUE: +** +** nill +** +** SIDE EFFECTS: +** +** nill +**-- +*/ +static void t0SendSM (struct scr_softc * sc, int cmd) +{ + if (sc->bigTrouble) return; // david,jim , remove this when dust settles + /* + ** check for major failures that are common to most states + */ + if (cmd == t0scTWorkWaiting || + cmd == gcT0RecvByteErr || + cmd == gcT0SendByteErr + ) + { + switch(cmd) + { + case t0scTWorkWaiting: + ASSERT(sc->t0SendS != t0ssIdle); + + /* kill all lower machines */ + t0SendByteSM(sc,t0sbcAbort); + t0RecvByteSM(sc,t0rbcAbort); + + /* set status */ + sc->status = ERROR_WORK_WAITING; + break; + + case gcT0RecvByteErr: // fall through + case gcT0SendByteErr: + scrUntimeout(t0SendSM, sc, t0scTWorkWaiting); + // done set status, already set in lower machine + break; + + default: + INVALID_STATE_CMD(sc, sc->t0SendS,cmd); + break; + } + + /* change states */ + sc->t0SendS = t0ssIdle; + masterSM(sc,mcT0Send); + return; + } + + switch (sc->t0SendS) + { + case t0ssIdle: + switch (cmd) + { + case t0scStart: + /* set initial values */ + sc->t0SendS = t0ssSendHeader; + sc->t0ByteParent = t0SendSM; + sc->commandCount = 0; + sc->dataCount = 0; + sc->dataMax = sc->pIoctlT0->command[CMD_BUF_DATA_LEN_OFF]; + sc->dataByte = sc->pIoctlT0->command[sc->commandCount]; + + // get a byte + t0SendByteSM(sc,t0sbcStart); + break; + + default: + INVALID_STATE_CMD(sc, sc->t0SendS,cmd); + break; + } + break; + + case t0ssSendHeader: + switch (cmd) + { + case gcT0SendByte: + sc->commandCount++; + if (sc->commandCount < CMD_BUF_LEN) + { + sc->dataByte = sc->pIoctlT0->command[sc->commandCount]; + t0SendByteSM(sc,t0sbcStart); + } + else + { + ASSERT(sc->commandCount == CMD_BUF_LEN); + + sc->t0SendS = t0ssRecvProcedure; + scrTimeout(t0SendSM,sc,t0scTWorkWaiting,T_WORK_WAITING); + t0RecvByteSM(sc,t0rbcStart); + } + break; + + default: + INVALID_STATE_CMD(sc, sc->t0SendS,cmd); + break; + } + break; + + case t0ssRecvProcedure: + switch (cmd) + { + case gcT0RecvByte: + scrUntimeout(t0SendSM, sc,t0scTWorkWaiting); + /* see if we should send all remaining bytes */ + if ( (sc->dataByte == sc->pIoctlT0->command[CMD_BUF_INS_OFF]) || + (sc->dataByte == (sc->pIoctlT0->command[CMD_BUF_INS_OFF] ^ 0x01)) ) + { + ASSERT(sc->dataCount < sc->dataMax); + sc->t0SendS = t0ssSendData; + sc->dataByte = sc->pIoctlT0->data[sc->dataCount]; + t0SendByteSM(sc,t0sbcStart); + sc->dataCount++; + } + + /* see if we should send one data byte */ + else if ((sc->dataByte == (sc->pIoctlT0->command[CMD_BUF_INS_OFF] ^ 0xFF)) || + (sc->dataByte == (sc->pIoctlT0->command[CMD_BUF_INS_OFF] ^ 0xFE)) ) + { + ASSERT(sc->dataCount < sc->dataMax); + sc->t0SendS = t0ssSendByte; + sc->dataByte = sc->pIoctlT0->data[ sc->dataCount]; + t0SendByteSM(sc,t0sbcStart); + sc->dataCount++; + } + + /* see if we should extend the work waiting period */ + else if (sc->dataByte == 0x60) + { + t0RecvByteSM(sc,t0rbcStart); + scrTimeout(t0SendSM,sc,t0scTWorkWaiting,T_WORK_WAITING); + } + +#ifdef ORIGINAL_SW1_CODE /* XXX XXX XXX cgd */ + /* see if we have a SW1 byte */ + else if ( ((sc->dataByte & 0xf0) == 0x60) || ((sc->dataByte & 0xf0) == 0x90) + && + sc->dataByte != 0x60) +#else /* XXX XXX XXX cgd */ + /* see if we have a SW1 byte */ + else if ( ( ((sc->dataByte & 0xf0) == 0x60) || ((sc->dataByte & 0xf0) == 0x90) ) + && + sc->dataByte != 0x60) +#endif /* XXX XXX XXX cgd */ + { + sc->pIoctlT0->sw1 = sc->dataByte; + sc->t0SendS = t0ssRecvSW2; + t0RecvByteSM(sc,t0rbcStart); + scrTimeout(t0SendSM,sc,t0scTWorkWaiting,T_WORK_WAITING); + } + + /* got bad data byte, log error and get out */ + else + { + sc->status = ERROR_BAD_PROCEDURE_BYTE; + + /* change state */ + sc->t0SendS = t0ssIdle; + masterSM(sc,mcT0Send); + } + break; + + default: + INVALID_STATE_CMD(sc, sc->t0SendS,cmd); + break; + } + break; + + case t0ssSendByte: + switch (cmd) + { + case gcT0SendByte: + if (sc->dataCount < sc->dataMax) + { + sc->t0SendS = t0ssRecvProcedure; + } + + /* wait for sw1 byte */ + else + { + ASSERT(sc->dataCount == sc->dataMax); + sc->t0SendS = t0ssRecvSW1; + } + + // ask for another byte + t0RecvByteSM(sc,t0rbcStart); + scrTimeout(t0SendSM,sc,t0scTWorkWaiting,T_WORK_WAITING); + break; + + default: + INVALID_STATE_CMD(sc, sc->t0SendS,cmd); + break; + } + break; + + case t0ssSendData: + switch (cmd) + { + case gcT0SendByte: + /* send data */ + if (sc->dataCount < sc->dataMax) + { + sc->t0SendS = t0ssSendData; + sc->dataByte = sc->pIoctlT0->data[ sc->dataCount]; + t0SendByteSM(sc,t0sbcStart); + sc->dataCount++; + } + + /* wait for sw1 byte */ + else + { + ASSERT(sc->dataCount == sc->dataMax); + sc->t0SendS = t0ssRecvSW1; + t0RecvByteSM(sc,t0rbcStart); + scrTimeout(t0SendSM,sc,t0scTWorkWaiting,T_WORK_WAITING); + } + break; + + default: + INVALID_STATE_CMD(sc, sc->t0SendS,cmd); + break; + } + break; + + case t0ssRecvSW1: + switch (cmd) + { + case gcT0RecvByte: + scrUntimeout(t0SendSM, sc,t0scTWorkWaiting); + sc->pIoctlT0->sw1 = sc->dataByte; + sc->t0SendS = t0ssRecvSW2; + t0RecvByteSM(sc,t0rbcStart); + scrTimeout(t0SendSM,sc,t0scTWorkWaiting,T_WORK_WAITING); + break; + default: + INVALID_STATE_CMD(sc, sc->t0SendS,cmd); + break; + } + break; + + case t0ssRecvSW2: + switch (cmd) + { + case gcT0RecvByte: + scrUntimeout(t0SendSM, sc,t0scTWorkWaiting); + sc->pIoctlT0->sw2 = sc->dataByte; + sc->t0SendS = t0ssIdle; + masterSM(sc,mcT0Send); + break; + + default: + INVALID_STATE_CMD(sc, sc->t0SendS,cmd); + break; + } + break; + + default: + INVALID_STATE_CMD(sc, sc->t0SendS,cmd); + break; + } +} + + + +/* +**++ +** FUNCTIONAL DESCRIPTION: +** +** t0RecvSM +** +** This is the T=0 Recv State Machine. It is responsible +** for performing the recv part of the ISO 7816-3 T=0 +** protocol. It is mid level protocol state machine. +** +** Once started, this machine is driven entirely via the +** FIQ/timeout structure . +** +** FORMAL PARAMETERS: +** +** sc - Pointer to the softc structure. +** cmd - command to this machine +** +** IMPLICIT INPUTS: +** +** sc->t0RecvS state of this machine +** sc->pIoctlT0->command command to send to card +** +** IMPLICIT OUTPUTS: +** +** sc->pIoctlT0->data data from card +** sc->pIoctlT0->dataLen size of data from card +** sc->pIoctlT0->sw1 command status from card +** sc->pIoctlT0->sw2 command status from card +** sc->status error status from this machine +** +** FUNCTION VALUE: +** +** nill +** +** SIDE EFFECTS: +** +** nill +**-- +*/ +static void t0RecvSM (struct scr_softc * sc,int cmd) +{ + if (sc->bigTrouble) return; // david,jim , remove this when dust settles + + /* + ** check for major failures that are common to most states + */ + if (cmd == t0rcTWorkWaiting || + cmd == gcT0RecvByteErr || + cmd == gcT0SendByteErr ) + + { + switch(cmd) + { + + case t0rcTWorkWaiting: + ASSERT(sc->t0RecvS != t0rsIdle); + + /* kill all lower level machines */ + t0SendByteSM(sc,t0sbcAbort); + t0RecvByteSM(sc,t0rbcAbort); + + /* set status */ + sc->status = ERROR_WORK_WAITING; + break; + + case gcT0RecvByteErr: // fall through + case gcT0SendByteErr: + /* kill all the timers */ + scrUntimeout(t0RecvSM, sc,t0rcTWorkWaiting); + break; + + default: + INVALID_STATE_CMD(sc, sc->t0RecvS,cmd); + break; + + } + + + + /* change state */ + sc->t0RecvS = t0rsIdle; + masterSM(sc,mcT0Recv); + + /* all done */ + return; + } + + switch (sc->t0RecvS) + { + case t0rsIdle: + switch (cmd) + { + case t0rcStart: + /* set initial values */ + sc->t0RecvS = t0rsSendHeader; + sc->t0ByteParent = t0RecvSM; + sc->commandCount = 0; + sc->dataCount = 0; + sc->dataMax = sc->pIoctlT0->command[CMD_BUF_DATA_LEN_OFF]; + if (sc->dataMax == 0) + { + sc->dataMax = 256; + } + sc->dataByte = sc->pIoctlT0->command[sc->commandCount]; + t0SendByteSM(sc,t0sbcStart); + break; + + default: + INVALID_STATE_CMD(sc, sc->t0RecvS,cmd); + break; + } + break; + + case t0rsSendHeader: + switch (cmd) + { + case gcT0SendByte: + sc->commandCount++; + if (sc->commandCount < CMD_BUF_LEN) + { + sc->dataByte = sc->pIoctlT0->command[sc->commandCount]; + t0SendByteSM(sc,t0sbcStart); + } + else + { + ASSERT(sc->commandCount == CMD_BUF_LEN); + + sc->t0RecvS = t0rsRecvProcedure; + scrTimeout(t0RecvSM,sc,t0rcTWorkWaiting,T_WORK_WAITING); + t0RecvByteSM(sc,t0rbcStart); + } + break; + + default: + INVALID_STATE_CMD(sc, sc->t0RecvS,cmd); + break; + } + break; + + case t0rsRecvProcedure: + switch (cmd) + { + case gcT0RecvByte: + scrUntimeout(t0RecvSM, sc,t0rcTWorkWaiting); + + /* see if we should recv all remaining bytes */ + if ( (sc->dataByte == sc->pIoctlT0->command[CMD_BUF_INS_OFF]) || + (sc->dataByte == (sc->pIoctlT0->command[CMD_BUF_INS_OFF] ^ 0x01)) ) + { + ASSERT(sc->dataCount < sc->dataMax); + + sc->t0RecvS = t0rsRecvData; + scrTimeout(t0RecvSM,sc,t0rcTWorkWaiting,T_WORK_WAITING); + t0RecvByteSM(sc,t0rbcStart); + } + + /* see if we should send one data byte */ + else if ((sc->dataByte == (sc->pIoctlT0->command[CMD_BUF_INS_OFF] ^ 0xFF)) || + (sc->dataByte == (sc->pIoctlT0->command[CMD_BUF_INS_OFF] ^ 0xFE)) ) + { + ASSERT(sc->dataCount < sc->dataMax); + sc->t0RecvS = t0rsRecvByte; + scrTimeout(t0RecvSM,sc,t0rcTWorkWaiting,T_WORK_WAITING); + t0RecvByteSM(sc,t0rbcStart); + } + + /* see if we should extend the work waiting period */ + else if (sc->dataByte == 0x60) + { + t0RecvByteSM(sc,t0rbcStart); + scrTimeout(t0RecvSM,sc,t0rcTWorkWaiting,T_WORK_WAITING); + } + +#ifdef ORIGINAL_SW1_CODE /* XXX XXX XXX cgd */ + /* see if we have a SW1 byte */ + else if ( ((sc->dataByte & 0xf0) == 0x60) || ((sc->dataByte & 0xf0) == 0x90) + && + sc->dataByte != 0x60) +#else /* XXX XXX XXX cgd */ + /* see if we have a SW1 byte */ + else if ( ( ((sc->dataByte & 0xf0) == 0x60) || ((sc->dataByte & 0xf0) == 0x90) ) + && + sc->dataByte != 0x60) +#endif /* XXX XXX XXX cgd */ + { + sc->pIoctlT0->sw1 = sc->dataByte; + sc->t0RecvS = t0rsRecvSW2; + t0RecvByteSM(sc,t0rbcStart); + scrTimeout(t0RecvSM,sc,t0rcTWorkWaiting,T_WORK_WAITING); + } + + /* got bad data byte, log error and get out */ + else + { + sc->status = ERROR_BAD_PROCEDURE_BYTE; + + /* change state */ + sc->t0RecvS = t0rsIdle; + masterSM(sc,mcT0Recv); + } + break; + + default: + INVALID_STATE_CMD(sc, sc->t0RecvS,cmd); + break; + } + break; + + case t0rsRecvByte: + switch (cmd) + { + case gcT0RecvByte: + /* clock in byte */ + scrUntimeout(t0RecvSM, sc,t0rcTWorkWaiting); + sc->pIoctlT0->data[sc->dataCount] = sc->dataByte; + sc->dataCount++; + + + if (sc->dataCount < sc->dataMax) + { + /* get procedure byte */ + sc->t0RecvS = t0rsRecvProcedure; + } + + else + { + ASSERT(sc->dataCount == sc->dataMax); + sc->t0RecvS = t0rsRecvSW1; + } + + // ask for another byte + scrTimeout(t0RecvSM,sc,t0rcTWorkWaiting,T_WORK_WAITING); + t0RecvByteSM(sc,t0rbcStart); + break; + + default: + INVALID_STATE_CMD(sc, sc->t0RecvS,cmd); + break; + } + break; + + case t0rsRecvData: + switch (cmd) + { + case gcT0RecvByte: + /* clock in data */ + scrUntimeout(t0RecvSM, sc,t0rcTWorkWaiting); + sc->pIoctlT0->data[sc->dataCount] = sc->dataByte; + sc->dataCount++; + + /* decide if we have all data */ + if (sc->dataCount >= sc->dataMax) + { + KERN_DEBUG (scrdebug, T0_RECV_SM_DEBUG_INFO,("\t\tt0RecvSM: changing state to t0rsRecvSW1\n",sc->dataByte)); + ASSERT(sc->dataCount == sc->dataMax); + sc->t0RecvS = t0rsRecvSW1; + } + + /* ask for another byte */ + scrTimeout(t0RecvSM,sc,t0rcTWorkWaiting,T_WORK_WAITING); + t0RecvByteSM(sc,t0rbcStart); + break; + + default: + INVALID_STATE_CMD(sc, sc->t0RecvS,cmd); + break; + } + break; + + case t0rsRecvSW1: + switch (cmd) + { + case gcT0RecvByte: + scrUntimeout(t0RecvSM, sc,t0rcTWorkWaiting); + sc->pIoctlT0->sw1 = sc->dataByte; + + sc->t0RecvS = t0rsRecvSW2; + t0RecvByteSM(sc,t0rbcStart); + scrTimeout(t0RecvSM,sc,t0rcTWorkWaiting,T_WORK_WAITING); + break; + default: + INVALID_STATE_CMD(sc, sc->t0RecvS,cmd); + break; + } + break; + + case t0rsRecvSW2: + switch (cmd) + { + case gcT0RecvByte: + scrUntimeout(t0RecvSM, sc,t0rcTWorkWaiting); + sc->pIoctlT0->sw2 = sc->dataByte; + + sc->t0RecvS = t0rsIdle; + masterSM(sc,mcT0Recv); + break; + + default: + INVALID_STATE_CMD(sc, sc->t0RecvS,cmd); + break; + } + break; + + default: + INVALID_STATE_CMD(sc, sc->t0RecvS,cmd); + break; + } +} + + +/* +**++ +** FUNCTIONAL DESCRIPTION: +** +** coldResetSM +** +** This state machine switches on the power, clock and reset pins +** in the correct order/timing. +** It is a low level bit-bashing state machine. +** +** +** FORMAL PARAMETERS: +** +** sc - Pointer to the softc structure. +** cmd - command to this machine +** +** IMPLICIT INPUTS: +** +** sc->coldResetS state of this machine +** +** IMPLICIT OUTPUTS: +** +** nill +** +** FUNCTION VALUE: +** +** nill +** +** SIDE EFFECTS: +** +** signals to card are on +**-- +*/ +static void coldResetSM(struct scr_softc * sc,int cmd) +{ + if (sc->bigTrouble) return; // david,jim , remove this when dust settles + + switch (sc->coldResetS) + { + case crsIdle: + switch (cmd) + { + case crcStart: + scrSetReset(TRUE); + scrSetClock(TRUE); + scrSetDataHighZ(); + scrSetPower(TRUE); + + /* start a t2 timer */ + scrTimeout(coldResetSM,sc,crcT2,T_t2); + sc->coldResetS = crsT2Wait; + break; + + default: + INVALID_STATE_CMD(sc,sc->masterS,cmd); + break; + } + break; + + case crsT2Wait: + switch (cmd) + { + case crcT2: + /* turn off rst */ + scrSetReset(FALSE); + + /* tell master state machine that we are all done */ + sc->coldResetS = crsIdle; + masterSM(sc,mcColdReset); + break; + + default: + INVALID_STATE_CMD(sc,sc->masterS,cmd); + break; + } + break; + + + default: + INVALID_STATE_CMD(sc,sc->coldResetS,cmd); + break; + } +} + +/* +**++ +** FUNCTIONAL DESCRIPTION: +** +** ATRSM +** +** This is the Answer To Reset State Machine. It is responsible +** for performing the Answer To Reset as specified in ISO 7816-3. +** It is mid level protocol state machine. +** +** Once started, this machine is driven entirely via the +** FIQ/timeout structure. +** +** +** During the first byte, we have to check if the card is operating +** at full speed or half speed. The first couple of bits are +** checked to see if it is 1/2 speed, and if so, the clock is changed +** and the state adjustes +** +** At the end of the first byte we have to determin the logic being +** used by the card, ie is it active high/low and msb/lsb. +** +** +** FORMAL PARAMETERS: +** +** sc - Pointer to the softc structure. +** cmd - command to this machine +** +** IMPLICIT INPUTS: +** +** sc->pIoctlAtr->atr data from card +** sc->pIoctlT0->sw1 command status from card +** sc->pIoctlT0->sw2 command status from card +** sc->status error status from this machine +** +** IMPLICIT OUTPUTS: +** +** sc->pIoctlOn->atrBuf data from ATR sequence +** sc->pIoctlOn->atrLen size of data from ATR sequence +** sc->status error status from this machine +** +** +** FUNCTION VALUE: +** +** nill +** +** SIDE EFFECTS: +** +** nill +**-- +*/ +static void ATRSM (struct scr_softc * sc,int cmd) +{ + int lc; + int tck; + + if (sc->bigTrouble) return; // david,jim , remove this when dust settles + + /* + ** check for major failures that are common to most states + */ + if (cmd == atrcT3 || + cmd == atrcTWorkWaiting || + cmd == gcT0RecvByteErr + ) + { + switch(cmd) + { + case atrcT3: + scrUntimeout (ATRSM,sc,atrcTWorkWaiting); + sc->status = ERROR_ATR_T3; + t0RecvByteSM(sc,t0rbcAbort); + break; + + case atrcTWorkWaiting: + scrUntimeout (ATRSM,sc,atrcT3); + sc->status = ERROR_WORK_WAITING; + t0RecvByteSM(sc,t0rbcAbort); + break; + + case gcT0RecvByteErr: + scrUntimeout (ATRSM,sc,atrcT3); + scrUntimeout (ATRSM,sc,atrcTWorkWaiting); + /* done set status, its already set */ + break; + + default: + INVALID_STATE_CMD(sc,sc->ATRS,cmd); + break; + } + + /* change state */ + sc->ATRS = atrsIdle; + masterSM(sc,mcATR); + return; + } + + switch (sc->ATRS) + { + case atrsIdle: + switch (cmd) + { + case atrcStart: + /* lets start looking */ + sc->ATRS = atrsTS; + sc->pIoctlOn->atrLen = 0; + sc->t0ByteParent = ATRSM; + scrTimeout(ATRSM,sc,atrcT3,T_t3 *2); /* by 2 to accomodate 1/2 freq cards */ + t0RecvByteSM(sc,t0rbcStart); + break; + + default: + INVALID_STATE_CMD(sc,sc->ATRS,cmd); + break; + } + break; + + case atrsTS: + switch (cmd) + { + case gcT0RecvByte: + scrUntimeout(ATRSM,sc,atrcT3); + sc->pIoctlOn->atrBuf[sc->pIoctlOn->atrLen] = sc->dataByte; + sc->pIoctlOn->atrLen++; + if(sc->pIoctlOn->atrLen >= ATR_BUF_MAX) + { + #ifdef SCR_DEBUG + DEBUGGER; + #endif + sc->status = ERROR_ATR_TCK; + sc->ATRS = atrsIdle; + masterSM(sc,mcATR); + } + else + { + /* move onto recv T0 */ + sc->ATRS = atrsT0; + scrTimeout(ATRSM,sc,atrcTWorkWaiting,T_WORK_WAITING); + t0RecvByteSM(sc,t0rbcStart); + } + break; + + default: + INVALID_STATE_CMD(sc,sc->ATRS,cmd); + break; + } + break; + + case atrsT0: + switch (cmd) + { + case gcT0RecvByte: + scrUntimeout(ATRSM,sc,atrcTWorkWaiting); + sc->pIoctlOn->atrBuf[sc->pIoctlOn->atrLen] = sc->dataByte; + sc->pIoctlOn->atrLen++; + if(sc->pIoctlOn->atrLen >= ATR_BUF_MAX) + { + #ifdef SCR_DEBUG + printf("atrLen >= ATR_BUF_MAX\n"); + DEBUGGER; + #endif + sc->status = ERROR_ATR_TCK; + sc->ATRS = atrsIdle; + masterSM(sc,mcATR); + } + else + { + /* store Y & K */ + sc->atrY = sc->dataByte & 0xf0; + sc->atrK = sc->dataByte & 0x0f; + + sc->atrTABCDx = 1; + sc->atrKCount = 1; + + /* if there are no TDx following set T0 protocol */ + if (ISCLR(sc->atrY,ATR_Y_TD)) + { + sc->protocolType = PROTOCOL_T0; + } + + + if (sc->atrY) + { + + sc->ATRS = atrsTABCD; + scrTimeout(ATRSM,sc,atrcTWorkWaiting,T_WORK_WAITING); + t0RecvByteSM(sc,t0rbcStart); + } + + else if (sc->atrK) + { + sc->ATRS = atrsTK; + scrTimeout(ATRSM,sc,atrcTWorkWaiting,T_WORK_WAITING); + t0RecvByteSM(sc,t0rbcStart); + } + + else if (sc->protocolType != PROTOCOL_T0) + { + sc->ATRS = atrsTCK; + scrTimeout(ATRSM,sc,atrcTWorkWaiting,T_WORK_WAITING); + t0RecvByteSM(sc,t0rbcStart); + } + + else /* got all of ATR */ + { + sc->ATRS = atrsIdle; + masterSM(sc,mcATR); + } + } + break; + + + default: + INVALID_STATE_CMD(sc,sc->ATRS,cmd); + break; + } + break; + + + case atrsTABCD: + switch (cmd) + { + case gcT0RecvByte: + scrUntimeout(ATRSM,sc,atrcTWorkWaiting); + sc->pIoctlOn->atrBuf[sc->pIoctlOn->atrLen] = sc->dataByte; + sc->pIoctlOn->atrLen++; + if(sc->pIoctlOn->atrLen >= ATR_BUF_MAX) + { + #ifdef SCR_DEBUG + printf("atrLen >= ATR_BUF_MAX\n"); + DEBUGGER; + #endif + sc->status = ERROR_ATR_TCK; + sc->ATRS = atrsIdle; + masterSM(sc,mcATR); + } + else + { + if (sc->atrY & ATR_Y_TA) + { + sc->atrY &= ~ATR_Y_TA; + if (sc->atrTABCDx == 1) + { + sc->Fi = FI2Fi[((sc->dataByte >> 4) & 0x0f)]; + if (sc->Fi == 0) + { + sc->status = ERROR_ATR_FI_INVALID; + sc->Fi = Fi_DEFAULT; + } + + sc->Di = DI2Di[(sc->dataByte & 0x0f)]; + if (sc->Di == 0) + { + sc->status = ERROR_ATR_DI_INVALID; + sc->Di = Di_DEFAULT; + } + + } + } + + else if (sc->atrY & ATR_Y_TB) + { + sc->atrY &= ~ATR_Y_TB; + } + + else if (sc->atrY & ATR_Y_TC) + { + sc->atrY &= ~ATR_Y_TC; + if (sc->atrTABCDx == 1) + { + sc->N = sc->dataByte; + } + + if (sc->atrTABCDx == 2) + { + sc->Wi = sc->dataByte; + } + } + + else + { + ASSERT(sc->atrY & ATR_Y_TD); + sc->atrY &= ~ATR_Y_TD; + + /* copy across the y section of TD */ + sc->atrY = sc->dataByte; + sc->atrY &= 0xf0; + + /* step to the next group of TABCD */ + sc->atrTABCDx++; + + /* store protocols */ + sc->protocolType = (1 << (sc->dataByte &0x0f)); + } + + + /* see what we should do next */ + if (sc->atrY) + { + /* just stay in the same state */ + scrTimeout(ATRSM,sc,atrcTWorkWaiting,T_WORK_WAITING); + t0RecvByteSM(sc,t0rbcStart); + } + + else if (sc->atrK) + { + sc->ATRS = atrsTK; + scrTimeout(ATRSM,sc,atrcTWorkWaiting,T_WORK_WAITING); + t0RecvByteSM(sc,t0rbcStart); + } + + else if (sc->protocolType != PROTOCOL_T0) + { + sc->ATRS = atrsTCK; + scrTimeout(ATRSM,sc,atrcTWorkWaiting,T_WORK_WAITING); + t0RecvByteSM(sc,t0rbcStart); + } + + else /* got all of ATR */ + { + sc->ATRS = atrsIdle; + masterSM(sc,mcATR); + } + } + + break; + + + default: + INVALID_STATE_CMD(sc,sc->ATRS,cmd); + break; + } + break; + + case atrsTK: + switch (cmd) + { + case gcT0RecvByte: + scrUntimeout(ATRSM,sc,atrcTWorkWaiting); + sc->pIoctlOn->atrBuf[sc->pIoctlOn->atrLen] = sc->dataByte; + sc->pIoctlOn->atrLen++; + if(sc->pIoctlOn->atrLen >= ATR_BUF_MAX) + { + #ifdef SCR_DEBUG + printf("atrLen >= ATR_BUF_MAX\n"); + DEBUGGER; + #endif + sc->status = ERROR_ATR_TCK; + sc->ATRS = atrsIdle; + masterSM(sc,mcATR); + } + else + { + + if (sc->atrKCount < sc->atrK) + { + sc->atrKCount++; + scrTimeout(ATRSM,sc,atrcTWorkWaiting,T_WORK_WAITING); + t0RecvByteSM(sc,t0rbcStart); + } + + + else if (sc->protocolType != PROTOCOL_T0) + { + sc->ATRS = atrsTCK; + scrTimeout(ATRSM,sc,atrcTWorkWaiting,T_WORK_WAITING); + t0RecvByteSM(sc,t0rbcStart); + } + + else /* got all of ATR */ + { + sc->ATRS = atrsIdle; + masterSM(sc,mcATR); + } + } + break; + + default: + INVALID_STATE_CMD(sc,sc->ATRS,cmd); + break; + } + break; + + case atrsTCK: + switch (cmd) + { + case gcT0RecvByte: + scrUntimeout(ATRSM,sc,atrcTWorkWaiting); + sc->pIoctlOn->atrBuf[sc->pIoctlOn->atrLen] = sc->dataByte; + sc->pIoctlOn->atrLen++; + if(sc->pIoctlOn->atrLen >= ATR_BUF_MAX) + { + #ifdef SCR_DEBUG + printf("atrLen >= ATR_BUF_MAX\n"); + DEBUGGER; + #endif + sc->status = ERROR_ATR_TCK; + sc->ATRS = atrsIdle; + masterSM(sc,mcATR); + } + else + { + tck = 0; + for (lc = 1; lc < sc->pIoctlOn->atrLen-1; lc++) + { + tck ^= sc->pIoctlOn->atrBuf[lc]; + } + + if (tck == sc->pIoctlOn->atrBuf[sc->pIoctlOn->atrLen-1]) + { + sc->ATRS = atrsIdle; + masterSM(sc,mcATR); + } + else + { + sc->status = ERROR_ATR_TCK; + sc->ATRS = atrsIdle; + masterSM(sc,mcATR); + } + } + break; + + default: + INVALID_STATE_CMD(sc,sc->ATRS,cmd); + break; + } + break; + + + + default: + INVALID_STATE_CMD(sc,sc->ATRS,cmd); + break; + } +} + + + +/* +**++ +** FUNCTIONAL DESCRIPTION: +** +** t0RecvByteSM +** +** This state machine attempts to read 1 byte from a card. +** It is a low level bit-bashing state machine. +** +** Data from the card is async, so the machine scans at +** 5 times the data rate looking for a state bit. Once +** a start bit has been found, it waits for the middle of +** the bit and starts sampling at the bit rate. +** +** Several mid level machines can use this machine, so the value +** sc->t0ByteParent is used to point to back to the mid level machine +** +** +** FORMAL PARAMETERS: +** +** sc - Pointer to the softc structure. +** cmd - command to this machine +** +** IMPLICIT INPUTS: +** +** sc->t0RecvByteS state of this machine +** sc->t0ByteParent mid level machine that started this machine +** +** IMPLICIT OUTPUTS: +** +** sc->shiftByte byte read from the card +** sc->status error value if could not read byte +** +** FUNCTION VALUE: +** +** nill +** +** SIDE EFFECTS: +** +** nill +**-- +*/ +static void t0RecvByteSM(struct scr_softc* sc,int cmd) +{ + if (sc->bigTrouble) return; // david,jim , remove this when dust settles + + if (cmd == t0rbcAbort) + { + /* kill all the timers */ + scrUntimeout(t0RecvByteSM, sc,t0rbcTFindStartEdge); + scrUntimeout(t0RecvByteSM, sc,t0rbcTFindStartMid); + scrUntimeout(t0RecvByteSM, sc,t0rbcTClockData); + scrUntimeout(t0RecvByteSM, sc,t0rbcTErrorStart); + scrUntimeout(t0RecvByteSM, sc,t0rbcTErrorStop); + + scrSetDataHighZ(); + sc->t0RecvByteS = t0rbsIdle; + return; + } + + + switch (sc->t0RecvByteS) + { + case t0rbsIdle: + switch (cmd) + { + case t0rbcStart: + /* set initial conditions */ + sc->shiftBits = 0; + sc->shiftByte = 0; + sc->shiftParity = 0; + sc->shiftParityCount = 0; + scrClkAdj(sc->clkCountStartRecv); /* recv data clock running at 5 times */ + + /* check if start bit is already here */ + //if (scrGetData()) + if (1) + { + /* didn't find it, keep looking */ + scrTimeout(t0RecvByteSM,sc,t0rbcTFindStartEdge,sc->clkCountStartRecv); + sc->t0RecvByteS = t0rbsFindStartEdge; + } + else + { + /* found start bit, look for mid bit */ + scrTimeout(t0RecvByteSM,sc,t0rbcTFindStartMid,sc->clkCountStartRecv); + sc->t0RecvByteS = t0rbsFindStartMid; + } + break; + + + + default: + INVALID_STATE_CMD(sc, sc->t0RecvByteS,cmd); + break; + } + break; + + + case t0rbsFindStartEdge: + switch (cmd) + { + case t0rbcTFindStartEdge: + if (scrGetData()) + { + /* didn't find it, keep looking */ + scrTimeout(t0RecvByteSM,sc,t0rbcTFindStartEdge,sc->clkCountStartRecv); + } + else + { + /* found start bit, look for mid bit */ + scrTimeout(t0RecvByteSM,sc,t0rbcTFindStartMid,sc->clkCountStartRecv * 2); + sc->t0RecvByteS = t0rbsFindStartMid; + } + break; + + + default: + INVALID_STATE_CMD(sc, sc->t0RecvByteS,cmd); + break; + } + break; + + case t0rbsFindStartMid: + switch (cmd) + { + case t0rbcTFindStartMid: + if (scrGetData()) + { + /* found glitch, so just go back to hunting */ + scrTimeout(t0RecvByteSM,sc,t0rbcTFindStartEdge,sc->clkCountStartRecv); + sc->t0RecvByteS = t0rbsFindStartEdge; + } + else + { + /* found start bit, start clocking in data */ + TOGGLE_TEST_PIN(); + scrTimeout(t0RecvByteSM,sc,t0rbcTClockData,sc->clkCountDataRecv); + sc->t0RecvByteS = t0rbsClockData; + } + break; + + + default: + INVALID_STATE_CMD(sc, sc->t0RecvByteS,cmd); + break; + } + break; + + + case t0rbsClockData: + TOGGLE_TEST_PIN(); + switch (cmd) + { + case t0rbcTClockData: + if (sc->shiftBits < 8) + { + if (sc->convention == CONVENTION_INVERSE || + sc->convention == CONVENTION_UNKOWN) + { + /* logic 1 is low, msb is first */ + sc->shiftByte <<= 1; + sc->shiftByte &= 0xfe; + if (!scrGetData()) + { + sc->shiftByte |= 0x01; + sc->shiftParity++; + } + } + else + { + ASSERT(sc->convention == CONVENTION_DIRECT); + /* logic 1 is high, lsb is first */ + sc->shiftByte = sc->shiftByte >> 1; + sc->shiftByte &= 0x7f; + if (scrGetData()) + { + sc->shiftParity++; + sc->shiftByte |= 0x80; + } + } + sc->shiftBits++; + + + /* in TS byte, check if we have a card that works at 1/2 freq */ + if (sc->convention == CONVENTION_UNKOWN && /* in TS byte */ + sc->shiftBits == 3 && /* test at bit 3 in word */ + sc->shiftByte == 4 && /* check for 1/2 freq pattern */ + sc->cardFreq == CARD_FREQ_DEF) /* only do this if at full freq */ + { + /* adjust counts down to 1/2 freq */ + sc->cardFreq = CARD_FREQ_DEF / 2; + sc->clkCountStartRecv = sc->clkCountStartRecv *2; + sc->clkCountDataRecv = sc->clkCountDataRecv *2; + sc->clkCountDataSend = sc->clkCountDataSend *2; + + + /* adjust this so that we have clocked in only fist bit of TS */ + sc->shiftParity = 0; + sc->shiftByte = 0; + sc->shiftBits = 1; + + scrTimeout(t0RecvByteSM,sc,t0rbcTClockData,(sc->clkCountDataRecv * 3) /4); + } + else + { + scrTimeout(t0RecvByteSM,sc,t0rbcTClockData,sc->clkCountDataRecv); + } + } + + /* clock in parity bit */ + else if (sc->shiftBits == 8) + { + if (sc->convention == CONVENTION_INVERSE) + { + if (!scrGetData()) + { + sc->shiftParity++; + } + } + else if (sc->convention == CONVENTION_DIRECT) + { + if (scrGetData()) + { + sc->shiftParity++; + } + } + + + else + { + /* sc->convention not set so sort it out */ + ASSERT(sc->convention == CONVENTION_UNKOWN); + if (sc->shiftByte == CONVENIONT_INVERSE_ID && scrGetData()) + { + sc->convention = CONVENTION_INVERSE; + sc->shiftParity = 0; /* force good parity */ + } + + else if (sc->shiftByte == CONVENTION_DIRECT_ID && scrGetData()) + { + sc->shiftByte = CONVENTION_DIRECT_FIX; + sc->convention = CONVENTION_DIRECT; + sc->shiftParity = 0; /* force good parity */ + } + + else + { + sc->shiftParity = 1; /* force bad parity */ + } + } + + + if ((sc->shiftParity & 01) == 0) + { + sc->shiftBits++; + scrTimeout(t0RecvByteSM,sc,t0rbcTClockData,sc->clkCountDataRecv); + } + else + { + /* got parity error */ + if (sc->shiftParityCount < PARITY_ERROR_MAX) + { + sc->shiftParityCount++; + scrTimeout(t0RecvByteSM,sc,t0rbcTErrorStart,sc->clkCountDataRecv); + sc->t0RecvByteS = t0rbsSendError; + } + else + + { + /* too many parity errors, just give up on this sc->dataByte */ + sc->status = ERROR_PARITY; + sc->t0RecvByteS = t0rbsIdle; + sc->t0ByteParent(sc,gcT0RecvByteErr); + } + } + } + + else + { + sc->dataByte = sc->shiftByte; + sc->t0RecvByteS = t0rbsIdle; + sc->t0ByteParent(sc,gcT0RecvByte); + } + break; + + default: + INVALID_STATE_CMD(sc, sc->t0RecvByteS,cmd); + break; + } + break; + + + case t0rbsSendError: + TOGGLE_TEST_PIN(); + switch (cmd) + { + case t0rbcTErrorStart: + /* start sending error bit */ + scrSetData(FALSE); + scrTimeout(t0RecvByteSM,sc,t0rbcTErrorStop,sc->clkCountDataRecv * 2); + break; + + case t0rbcTErrorStop: + /* stop sending parity error & reset information*/ + scrSetData(TRUE); + sc->shiftBits = 0; + sc->shiftByte = 0; + sc->shiftParity = 0; + + /* start looking for start bit */ + scrTimeout(t0RecvByteSM,sc,t0rbcTFindStartEdge,1); + sc->t0RecvByteS = t0rbsFindStartEdge; + break; + + default: + INVALID_STATE_CMD(sc, sc->t0RecvByteS,cmd); + break; + } + break; + + + default: + INVALID_STATE_CMD(sc, sc->t0RecvByteS,cmd); + break; + } +} + +/* +**++ +** FUNCTIONAL DESCRIPTION: +** +** t0SendByteSM +** +** This state machine writes 1 byte to a card. +** It is a low level bit-bashing state machine. +** +** +** Several mid level machines can use this machine, so the value +** sc->t0ByteParent is used to point to back to the mid level machine +** +** FORMAL PARAMETERS: +** +** sc - Pointer to the softc structure. +** cmd - command to this machine +** +** IMPLICIT INPUTS: +** +** sc->t0SendByteS state of this machine +** sc->shiftByte byte to write to the card +** +** IMPLICIT OUTPUTS: +** +** sc->status error value if could not read byte +** +** FUNCTION VALUE: +** +** nill +** +** SIDE EFFECTS: +** +** nill +**-- +*/ +//int bigTroubleTest = 0; +static void t0SendByteSM (struct scr_softc * sc,int cmd) +{ + //if(bigTroubleTest == 2000) + //{ + // INVALID_STATE_CMD(sc, sc->t0SendByteS,cmd); + // bigTroubleTest = 0; + //} + // + //bigTroubleTest++; + + if (sc->bigTrouble) return; // david,jim , remove this when dust settles + + if (cmd == t0sbcAbort) + { + /* kill all the timers */ + scrUntimeout(t0SendByteSM, sc, t0sbcTGuardTime); + scrUntimeout(t0SendByteSM, sc, t0sbcTClockData); + scrUntimeout(t0SendByteSM, sc, t0sbcTError); + + scrSetDataHighZ(); + return; + } + + + switch (sc->t0SendByteS) + { + case t0sbsIdle: + switch (cmd) + { + case t0sbcStart: + /* set initial conditions */ + sc->shiftBits = 0; + sc->shiftParity = 0; + sc->shiftParityCount = 0; + sc->shiftByte = sc->dataByte; + + scrClkAdj(sc->clkCountDataSend); /* send data clock running at 1 ETU */ + + /* check if we have to wait for guard time */ + if (0) /* possible optimization here */ + { + /* can send start bit now */ + scrTimeout(t0SendByteSM,sc,t0sbcTClockData,sc->clkCountDataSend); + scrSetData(FALSE); + sc->t0SendByteS = t0sbsClockData; + } + else + { + /* need to wait for guard time */ + scrTimeout(t0SendByteSM,sc,t0sbcTGuardTime,sc->clkCountDataSend * (12 + sc->N)); + sc->t0SendByteS = t0sbsWaitGuardTime; + + } + break; + + default: + INVALID_STATE_CMD(sc, sc->t0SendByteS,cmd); + break; + } + break; + + + case t0sbsWaitGuardTime: + switch (cmd) + { + case t0sbcTGuardTime: + TOGGLE_TEST_PIN(); + /* set start bit */ + scrTimeout(t0SendByteSM,sc,t0sbcTClockData,sc->clkCountDataSend); + scrSetData(FALSE); + sc->t0SendByteS = t0sbsClockData; + break; + + default: + INVALID_STATE_CMD(sc, sc->t0SendByteS,cmd); + break; + } + break; + + + case t0sbsClockData: + switch (cmd) + { + case t0sbcTClockData: + TOGGLE_TEST_PIN(); + /* clock out data bit */ + if (sc->shiftBits < 8) + { + if (sc->convention == CONVENTION_INVERSE) + { + if (sc->shiftByte & 0x80) + { + scrSetData(FALSE); + sc->shiftParity++; + } + else + { + scrSetData(TRUE); + } + sc->shiftByte = sc->shiftByte << 1; + } + else + { + ASSERT(sc->convention == CONVENTION_DIRECT); + if (sc->shiftByte & 0x01) + { + scrSetData(TRUE); + sc->shiftParity++; + } + else + { + scrSetData(FALSE); + } + sc->shiftByte = sc->shiftByte >> 1; + } + sc->shiftBits++; + scrTimeout(t0SendByteSM,sc,t0sbcTClockData,sc->clkCountDataSend); + } + + /* clock out parity bit */ + else if (sc->shiftBits == 8) + { + if ( ((sc->shiftParity & 0x01) && (sc->convention == CONVENTION_INVERSE)) || + (!(sc->shiftParity & 0x01) && (sc->convention == CONVENTION_DIRECT)) ) + { + scrSetData(FALSE); + } + else + { + scrSetData(TRUE); + } + sc->shiftBits++; + scrTimeout(t0SendByteSM,sc,t0sbcTClockData,sc->clkCountDataSend); + } + + /* all data shifted out, move onto next state */ + else + { + ASSERT(sc->shiftBits > 8); + scrSetData(TRUE); + scrTimeout(t0SendByteSM,sc,t0sbcTError,sc->clkCountDataSend); + sc->t0SendByteS = t0sbsWaitError; + } + break; + + default: + INVALID_STATE_CMD(sc, sc->t0SendByteS,cmd); + break; + } + break; + + case t0sbsWaitError: + switch (cmd) + { + case t0sbcTError: + /* no error indicated*/ + if (scrGetData()) + { + sc->t0SendByteS = t0sbsIdle; + sc->t0ByteParent(sc,gcT0SendByte); + } + + /* got error */ + else + { + /* got parity error */ + if (sc->shiftParityCount < PARITY_ERROR_MAX) + { + sc->shiftParityCount++; + scrTimeout(t0SendByteSM,sc,t0sbcTResend,sc->clkCountDataSend * 2); + sc->t0SendByteS = t0sbsWaitResend; + } + else + { + /* too many parity errors, just give up on this sc->dataByte */ + sc->status = ERROR_PARITY; + sc->t0SendByteS = t0sbsIdle; + sc->t0ByteParent(sc,gcT0SendByteErr); + } + } + break; + + default: + INVALID_STATE_CMD(sc, sc->t0SendByteS,cmd); + break; + } + break; + + case t0sbsWaitResend: + switch (cmd) + { + case t0sbcTResend: + sc->shiftBits = 0; + sc->shiftParity = 0; + sc->shiftByte = sc->dataByte; + /* set start bit */ + + scrTimeout(t0SendByteSM,sc,t0sbcTClockData,sc->clkCountDataSend); + scrSetData(FALSE); + sc->t0SendByteS = t0sbsClockData; + break; + + default: + INVALID_STATE_CMD(sc, sc->t0SendByteS,cmd); + break; + } + break; + + + default: + INVALID_STATE_CMD(sc, sc->t0SendByteS,cmd); + break; + } +} + + + + + + + + + + + +/* +**++ +** FUNCTIONAL DESCRIPTION: +** +** cardOff +** +** Turn all signals to the card off +** +** FORMAL PARAMETERS: +** +** sc - Pointer to the softc structure. +** +** IMPLICIT INPUTS: +** +** nill +** +** IMPLICIT OUTPUTS: +** +** nill +** +** FUNCTION VALUE: +** +** nill +** +** SIDE EFFECTS: +** +** nill +**-- +*/ +static void cardOff (struct scr_softc * sc) +{ + scrSetReset(TRUE); + scrSetDataHighZ(); + scrSetClock(FALSE); + scrSetPower(FALSE); +} + + + + +/* +** +** +** **************** timer routines *************** +** +*/ + +/* +**++ +** FUNCTIONAL DESCRIPTION: +** +** scrClkInit +** +** Init the callout queues. The callout queues are used +** by the timeout/untimeout queues +** +** FORMAL PARAMETERS: +** +** nill +** +** IMPLICIT INPUTS: +** +** nill +** +** IMPLICIT OUTPUTS: +** +** nill +** +** FUNCTION VALUE: +** +** nill +** +** SIDE EFFECTS: +** +** nill +**-- +*/ +static void scrClkInit(void) +{ + + int lc; + Callout *c; + Callout *new; + + scrClkCallTodo.c_next = NULL; + scrClkCallFree = &scrClkCalloutArray[0]; + c = scrClkCallFree; + + for (lc = 1; lc < SCR_CLK_CALLOUT_COUNT; lc++) + { + new = &scrClkCalloutArray[lc]; + c->c_next = new; + c = new; + } + + c->c_next = NULL; +} + + +/* +**++ +** FUNCTIONAL DESCRIPTION: +** +** scrClkStart +** +** This function starts the clock running. The clock is reall the +** HAT clock (High Available Timer) that is using a FIQ (fast interrupt +** request). +** +** FORMAL PARAMETERS: +** +** sc - Pointer to the softc structure. +** countPerTick - value for T2 timer that drives FIQ +** +** IMPLICIT INPUTS: +** +** nill +** +** IMPLICIT OUTPUTS: +** +** nill +** +** FUNCTION VALUE: +** +** nill +** +** SIDE EFFECTS: +** +** nill +**-- +*/ +static void scrClkStart(struct scr_softc * sc,int countPerTick) +{ + u_int savedInts; + + savedInts = disable_interrupts(I32_bit | F32_bit); + + + + ASSERT(scrClkCallTodo.c_next == NULL); + ASSERT(!scrClkEnable); + scrClkEnable = 1; + scrClkCount = countPerTick; + + hatClkOn(countPerTick, + hatClkIrq, + 0xdeadbeef, + hatStack + HATSTACKSIZE - sizeof(unsigned), + myHatWedge); + + restore_interrupts(savedInts); +} + +/* +**++ +** FUNCTIONAL DESCRIPTION: +** +** scrClkAdj +** +** Adjusts the frequence of the clock +** +** FORMAL PARAMETERS: +** +** count - new value for T2 timer that drives FIQ +** +** IMPLICIT INPUTS: +** +** nill +** +** IMPLICIT OUTPUTS: +** +** nill +** +** FUNCTION VALUE: +** +** nill +** +** SIDE EFFECTS: +** +** nill +**-- +*/ +static void scrClkAdj (int count) +{ + u_int savedInts; + + if (count != scrClkCount) + { + savedInts = disable_interrupts(I32_bit | F32_bit); + + ASSERT(scrClkEnable); + + scrClkCount = count; + hatClkAdjust(count); + + restore_interrupts(savedInts); + } +} + +/* +**++ +** FUNCTIONAL DESCRIPTION: +** +** scrClkStop +** +** Stops the clock +** +** FORMAL PARAMETERS: +** +** nill +** +** +** IMPLICIT INPUTS: +** +** nill +** +** IMPLICIT OUTPUTS: +** +** nill +** +** FUNCTION VALUE: +** +** nill +** +** SIDE EFFECTS: +** +** nill +**-- +*/ +static void scrClkStop(void) +{ + u_int savedInts; + savedInts = disable_interrupts(I32_bit | F32_bit); + + ASSERT(scrClkEnable); + scrClkEnable = 0; + ASSERT(scrClkCallTodo.c_next == NULL); + hatClkOff(); + + restore_interrupts(savedInts); +} + + + +/* +**++ +** FUNCTIONAL DESCRIPTION: +** +** hatClkIrq +** +** This is what the HAT clock calls. This call drives +** the timeout queues, which in turn drive the state machines +** +** Be very carefully when calling a timeout as the function +** that is called may in turn do timeout/untimeout calls +** before returning +** +** FORMAL PARAMETERS: +** +** int x - not used +** +** IMPLICIT INPUTS: +** +** nill +** +** IMPLICIT OUTPUTS: +** +** nill +** +** FUNCTION VALUE: +** +** nill +** +** SIDE EFFECTS: +** +** a timeout may be called if it is due +**-- +*/ +static void hatClkIrq(int x) +{ + register Callout *p1; + register int needsoft =0; + register Callout *c; + register int arg; + register void (*func) __P((struct scr_softc*,int)); + struct scr_softc * sc; + + ASSERT(scrClkEnable); + for (p1 = scrClkCallTodo.c_next; p1 != NULL; p1 = p1->c_next) + { + p1->c_time -= scrClkCount; + + if (p1->c_time > 0) + { + break; + } + needsoft = 1; + if (p1->c_time == 0) + { + break; + } + } + + + if (needsoft) + { + while ((c = scrClkCallTodo.c_next) != NULL && c->c_time <= 0) + { + func = c->c_func; + sc = c->c_sc; + arg = c->c_arg; + scrClkCallTodo.c_next = c->c_next; + c->c_next = scrClkCallFree; + scrClkCallFree = c; + (*func)(sc,arg); + } + } +} + +/* +**++ +** FUNCTIONAL DESCRIPTION: +** +** myHatWedge +** +** Called if the HAT timer becomes clogged/wedged. Not +** used by this driver, we let upper layers recover +** from this condition +** +** FORMAL PARAMETERS: +** +** int nFIQs - not used +** +** IMPLICIT INPUTS: +** +** nill +** +** IMPLICIT OUTPUTS: +** +** nill +** +** FUNCTION VALUE: +** +** nill +** +** SIDE EFFECTS: +** +** nill +**-- +*/ +static void myHatWedge(int nFIQs) +{ + #ifdef DEBUG + printf("myHatWedge: nFIQ = %d\n",nFIQs); + #endif +} + + + +/* +**++ +** FUNCTIONAL DESCRIPTION: +** +** scrTimeout +** +** Execute a function after a specified length of time. +** +** +** FORMAL PARAMETERS: +** +** ftn - function to execute +** sc - pointer to soft c +** arg - argument passed to function +** count - number of T2 counts for timeout +** +** IMPLICIT INPUTS: +** +** nill +** +** IMPLICIT OUTPUTS: +** +** nill +** +** FUNCTION VALUE: +** +** nill +** +** SIDE EFFECTS: +** +** nill +**-- +*/ + +static void scrTimeout(ftn, sc, arg, count) + void (*ftn) __P((struct scr_softc*,int)); + struct scr_softc* sc; + int arg; + register int count; +{ + + register Callout *new, *p, *t; + ASSERT(scrClkEnable); + + + if (count <= 0) + { + count = 1; + } + + + /* Fill in the next free fcallout structure. */ + if (scrClkCallFree == NULL) + { + panic("timeout table full"); + } + + new = scrClkCallFree; + scrClkCallFree = new->c_next; + new->c_sc = sc; + new->c_arg = arg; + new->c_func = ftn; + + /* + * The time for each event is stored as a difference from the time + * of the previous event on the queue. Walk the queue, correcting + * the counts argument for queue entries passed. Correct the counts + * value for the queue entry immediately after the insertion point + * as well. Watch out for negative c_time values; these represent + * overdue events. + */ + for (p = &scrClkCallTodo; (t = p->c_next) != NULL && count > t->c_time; p = t) + { + if (t->c_time > 0) + { + count -= t->c_time; + } + } + + + new->c_time = count; + if (t != NULL) + { + t->c_time -= count; + } + + /* Insert the new entry into the queue. */ + p->c_next = new; + new->c_next = t; +} + +/* +**++ +** FUNCTIONAL DESCRIPTION: +** +** scrUntimeout +** +** Cancel previous timeout function call. +** +** FORMAL PARAMETERS: +** +** ftn - function of timeout to cancel +** sc - sc of timeout to cancel +** arg - arg of timeout to cancel +** +** IMPLICIT INPUTS: +** +** nill +** +** IMPLICIT OUTPUTS: +** +** nill +** +** FUNCTION VALUE: +** +** nill +** +** SIDE EFFECTS: +** +** nill +**-- +*/ +static void scrUntimeout(ftn, sc, arg) +void (*ftn) __P((struct scr_softc*,int)); +struct scr_softc* sc; +int arg; +{ + register Callout *p, *t; + ASSERT(scrClkEnable); + + for (p = &scrClkCallTodo; (t = p->c_next) != NULL; p = t) + { + if (t->c_func == ftn && t->c_sc == sc && t->c_arg == arg) + { + /* Increment next entry's count. */ + if (t->c_next && t->c_time > 0) + { + t->c_next->c_time += t->c_time; + } + + /* Move entry from fcallout queue to scrClkCallFree queue. */ + p->c_next = t->c_next; + t->c_next = scrClkCallFree; + scrClkCallFree = t; + break; + } + } +} + + + + + + + + + + + + + + + +/******************* routines used only during debugging */ +#ifdef SCR_DEBUG + +/* +**++ +** FUNCTIONAL DESCRIPTION: +** +** invalidStateCmd +** +** Debugging function. Printout information about problem +** and then kick in the debugger or panic +** +** FORMAL PARAMETERS: +** +** sc - pointer to soft c +** state - state of machine +** cmd - command of machine +** line - line that problem was detected +** +** +** IMPLICIT INPUTS: +** +** nill +** +** IMPLICIT OUTPUTS: +** +** nill +** +** FUNCTION VALUE: +** +** nill +** +** SIDE EFFECTS: +** +** nill +**-- +*/ +void invalidStateCmd (struct scr_softc* sc,int state,int cmd,int line) +{ + printf("INVALID_STATE_CMD: sc = %X, state = %X, cmd = %X, line = %d\n",sc,state,cmd,line); + DEBUGGER; +} + +/* +**++ +** FUNCTIONAL DESCRIPTION: +** +** getText +** +** Get text representation of state or command +** +** FORMAL PARAMETERS: +** +** x - state or command +** +** IMPLICIT INPUTS: +** +** nill +** +** IMPLICIT OUTPUTS: +** +** nill +** +** FUNCTION VALUE: +** +** nill +** +** SIDE EFFECTS: +** +** nill +**-- +*/ +char * getText(int x) +{ + switch (x) + { + /* commands to Master State Machine (mc = Master Command )*/ + case mcOn: return "mcOn"; + case mcT0DataSend: return "mcT0DataSend"; + case mcT0DataRecv: return "mcT0DataRecv"; + case mcColdReset: return "mcColdReset"; + case mcATR: return "mcATR"; + case mcT0Send: return "mcT0Send"; + case mcT0Recv: return "mcT0Recv"; + + /* states in Master state machine (ms = Master State) */ + case msIdleOff: return "msIdleOff"; + case msColdReset: return "msColdReset"; + case msATR: return "msATR"; + case msIdleOn: return "msIdleOn"; + case msT0Send: return "msT0Send"; + case msT0Recv: return "msT0Recv"; + + + + /* commands to T0 send state machine */ + case t0scStart: return "t0scStart"; + case t0scTWorkWaiting: return "t0scTWorkWaiting"; + + + /* states in T0 send state machine */ + case t0ssIdle: return "t0ssIdle"; + case t0ssSendHeader: return "t0ssSendHeader"; + case t0ssRecvProcedure: return "t0ssRecvProcedu"; + case t0ssSendByte: return "t0ssSendByte"; + case t0ssSendData: return "t0ssSendData"; + case t0ssRecvSW1: return "t0ssRecvSW1"; + case t0ssRecvSW2: return "t0ssRecvSW2"; + + + /* commands to T0 recv state machine */ + case t0rcStart: return "t0rcStart"; + case t0rcTWorkWaiting: return "t0rcTWorkWaiting"; + + /* states in T0 recv state machine */ + case t0rsIdle: return "t0rsIdle"; + case t0rsSendHeader: return "t0rsSendHeader"; + case t0rsRecvProcedure: return "t0rsRecvProcedure"; + case t0rsRecvByte: return "t0rsRecvByte"; + case t0rsRecvData: return "t0rsRecvData"; + case t0rsRecvSW1: return "t0rsRecvSW1"; + case t0rsRecvSW2: return "t0rsRecvSW2"; + + + + + + /* commands to Answer To Reset (ATR) state machine */ + case atrcStart: return "atrcStart"; + case atrcT3: return "0x0b04"; + case atrcTWorkWaiting: return "atrcTWorkWaiting"; + + + /* states in in Anser To Reset (ATR) state machine */ + case atrsIdle: return "atrsIdle"; + case atrsTS: return "atrsTS"; + case atrsT0: return "atrsT0"; + case atrsTABCD: return "atrsTABCD"; + case atrsTK: return "atrsTK"; + case atrsTCK: return "atrsTCK"; + + + + /* commands to T0 Recv Byte state machine */ + case t0rbcStart: return "t0rbcStart"; + case t0rbcAbort: return "t0rbcAbort"; + + case t0rbcTFindStartEdge:return "t0rbcTFindStartEdge"; + case t0rbcTFindStartMid: return "t0rbcTFindStartMid"; + case t0rbcTClockData: return "t0rbcTClockData"; + case t0rbcTErrorStart: return "t0rbcTErrorStart"; + case t0rbcTErrorStop: return "t0rbcTErrorStop"; + + /* states in in TO Recv Byte state machine */ + case t0rbsIdle: return "t0rbsIdle"; + case t0rbsFindStartEdge: return "t0rbcFindStartEdge"; + case t0rbsFindStartMid: return "t0rbcFindStartMid"; + case t0rbsClockData: return "t0rbcClockData"; + case t0rbsSendError: return "t0rbcSendError"; + + + /* commands to T0 Send Byte state machine */ + case t0sbcStart: return "t0sbcStart"; + case t0sbcAbort: return "t0sbcAbort"; + case t0sbcTGuardTime: return "t0sbcTGuardTime"; + case t0sbcTClockData: return "t0sbcTClockData"; + case t0sbcTError: return "t0sbcTError"; + case t0sbcTResend: return "t0sbcTResend"; + + /* states in in T0 Send Byte state machine */ + case t0sbsIdle: return "t0sbsIdle"; + case t0sbsClockData: return "t0sbsClockData"; + case t0sbsWaitError: return "t0sbsWaitError"; + case t0sbsWaitResend: return "t0sbsWaitResend"; + case t0sbsWaitGuardTime: return "t0sbsWaitGuardTime"; + + + case gcT0RecvByte: return "gcT0RecvByte"; + case gcT0RecvByteErr: return "gcT0RecvByteErr"; + case gcT0SendByte: return "gcT0SendByte"; + case gcT0SendByteErr: return "gcT0SendByteErr"; + + + case crcStart: return "crcStart"; + case crcT2: return "crcT2"; + + + default: + printf("unkown case, %x\n",x); + break; + } + return "???"; +} + +#endif /* SCR_DEBUG */ + + + diff --git a/sys/arch/dnard/dnard/sequoia.c b/sys/arch/dnard/dnard/sequoia.c new file mode 100644 index 000000000000..d0ca8839dd76 --- /dev/null +++ b/sys/arch/dnard/dnard/sequoia.c @@ -0,0 +1,775 @@ +/* $NetBSD: sequoia.c,v 1.1 2001/05/09 15:58:08 matt Exp $ */ + +/* + * Copyright 1997 + * Digital Equipment Corporation. All rights reserved. + * + * This software is furnished under license and may be used and + * copied only in accordance with the following terms and conditions. + * Subject to these conditions, you may download, copy, install, + * use, modify and distribute this software in source and/or binary + * form. No title or ownership is transferred hereby. + * + * 1) Any source code used, modified or distributed must reproduce + * and retain this copyright notice and list of conditions as + * they appear in the source file. + * + * 2) No right is granted to use any trade name, trademark, or logo of + * Digital Equipment Corporation. Neither the "Digital Equipment + * Corporation" name nor any trademark or logo of Digital Equipment + * Corporation may be used to endorse or promote products derived + * from this software without the prior written permission of + * Digital Equipment Corporation. + * + * 3) This software is provided "AS-IS" and any express or implied + * warranties, including but not limited to, any implied warranties + * of merchantability, fitness for a particular purpose, or + * non-infringement are disclaimed. In no event shall DIGITAL be + * liable for any damages whatsoever, and in particular, DIGITAL + * shall not be liable for special, indirect, consequential, or + * incidental damages or damages for lost profits, loss of + * revenue or loss of use, whether such damages arise in contract, + * negligence, tort, under statute, in equity, at law or otherwise, + * even if advised of the possibility of such damage. + */ + +/* +** +** INCLUDE FILES +** +*/ + +#include +#include +#include +#include +#include +#include +#include +#include + + +#include +#include +#include +#include +#include + + + + + +/* +** +** MACROS +** +*/ +#define SET(t, f) (t) |= (f) +#define CLR(t, f) (t) &= ~(f) +#define ISSET(t, f) ((t) & (f)) +#define ISCLR(t, f) ( ((t) & (f)) == 0) + +/* define regisers on sequoia used by pins */ +#define SEQUOIA_1GPIO PMC_GPCR_REG /* reg 0x007 gpio 0-3 */ +#define SEQUOIA_2GPIO SEQ2_OGPIOCR_REG /* reg 0x304 gpio 4.8 */ + +/* define pins on sequoia that talk to smart card reader */ +#define SCR_DETECT_DIR GPIOCR2_M_GPIOBDIR0 +#define SCR_DETECT GPIOCR2_M_GPIOBDATA0 + + +#define SCR_POWER_DIR GPCR_M_GPIODIR0 +#define SCR_POWER GPCR_M_GPIODATA0 + +#define SCR_RESET_DIR GPCR_M_GPIODIR1 +#define SCR_RESET GPCR_M_GPIODATA1 + +#define SCR_CLOCK_DIR OGPIOCR_M_GPIODIR6 +#define SCR_CLOCK OGPIOCR_M_GPIODATA6 + +#define SCR_DATA_IN_DIR GPCR_M_GPIODIR2 +#define SCR_DATA_IN GPCR_M_GPIODATA2 + +#define SCR_DATA_OUT_DIR OGPIOCR_M_GPIODIR5 +#define SCR_DATA_OUT OGPIOCR_M_GPIODATA5 + +#define SCR_BUGA_DIR OGPIOCR_M_GPIODIR4 +#define SCR_BUGA OGPIOCR_M_GPIODATA4 + +#define SCR_BUGB_DIR OGPIOCR_M_GPIODIR7 +#define SCR_BUGB OGPIOCR_M_GPIODATA7 + + + +/* define pins on sequoia that talk to leds */ +#define LED_BILED_YELLOW_BIT FOMPCR_M_PCON5 +#define LED_BILED_GREEN_BIT FOMPCR_M_PCON6 + +#define LED_DEBUG_YELLOW_BIT FOMPCR_M_PCON7 +#define LED_DEBUG_GREEN_BIT FOMPCR_M_PCON8 + + +/* define biled colors */ +#define LED_BILED_NONE 0 +#define LED_BILED_GREEN 1 +#define LED_BILED_YELLOW 2 +#define LED_BILED_RED 3 + + +#define LED_TIMEOUT HZ / 20 /* 20 times a second */ +#define LED_NET_ACTIVE (1000000/HZ) * LED_TIMEOUT /* delay in us for net activity */ + + + + +/* +** +** DATA +** +*/ +static bus_space_handle_t sequoia_ioh; + +static struct timeval ledLastActive; /* last time we get net activity */ +static int ledColor; /* present color of led */ +static int ledBlockCount;; /* reference count of block calles */ +int sequoia_index_cache = -1; /* set to silly value so that we dont cache on init */ + +static struct callout led_timo_ch = CALLOUT_INITIALIZER; + +/* +** +** FUNCITONAL PROTOTYPES +** +*/ +static void ledSetBiled(int color); +static void ledTimeout(void * arg); + +/* +** +** FUNCITONS +** +*/ +void sequoiaInit(void) +{ + u_int16_t seqReg; + + /* map the sequoi registers */ + if (bus_space_map(&isa_io_bs_tag, SEQUOIA_BASE, SEQUOIA_NPORTS, 0, &sequoia_ioh)) + { + panic("SequoiaInit: io mapping failed"); + } + + /* + ** + ** setup the pins associated with the X server + ** + */ + /* seems power on sets them correctly */ + + + + /* + ** setup the pins associated with the led + */ + sequoiaRead(SEQR_SEQPSR1_REG,&seqReg); + SET(seqReg,SEQPSR1_M_TAGDEN); /* enable pc[4:9] */ + sequoiaWrite(SEQR_SEQPSR1_REG,seqReg); + + + sequoiaRead(SEQR_SEQPSR3_REG,&seqReg); + CLR(seqReg,SEQPSR3_M_PC5PINEN); /* enable pc5, biled */ + CLR(seqReg,SEQPSR3_M_PC6PINEN); /* enable pc6, biled */ + CLR(seqReg,SEQPSR3_M_PC7PINEN); /* enable pc7, debug led yellow */ + CLR(seqReg,SEQPSR3_M_PC8PINEN); /* enable pc8, debug led green */ + sequoiaWrite(SEQR_SEQPSR3_REG,seqReg); + + sequoiaRead (PMC_FOMPCR_REG, &seqReg); + CLR(seqReg,LED_BILED_YELLOW_BIT); + CLR(seqReg,LED_BILED_GREEN_BIT); + SET(seqReg,LED_DEBUG_YELLOW_BIT); + CLR(seqReg,LED_DEBUG_GREEN_BIT); + sequoiaWrite(PMC_FOMPCR_REG, seqReg); + + + /* setup the biled info */ + ledColor = LED_BILED_GREEN; + ledLastActive.tv_usec = 0; + ledLastActive.tv_sec = 0; + ledBlockCount = 0; + callout_reset(&led_timo_ch, LED_TIMEOUT, ledTimeout, NULL); + /* + ** + ** setup the pins associated with the smart card reader * + ** + */ + /* sequoia 1 direction & data */ + + sequoiaRead(SEQUOIA_1GPIO,&seqReg); + + SET(seqReg,SCR_POWER_DIR); /* output */ + SET(seqReg,SCR_RESET_DIR); /* output */ + CLR(seqReg,SCR_DATA_IN_DIR); /* input */ + + CLR(seqReg,SCR_POWER); /* 0V to card */ + SET(seqReg,SCR_RESET); /* 0V to card */ + + sequoiaWrite(SEQUOIA_1GPIO,seqReg); + + + + + /* sequoia 2 pin enables */ + sequoiaRead(SEQ2_SEQ2PSR_REG,&seqReg); + + SET(seqReg,SEQ2PSR_M_DPBUSEN); + CLR(seqReg,SEQ2PSR_M_GPIOPINEN); + + sequoiaWrite(SEQ2_SEQ2PSR_REG,seqReg); + + + + /* sequoia 2 direction & data */ + sequoiaRead(SEQUOIA_2GPIO,&seqReg); + + SET(seqReg,SCR_BUGA_DIR); /* output */ + SET(seqReg,SCR_DATA_OUT_DIR); /* output */ + SET(seqReg,SCR_CLOCK_DIR); /* output */ + SET(seqReg,SCR_BUGB_DIR); /* output */ + + CLR(seqReg,SCR_BUGA); /* 0 */ + CLR(seqReg,SCR_BUGB); /* 0 */ + CLR(seqReg,SCR_CLOCK); /* 0 */ + sequoiaWrite(SEQUOIA_2GPIO,seqReg); + + /* setup the wak0 pin to be detect */ + sequoiaRead(SEQR_SEQPSR2_REG,&seqReg); + + SET(seqReg,SEQPSR2_M_DIRTYPINEN); + SET(seqReg,SEQPSR2_M_GPIOB0PINEN); + + sequoiaWrite(SEQR_SEQPSR2_REG,seqReg); + + + sequoiaRead(PMC_GPIOCR2_REG,&seqReg); + + CLR(seqReg,SCR_DETECT_DIR); /* input */ + + sequoiaWrite(PMC_GPIOCR2_REG,seqReg); + + /* don't delay when setting PC bits. this is particularly important + for using PC[4] to clear the FIQ. */ + sequoiaRead(PMC_SCCR_REG, &seqReg); + sequoiaWrite(PMC_SCCR_REG, seqReg | SCCR_M_PCSTGDIS); + +} + + + + + +/* X console functions */ +void consXTvOn(void) +{ + u_int16_t savedPSR3; + u_int16_t savedFMPCR; + /* + ** Switch on TV output on the Sequoia, data indicates mode, + ** but we are currently hardwired to NTSC, so ignore it. + */ + + sequoiaRead (SEQR_SEQPSR3_REG, &savedPSR3); + sequoiaWrite(SEQR_SEQPSR3_REG, (savedPSR3 | SEQPSR3_M_PC3PINEN)); + + sequoiaRead (PMC_FOMPCR_REG, &savedFMPCR); + sequoiaWrite(PMC_FOMPCR_REG, (savedFMPCR | FOMPCR_M_PCON3)); + +} + +void consXTvOff(void) +{ + u_int16_t savedPSR3; + u_int16_t savedFMPCR; + /* + ** Switch off TV output on the Seqoia + */ + sequoiaRead (SEQR_SEQPSR3_REG, &savedPSR3); + sequoiaWrite(SEQR_SEQPSR3_REG, (savedPSR3 & ~SEQPSR3_M_PC3PINEN)); + + sequoiaRead (PMC_FOMPCR_REG, &savedFMPCR); + sequoiaWrite(PMC_FOMPCR_REG, (savedFMPCR & ~FOMPCR_M_PCON3)); + +} + + + + + /* smart card routines */ + +int scrGetDetect (void) +{ + int r; + u_int16_t seqReg; + + sequoiaRead(PMC_GPIOCR2_REG,&seqReg); + + /* inverse logic, so invert */ + if (ISSET(seqReg,SCR_DETECT)) + { + r = 0; + } else + { + r = 1; + } + + return r; +} + + +void scrSetPower (int value) +{ + u_int16_t seqReg; +#ifdef SHARK + u_int savedints; + + savedints = disable_interrupts(I32_bit | F32_bit); +#endif + + sequoiaRead(SEQUOIA_1GPIO,&seqReg); + + if (value) + { + SET(seqReg,SCR_POWER); + } else + { + CLR(seqReg,SCR_POWER); + } + sequoiaWrite(SEQUOIA_1GPIO,seqReg); + +#ifdef SHARK + restore_interrupts(savedints); +#endif +} + +void scrSetClock (int value) +{ + u_int16_t seqReg; +#ifdef SHARK + u_int savedints; + + savedints = disable_interrupts(I32_bit | F32_bit); +#endif + + sequoiaRead(SEQUOIA_2GPIO,&seqReg); + + if (value) + { + SET(seqReg,SCR_CLOCK); + } else + { + CLR(seqReg,SCR_CLOCK); + } + sequoiaWrite(SEQUOIA_2GPIO,seqReg); +#ifdef SHARK + restore_interrupts(savedints); +#endif +} + +void scrSetReset (int value) +{ + u_int16_t seqReg; +#ifdef SHARK + u_int savedints; + + savedints = disable_interrupts(I32_bit | F32_bit); +#endif + + sequoiaRead(SEQUOIA_1GPIO,&seqReg); + + if (value) + { + SET(seqReg,SCR_RESET); + } else + { + CLR(seqReg,SCR_RESET); + } + sequoiaWrite(SEQUOIA_1GPIO,seqReg); + +#ifdef SHARK + restore_interrupts(savedints); +#endif +} + + +void scrSetDataHighZ (void) +{ + u_int16_t seqReg; +#ifdef SHARK + u_int savedints; + + savedints = disable_interrupts(I32_bit | F32_bit); +#endif + + sequoiaRead(SEQUOIA_2GPIO,&seqReg); + + /* set data to 5V, io pin is inverse logic */ + CLR(seqReg,SCR_DATA_OUT); + + sequoiaWrite(SEQUOIA_2GPIO,seqReg); +#ifdef SHARK + restore_interrupts(savedints); +#endif +} + +void scrSetData (int value) +{ + u_int16_t seqReg; +#ifdef SHARK + u_int savedints; + + savedints = disable_interrupts(I32_bit | F32_bit); +#endif + + sequoiaRead(SEQUOIA_2GPIO,&seqReg); + /* inverse logic */ + if (value ) + { + CLR(seqReg,SCR_DATA_OUT); + } else + { + SET(seqReg,SCR_DATA_OUT); + } + sequoiaWrite(SEQUOIA_2GPIO,seqReg); +#ifdef SHARK + restore_interrupts(savedints); +#endif +} + +int scrGetData (void) +{ + int r; + u_int16_t seqReg; + + sequoiaRead(SEQUOIA_1GPIO,&seqReg); + + if (ISSET(seqReg,SCR_DATA_IN)) + { + r = 1; + } else + { + r = 0; + } + return r; +} + + + + + + + + +void ledNetActive (void) +{ + ledLastActive = time; +} + +void ledNetBlock (void) +{ + ledBlockCount++; +} + +void ledNetUnblock (void) +{ + ledBlockCount--; +} + +void ledPanic (void) +{ + /* we are in panic, timeout wont happen, so set led */ + ledSetBiled(LED_BILED_RED); +} + +static void ledTimeout(void * arg) +{ + int timeSpan; /* in usec */ + + if(time.tv_sec == ledLastActive.tv_sec) + { + timeSpan = time.tv_usec - ledLastActive.tv_usec; + } + + else if (time.tv_sec - 10 < ledLastActive.tv_sec) /* stop rollover problems */ + { + timeSpan = (1000000 + time.tv_usec) - ledLastActive.tv_usec; + } + + else + { + timeSpan = LED_NET_ACTIVE * 2; /* ie big number */ + } + + + + /* check if we are blocked */ + if(ledBlockCount) + { + if(ledColor == LED_BILED_YELLOW) + { + ledSetBiled(LED_BILED_NONE); + } + else + { + ledSetBiled(LED_BILED_YELLOW); + } + } + + + /* check if we have network activity */ + else if (timeSpan < LED_NET_ACTIVE) + { + if(ledColor == LED_BILED_GREEN) + { + ledSetBiled(LED_BILED_NONE); + } + else + { + ledSetBiled(LED_BILED_GREEN); + } + } + + /* normal operating mode */ + else + { + if(ledColor != LED_BILED_GREEN) + { + ledSetBiled(LED_BILED_GREEN); + } + } + + /* resubmint the timeout */ + callout_reset(&led_timo_ch, LED_TIMEOUT, ledTimeout, NULL); + +} + + +static void ledSetBiled(int color) +{ + u_int16_t seqReg; +#ifdef SHARK + u_int savedints; + + savedints = disable_interrupts(I32_bit | F32_bit); +#endif + ledColor = color; + + + sequoiaRead (PMC_FOMPCR_REG, &seqReg); + switch(color) + { + case LED_BILED_NONE: + SET(seqReg,LED_BILED_YELLOW_BIT); + SET(seqReg,LED_BILED_GREEN_BIT); + break; + + case LED_BILED_YELLOW: + CLR(seqReg,LED_BILED_YELLOW_BIT); + SET(seqReg,LED_BILED_GREEN_BIT); + break; + + case LED_BILED_GREEN: + SET(seqReg,LED_BILED_YELLOW_BIT); + CLR(seqReg,LED_BILED_GREEN_BIT); + break; + + case LED_BILED_RED: + CLR(seqReg,LED_BILED_YELLOW_BIT); + CLR(seqReg,LED_BILED_GREEN_BIT); + break; + + default: + panic("invalid color %x\n",color); + break; + } + sequoiaWrite(PMC_FOMPCR_REG, seqReg); +#ifdef SHARK + restore_interrupts(savedints); +#endif +} + + +int hwGetRev(void) +{ + u_int16_t seqReg; + + sequoiaRead(SR_POR_REG,&seqReg); + + seqReg = seqReg >> POR_V_MISCCF0; + seqReg = seqReg & 0x7; + + return seqReg; +} + + + + + +/* routines to read/write to sequoia registers */ +void sequoiaWrite(int reg,u_int16_t seqReg) +{ +#ifdef SHARK + u_int savedints; + + savedints = disable_interrupts(I32_bit | F32_bit); +#endif + + /* + On SHARK, the fiq comes from the pmi/smi. After receiving + a FIQ, the SMI must be cleared. The SMI gets cleared by + changing to sleep mode, thereby lowering PC[4]. */ + // need to do the right thing with the cache if this is going to work */ + if (reg == PMC_FOMPCR_REG) { + bus_space_write_2(&isa_io_bs_tag,sequoia_ioh,SEQUOIA_INDEX_OFFSET,reg); + bus_space_write_2(&isa_io_bs_tag,sequoia_ioh,SEQUOIA_DATA_OFFSET, + seqReg | (FOMPCR_M_PCON4)); + bus_space_write_2(&isa_io_bs_tag,sequoia_ioh,SEQUOIA_INDEX_OFFSET, + PMC_SLPMPCR_REG); + bus_space_write_2(&isa_io_bs_tag,sequoia_ioh,SEQUOIA_DATA_OFFSET, + seqReg & ~(SLPMPCR_M_PCSLP4)); + sequoia_index_cache = PMC_SLPMPCR_REG; + } else { + /* normal case: just do the write */ + if(sequoia_index_cache != reg) + { + sequoia_index_cache = reg; + bus_space_write_2(&isa_io_bs_tag,sequoia_ioh,SEQUOIA_INDEX_OFFSET,reg); + } + bus_space_write_2(&isa_io_bs_tag,sequoia_ioh,SEQUOIA_DATA_OFFSET,seqReg); + } +#ifdef SHARK + restore_interrupts(savedints); +#endif +} + +void sequoiaRead (int reg,u_int16_t * seqReg_ptr) +{ +#ifdef SHARK + u_int savedints; + + savedints = disable_interrupts(I32_bit | F32_bit); +#endif + if(sequoia_index_cache != reg) + { + sequoia_index_cache = reg; + bus_space_write_2(&isa_io_bs_tag,sequoia_ioh,SEQUOIA_INDEX_OFFSET,reg); + } + *seqReg_ptr = bus_space_read_2(&isa_io_bs_tag,sequoia_ioh,SEQUOIA_DATA_OFFSET); +#ifdef SHARK + restore_interrupts(savedints); +#endif +} + + +void ledSetDebug(int command) +{ + u_int16_t seqReg; +#ifdef SHARK + u_int savedints; + + savedints = disable_interrupts(I32_bit | F32_bit); +#endif + sequoiaRead (PMC_FOMPCR_REG, &seqReg); + + + switch (command) + { + case LED_DEBUG_STATE_0: + CLR(seqReg,LED_DEBUG_YELLOW_BIT); + CLR(seqReg,LED_DEBUG_GREEN_BIT); + break; + + case LED_DEBUG_STATE_1: + SET(seqReg,LED_DEBUG_YELLOW_BIT); + CLR(seqReg,LED_DEBUG_GREEN_BIT); + break; + + case LED_DEBUG_STATE_2: + CLR(seqReg,LED_DEBUG_YELLOW_BIT); + SET(seqReg,LED_DEBUG_GREEN_BIT); + break; + + case LED_DEBUG_STATE_3: + SET(seqReg,LED_DEBUG_YELLOW_BIT); + SET(seqReg,LED_DEBUG_GREEN_BIT); + break; + + case LED_DEBUG_YELLOW_ON: + SET(seqReg,LED_DEBUG_YELLOW_BIT); + break; + + case LED_DEBUG_YELLOW_OFF: + CLR(seqReg,LED_DEBUG_YELLOW_BIT); + break; + + case LED_DEBUG_GREEN_ON: + SET(seqReg,LED_DEBUG_GREEN_BIT); + break; + + case LED_DEBUG_GREEN_OFF: + CLR(seqReg,LED_DEBUG_GREEN_BIT); + break; + + default: + panic("ledSetDebug: invalid command %d\n",command); + break; + } + sequoiaWrite(PMC_FOMPCR_REG, seqReg); +#ifdef SHARK + restore_interrupts(savedints); +#endif +} + + +#ifdef USEFULL_DEBUG +void sequoiaOneAccess(void) +{ +u_int16_t reg; +#ifdef SHARK + u_int savedints; + + savedints = disable_interrupts(I32_bit | F32_bit); +#endif + reg = bus_space_read_2(&isa_io_bs_tag,sequoia_ioh,SEQUOIA_DATA_OFFSET); +#ifdef SHARK + restore_interrupts(savedints); +#endif +} +#endif + +int testPin=0; +void scrToggleTestPin (void) +{ + u_int16_t seqReg; +#ifdef SHARK + u_int savedints; + + savedints = disable_interrupts(I32_bit | F32_bit); +#endif + + sequoiaRead(SEQUOIA_2GPIO,&seqReg); + + if (testPin) + { + testPin = 0; + CLR(seqReg,SCR_BUGA); + } + else + { + SET(seqReg,SCR_BUGA); + testPin = 1; + } + sequoiaWrite(SEQUOIA_2GPIO,seqReg); +#ifdef SHARK + restore_interrupts(savedints); +#endif +} + diff --git a/sys/arch/dnard/dnard/sequoia.h b/sys/arch/dnard/dnard/sequoia.h new file mode 100644 index 000000000000..4089f6fca2c6 --- /dev/null +++ b/sys/arch/dnard/dnard/sequoia.h @@ -0,0 +1,5130 @@ +/* $NetBSD: sequoia.h,v 1.1 2001/05/09 15:58:08 matt Exp $ */ + +/* + * Copyright 1997 + * Digital Equipment Corporation. All rights reserved. + * + * This software is furnished under license and may be used and + * copied only in accordance with the following terms and conditions. + * Subject to these conditions, you may download, copy, install, + * use, modify and distribute this software in source and/or binary + * form. No title or ownership is transferred hereby. + * + * 1) Any source code used, modified or distributed must reproduce + * and retain this copyright notice and list of conditions as + * they appear in the source file. + * + * 2) No right is granted to use any trade name, trademark, or logo of + * Digital Equipment Corporation. Neither the "Digital Equipment + * Corporation" name nor any trademark or logo of Digital Equipment + * Corporation may be used to endorse or promote products derived + * from this software without the prior written permission of + * Digital Equipment Corporation. + * + * 3) This software is provided "AS-IS" and any express or implied + * warranties, including but not limited to, any implied warranties + * of merchantability, fitness for a particular purpose, or + * non-infringement are disclaimed. In no event shall DIGITAL be + * liable for any damages whatsoever, and in particular, DIGITAL + * shall not be liable for special, indirect, consequential, or + * incidental damages or damages for lost profits, loss of + * revenue or loss of use, whether such damages arise in contract, + * negligence, tort, under statute, in equity, at law or otherwise, + * even if advised of the possibility of such damage. + */ + +/* +** +** MODULE DESCRIPTION: +** +** National Sequoia-1 and Sequoia-2 Definitions +** +** Initial Register Write Values are identified by _INIT +** +** CREATION DATE: +** +** 22-Jan-1997 +** +** AUTHOR: +** +** Madeleine D. Robert +** +** MODIFICATION HISTORY: +** +** 27-Jan-1997 Maddy Added additional initial values. +** +** 24-Jan-1997 Maddy Initial Entry. +*/ + + +#ifndef SEQUOIAH +#define SEQUOIAH + +/**************************************************** +** SEQUOIA ** +*****************************************************/ +#define SEQUOIA_BASE 0x24 +#define SEQUOIA_NPORTS 0x4 + +#define SEQUOIA_INDEX 0x24 +#define SEQUOIA_INDEX_OFFSET 0x0 + +#define SEQUOIA_DATA 0x26 +#define SEQUOIA_DATA_OFFSET 0x2 + + +/**************************************************** +** SEQUOIA-1 ** +*****************************************************/ + +/* +** Power Management Control Registers +** +*/ + +/* +** +** PMC Clock Control Register (CCR) - Index 0x000 +** +** Loc Size Name Function +** ----- ---- ---- --------------------------------- +** <0> 1 CNCLKSEL0 Conserve Clock Select 0 +** <1> 1 CNCLKSEL1 Conserve Clock Select 1 +** <2> 1 CNCLKSEL2 Conserve Clock Select 2 +** <3> 1 CNSRVEN Conserve Mode Enable +** <4> 1 SLCLKSEL0 Slow Clock Select 0 +** <5> 1 SLCLKSEL1 Slow Clock Select 1 +** <6> 1 SLCLKSEL2 Slow Clock Select 2 +** <7> 1 SLWCLKEN Slow Clock Enable +** <8> 1 SLPSLWEN Sleep Mode, Slow Clock Enable +** <9> 1 DZSLWEN Doze Mode, Slow Clock Enable +** <10> 1 SPNDSLWEN Suspend Mode, Slow Clock Enable +** <11> 1 LBSLWEN Low Battery Slow Enable +** <12> 1 DZONHALT Doze on HALT +** <14> 1 LBST Low Battery Status +** <15> 1 VLBST Very Low Battery Status +** +** <13> Reserved +*/ +#define PMC_CCR_REG 0x000 +#define PMC_CCR_INIT 0x000 +#define CCR_V_CNCLKSEL 0 +#define CCR_M_CNCLKSEL 0x7 << CCR_V_CNCLKSEL +#define CCR_V_CNCLKSEL0 0 +#define CCR_M_CNCLKSEL0 1 << CCR_V_CNCLKSEL0 +#define CCR_V_CNCLKSEL1 1 +#define CCR_M_CNCLKSEL1 1 << CCR_V_CNCLKSEL1 +#define CCR_V_CNCLKSEL2 2 +#define CCR_M_CNCLKSEL2 1 << CCR_V_CNCLKSEL2 +#define CCR_V_CNSRVEN 3 +#define CCR_M_CNSRVEN 1 << CCR_V_CNSRVEN +#define CCR_V_SLCLKSEL 4 +#define CCR_M_SLCLKSEL 0x7 << CCR_V_SLCLKSEL +#define CCR_V_SLCLKSEL0 4 +#define CCR_M_SLCLKSEL0 1 << CCR_V_SLCLKSEL0 +#define CCR_V_SLCLKSEL1 5 +#define CCR_M_SLCLKSEL1 1 << CCR_V_SLCLKSEL1 +#define CCR_V_SLCLKSEL2 6 +#define CCR_M_SLCLKSEL2 1 << CCR_V_SLCLKSEL2 +#define CCR_V_SLWCLKEN 7 +#define CCR_M_SLWCLKEN 1 << CCR_V_SLWCLKEN +#define CCR_V_SLPSLWEN 8 +#define CCR_M_SLPSLWEN 1 << CCR_V_SLPSLWEN +#define CCR_V_DZSLWEN 9 +#define CCR_M_DZSLWEN 1 << CCR_V_DZSLWEN +#define CCR_V_SPNDSLWEN 10 +#define CCR_M_SPNDSLWEN 1 << CCR_V_SPNDSLWEN +#define CCR_V_LBSLWEN 11 +#define CCR_M_LBSLWEN 1 << CCR_V_LBSLWEN +#define CCR_V_DZONHALT 12 +#define CCR_M_DZONHALT 1 << CCR_V_DZONHALT +#define CCR_V_LBST 14 +#define CCR_M_LBST 1 << CCR_V_LBST +#define CCR_V_VLBST 15 +#define CCR_M_VLBST 1 << CCR_V_VLBST + +/* +** Conserve Clock Selects +*/ +#define CNCLKSEL_DIV1 0x000 +#define CNCLKSEL_DIV2 CCR_M_CNCLKSEL0 +#define CNCLKSEL_DIV4 CCR_M_CNCLKSEL1 +#define CNCLKSEL_DIV8 (CCR_M_CNCLKSEL0 | CCR_M_CNCLKSEL1) +#define CNCLKSEL_DIV16 CCR_M_CNCLKSEL2 +#define CNCLKSEL_DIV32 (CCR_M_CNCLKSEL0 | CCR_M_CNCLKSEL2) +#define CNCLKSEL_DIV64 (CCR_M_CNCLKSEL1 | CCR_M_CNCLKSEL2) + +/* +** Slow Clock Selects +*/ +#define SLCLKSEL_DIV1 0x000 +#define SLCLKSEL_DIV2 CCR_M_SLCLKSEL0 +#define SLCLKSEL_DIV4 CCR_M_SLCLKSEL1 +#define SLCLKSEL_DIV8 (CCR_M_SLCLKSEL0 | CCR_M_SLCLKSEL1) +#define SLCLKSEL_DIV16 CCR_M_SLCLKSEL2 +#define SLCLKSEL_DIV32 (CCR_M_SLCLKSEL0 | CCR_M_SLCLKSEL2) +#define SLCLKSEL_DIV64 (CCR_M_SLCLKSEL1 | CCR_M_SLCLKSEL2) +#define SLCLKSEL_STOPPED (CCR_M_SLCLKSEL0 | CCR_M_SLCLKSEL1 | CCR_M_SLCLKSEL2) + +/* +** +** Power Management Status Register (PMSR) - Index 0x001 +** +** Loc Size Name Function +** ----- ---- ---- --------------------------------- +** <0> 1 WAKESRC0 Wake-up Source 0 +** <1> 1 WAKESRC1 Wake-up Source 1 +** <2> 1 WAKESRC2 Wake-up Source 2 +** <3> 1 ACPWR AC Power +** <4> 1 PMISRC0 Power Management Interrupt 0 +** <5> 1 PMISRC1 Power Management Interrupt 1 +** <6> 1 PMISRC2 Power Management Interrupt 2 +** <7> 1 PMISRC3 Power Management Interrupt 3 +** <8> 1 PMISRC4 Power Management Interrupt 4 +** <9> 1 RESUME Resume +** <10> 1 WAKE0STATUS Wake 0 Status +** <11> 1 WAKE1STATUS Wake 1 Status +** <13> 1 PMMD0 Power Management Mode 0 +** <14> 1 PMMD1 Power Management Mode 1 +** <15> 1 PMMD2 Power Management Mode 2 +** +** <12> Reserved +*/ +#define PMC_PMSR_REG 0x001 +#define PMC_PMSR_INIT ( PMSR_M_WAKESRC | PMSR_M_PMISRC | PMMD_ON ) +#define PMSR_V_WAKESRC 0 +#define PMSR_M_WAKESRC 0x7 << PMSR_V_WAKESRC +#define PMSR_V_WAKESRC0 0 +#define PMSR_M_WAKESRC0 1 << PMSR_V_WAKESRC0 +#define PMSR_V_WAKESRC1 1 +#define PMSR_M_WAKESRC1 1 << PMSR_V_WAKESRC1 +#define PMSR_V_WAKESRC2 2 +#define PMSR_M_WAKESRC2 1 << PMSR_V_WAKESRC2 +#define PMSR_V_ACPWR 3 +#define PMSR_M_ACPWR 1 << PMSR_V_ACPWR +#define PMSR_V_PMISRC 4 +#define PMSR_M_PMISRC 0x1F << PMSR_V_PMISRC +#define PMSR_V_PMISRC0 4 +#define PMSR_M_PMISRC0 1 << PMSR_V_PMISRC0 +#define PMSR_V_PMISRC1 5 +#define PMSR_M_PMISRC1 1 << PMSR_V_PMISRC1 +#define PMSR_V_PMISRC2 6 +#define PMSR_M_PMISRC2 1 << PMSR_V_PMISRC2 +#define PMSR_V_PMISRC3 7 +#define PMSR_M_PMISRC3 1 << PMSR_V_PMISRC3 +#define PMSR_V_PMISRC4 8 +#define PMSR_M_PMISRC4 1 << PMSR_V_PMISRC4 +#define PMSR_V_RESUME 9 +#define PMSR_M_RESUME 1 << PMSR_V_RESUME +#define PMSR_V_WAKE0STATUS 10 +#define PMSR_M_WAKE0STATUS 1 << PMSR_V_WAKE0STATUS +#define PMSR_V_WAKE1STATUS 11 +#define PMSR_M_WAKE1STATUS 1 << PMSR_V_WAKE1STATUS +#define PMSR_V_PMMD 13 +#define PMSR_M_PMMD 0x7 << PMSR_V_PMMD +#define PMSR_V_PMMD0 13 +#define PMSR_M_PMMD0 1 << PMSR_V_PMMD0 +#define PMSR_V_PMMD1 14 +#define PMSR_M_PMMD1 1 << PMSR_V_PMMD1 +#define PMSR_V_PMMD2 15 +#define PMSR_M_PMMD2 1 << PMSR_V_PMMD2 + +/* +** Wake-up Source +*/ +#define WAKESRC_NONE 0x000 +#define WAKESRC_RING PMSR_M_WAKESRC0 +#define WAKESRC_RTCI PMSR_M_WAKESRC1 +#define WAKESRC_SWTCH (PMSR_M_WAKESRC0 | PMSR_M_WAKESRC1) +#define WAKESRC_GPTC PMSR_M_WAKESRC2 +#define WAKESRC_WAKE0 (PMSR_M_WAKESRC0 | PMSR_M_WAKESRC2) +#define WAKESRC_WAKE1 (PMSR_M_WAKESRC1 | PMSR_M_WAKESRC2) +#define WAKESRC_WAKECLR (PMSR_M_WAKESRC0 | PMSR_M_WAKESRC1 | PMSR_M_WAKESRC2) + +/* +** Power Management Interrupt Source +*/ +#define PMISRC_NONE 0x000 +#define PMISRC_IRQI PMSR_M_PMISRC0 +#define PMISRC_LBC PMSR_M_PMISRC1 +#define PMISRC_SUSTO (PMSR_M_PMISRC0 | PMSR_M_PMISRC1) +#define PMISRC_SLPTO PMSR_M_PMISRC2 +#define PMISRC_DZTO (PMSR_M_PMISRC0 | PMSR_M_PMISRC2) +#define PMISRC_GENTO (PMSR_M_PMISRC1 | PMSR_M_PMISRC2) +#define PMISRC_GENACT (PMSR_M_PMISRC0 | PMSR_M_PMISRC1 | PMSR_M_PMISRC2) +#define PMISRC_PRIACT PMSR_M_PMISRC3 +#define PMISRC_SCDACT (PMSR_M_PMISRC0 | PMSR_M_PMISRC3) +#define PMISRC_SCDACTTO (PMSR_M_PMISRC1 | PMSR_M_PMISRC3) +#define PMISRC_SWTCH (PMSR_M_PMISRC0 | PMSR_M_PMISRC1 | PMSR_M_PMISRC3) +#define PMISRC_ACPWR (PMSR_M_PMISRC2 | PMSR_M_PMISRC3) +#define PMISRC_PRGTTO (PMSR_M_PMISRC0 | PMSR_M_PMISRC2 | PMSR_M_PMISRC3) +#define PMISRC_GPTCOMP (PMSR_M_PMISRC1 | PMSR_M_PMISRC2 | PMSR_M_PMISRC3) +#define PMISRC_RTC (PMSR_M_PMISRC0 | PMSR_M_PMISRC4) +#define PMISRC_RESCHPMI (PMSR_M_PMISRC1 | PMSR_M_PMISRC4) +#define PMISRC_SWSMI (PMSR_M_PMISRC0 | PMSR_M_PMISRC1 | PMSR_M_PMISRC4) + +/* +** Power Management Mode +*/ +#define PMMD_STDBY 0x000 +#define PMMD_ON PMSR_M_PMMD0 +#define PMMD_CONSERVE PMSR_M_PMMD1 +#define PMMD_DOZE (PMSR_M_PMMD0 | PMSR_M_PMMD1) +#define PMMD_SLEEP PMSR_M_PMMD2 +#define PMMD_SUSPEND (PMSR_M_PMMD0 | PMSR_M_PMMD2) + + +/* +** +** Activity Source Register (ASR) - Index 0x002 +** +** Loc Size Name Function +** ----- ---- ---- --------------------------------- +** <0> 1 VIDACTV Video Active +** <1> 1 HDACTV Hard Disk Active +** <2> 1 FLPACTV Floppy Disk Active +** <3> 1 KBDACTV Keyboard Active +** <4> 1 SIOACTV Serial I/O Active +** <5> 1 PIOACTV Parallel I/O Active +** <6> 1 PROG0ACTV PRM 0 Active +** <7> 1 PROG1ACTV PRM 1 Active +** <8> 1 PROG2ACTV PRM 2 Active +** <9> 1 PROG3ACTV PRM 3 Active +** <12> 1 EXT0ACTV Primary Activity Mask EXTACT0 +** <13> 1 EXT1ACTV Primary Activity Mask EXTACT1 +** <14> 1 EXT2ACTV Primary Activity Mask EXTACT2 +** <15> 1 EXT3ACTV Primary Activity Mask EXTACT3 +** +** <10:11> Reserved +*/ +#define PMC_ASR_REG 0x002 +#define PMC_ASR_INIT 0x0000 +#define ASR_V_VIDACTV 0 +#define ASR_M_VIDACTV 1 << ASR_V_VIDACTV +#define ASR_V_HDACTV 1 +#define ASR_M_HDACTV 1 << ASR_V_HDACTV +#define ASR_V_FLPACTV 2 +#define ASR_M_FLPACTV 1 << ASR_V_FLPACTV +#define ASR_V_KBDACTV 3 +#define ASR_M_KBDACTV 1 << ASR_V_KBDACTV +#define ASR_V_SIOACTV 4 +#define ASR_M_SIOACTV 1 << ASR_V_SIOACTV +#define ASR_V_PIOACTV 5 +#define ASR_M_PIOACTV 1 << ASR_V_PIOACTV +#define ASR_V_PROG0ACTV 6 +#define ASR_M_PROG0ACTV 1 << ASR_V_PROG0ACTV +#define ASR_V_PROG1ACTV 7 +#define ASR_M_PROG1ACTV 1 << ASR_V_PROG1ACTV +#define ASR_V_PROG2ACTV 8 +#define ASR_M_PROG2ACTV 1 << ASR_V_PROG2ACTV +#define ASR_V_PROG3ACTV 9 +#define ASR_M_PROG3ACTV 1 << ASR_V_PROG3ACTV +#define ASR_V_EXT0ACTV 12 +#define ASR_M_EXT0ACTV 1 << ASR_V_EXT0ACTV +#define ASR_V_EXT1ACTV 13 +#define ASR_M_EXT1ACTV 1 << ASR_V_EXT1ACTV +#define ASR_V_EXT2ACTV 14 +#define ASR_M_EXT2ACTV 1 << ASR_V_EXT2ACTV +#define ASR_V_EXT3ACTV 15 +#define ASR_M_EXT3ACTV 1 << ASR_V_EXT3ACTV + +/* +** +** Primary Activity Mask Register (PAMR) - Index 0x003 +** +** Loc Size Name Function +** ----- ---- ---- --------------------------------- +** <0> 1 PAMSKVID PAM Video Accesses +** <1> 1 PAMSKHD PAM Hard Disk Accesses +** <2> 1 PAMSKFLP PAM Floppy Accesses +** <3> 1 PAMSKKDB PAM Keyboard Accesses +** <4> 1 PAMSKSIO PAM Serial I/O Accesses +** <5> 1 PAMSKPIO PAM Parallel I/O Accesses +** <6> 1 PAMSKPROG0 PAM Programmable Range 0 +** <7> 1 PAMSKPROG1 PAM Programmable Range 1 +** <8> 1 PAMSKPROG2 PAM Programmable Range 2 +** <9> 1 PAMSKPROG3 PAM Programmable Range 3 +** <12> 1 PAMSKEACT0 PAM EXTACT0 +** <13> 1 PAMSKEACT1 PAM EXTACT1 +** <14> 1 PAMSKEACT2 PAM EXTACT2 +** <15> 1 PAMSKEACT3 PAM EXTACT3 +** +** <10:11> Reserved +*/ +#define PMC_PAMR_REG 0x003 +#define PMC_PAMR_INIT 0x0000 +#define PAMR_V_PAMSKVID 0 +#define PAMR_M_PAMSKVID 1 << PAMR_V_PAMSKVID +#define PAMR_V_PAMSKHD 1 +#define PAMR_M_PAMSKHD 1 << PAMR_V_PAMSKHD +#define PAMR_V_PAMSKFLP 2 +#define PAMR_M_PAMSKFLP 1 << PAMR_V_PAMSKFLP +#define PAMR_V_PAMSKKDB 3 +#define PAMR_M_PAMSKKDB 1 << PAMR_V_PAMSKKDB +#define PAMR_V_PAMSKSIO 4 +#define PAMR_M_PAMSKSIO 1 << PAMR_V_PAMSKSIO +#define PAMR_V_PAMSKPIO 5 +#define PAMR_M_PAMSKPIO 1 << PAMR_V_PAMSKPIO +#define PAMR_V_PAMSKPROG0 6 +#define PAMR_M_PAMSKPROG0 1 << PAMR_V_PAMSKPROG0 +#define PAMR_V_PAMSKPROG1 7 +#define PAMR_M_PAMSKPROG1 1 << PAMR_V_PAMSKPROG1 +#define PAMR_V_PAMSKPROG2 8 +#define PAMR_M_PAMSKPROG2 1 << PAMR_V_PAMSKPROG2 +#define PAMR_V_PAMSKPROG3 9 +#define PAMR_M_PAMSKPROG3 1 << PAMR_V_PAMSKPROG3 +#define PAMR_V_PAMSKEACT0 12 +#define PAMR_M_PAMSKEACT0 1 << PAMR_V_PAMSKEACT0 +#define PAMR_V_PAMSKEACT1 13 +#define PAMR_M_PAMSKEACT1 1 << PAMR_V_PAMSKEACT1 +#define PAMR_V_PAMSKEACT2 14 +#define PAMR_M_PAMSKEACT2 1 << PAMR_V_PAMSKEACT2 +#define PAMR_V_PAMSKEACT3 15 +#define PAMR_M_PAMSKEACT3 1 << PAMR_V_PAMSKEACT3 + +/* +** +** PMI Mask Register (PMIMR) - Index 0x004 +** +** Loc Size Name Function +** ----- ---- ---- --------------------------------- +** <0> 1 IMSKVID PMI Mask Video Accesses +** <1> 1 IMSKHD PMI Mask Hard Disk Accesses +** <2> 1 IMSKFLP PMI Mask Floppy Accesses +** <3> 1 IMSKKDB PMI Mask Keyboard Accesses +** <4> 1 IMSKSIO PMI Mask Serial I/O Accesses +** <5> 1 IMSKPIO PMI Mask Parallel I/O Accesses +** <6> 1 IMSKPROG0 PMI Mask Programmable Range 0 +** <7> 1 IMSKPROG1 PMI Mask Programmable Range 1 +** <8> 1 IMSKPROG2 PMI Mask Programmable Range 2 +** <9> 1 IMSKPROG3 PMI Mask Programmable Range 3 +** <12> 1 IMSKEACT0 PMI Mask EXTACT0 +** <13> 1 IMSKEACT1 PMI Mask EXTACT1 +** <14> 1 IMSKEACT2 PMI Mask EXTACT2 +** <15> 1 IMSKEACT3 PMI Mask EXTACT3 +** +** <10:11> Reserved +*/ +#define PMC_PMIMR_REG 0x004 +#define PMC_PMIMR_INIT ( PMIMR_M_IMSKVID | PMIMR_M_IMSKHD | \ + PMIMR_M_IMSKFLP | PMIMR_M_IMSKKDB | \ + PMIMR_M_IMSKSIO | PMIMR_M_IMSKPIO | \ + PMIMR_M_IMSKPROG0 | PMIMR_M_IMSKPROG1 | \ + PMIMR_M_IMSKPROG2 | PMIMR_M_IMSKPROG3 | \ + PMIMR_M_IMSKEACT0 | PMIMR_M_IMSKEACT1 | \ + PMIMR_M_IMSKEACT2 | PMIMR_M_IMSKEACT3 ) +#define PMIMR_V_IMSKVID 0 +#define PMIMR_M_IMSKVID 1 << PMIMR_V_IMSKVID +#define PMIMR_V_IMSKHD 1 +#define PMIMR_M_IMSKHD 1 << PMIMR_V_IMSKHD +#define PMIMR_V_IMSKFLP 2 +#define PMIMR_M_IMSKFLP 1 << PMIMR_V_IMSKFLP +#define PMIMR_V_IMSKKDB 3 +#define PMIMR_M_IMSKKDB 1 << PMIMR_V_IMSKKDB +#define PMIMR_V_IMSKSIO 4 +#define PMIMR_M_IMSKSIO 1 << PMIMR_V_IMSKSIO +#define PMIMR_V_IMSKPIO 5 +#define PMIMR_M_IMSKPIO 1 << PMIMR_V_IMSKPIO +#define PMIMR_V_IMSKPROG0 6 +#define PMIMR_M_IMSKPROG0 1 << PMIMR_V_IMSKPROG0 +#define PMIMR_V_IMSKPROG1 7 +#define PMIMR_M_IMSKPROG1 1 << PMIMR_V_IMSKPROG1 +#define PMIMR_V_IMSKPROG2 8 +#define PMIMR_M_IMSKPROG2 1 << PMIMR_V_IMSKPROG2 +#define PMIMR_V_IMSKPROG3 9 +#define PMIMR_M_IMSKPROG3 1 << PMIMR_V_IMSKPROG3 +#define PMIMR_V_IMSKEACT0 12 +#define PMIMR_M_IMSKEACT0 1 << PMIMR_V_IMSKEACT0 +#define PMIMR_V_IMSKEACT1 13 +#define PMIMR_M_IMSKEACT1 1 << PMIMR_V_IMSKEACT1 +#define PMIMR_V_IMSKEACT2 14 +#define PMIMR_M_IMSKEACT2 1 << PMIMR_V_IMSKEACT2 +#define PMIMR_V_IMSKEACT3 15 +#define PMIMR_M_IMSKEACT3 1 << PMIMR_V_IMSKEACT3 + +/* +** +** Heat Regulator Control Register (HRCR) - Index 0x005 +** +** Loc Size Name Function +** ----- ---- ---- --------------------------------- +** <0> 1 HTRGDLY0 Heat Regulator Delay 0 +** <1> 1 HTRGDLY1 Heat Regulator Delay 1 +** <2> 1 HTRGDLY2 Heat Regulator Delay 2 +** <3> 1 HTRGRAT0 Heat Regulator Ratio 0 +** <4> 1 HTRGRAT1 Heat Regulator Ratio 1 +** <5> 1 HTRGRAT2 Heat Regulator Ratio 2 +** <6> 1 HTRGEN Heat Regulator Enable +** <7> 1 HTRGLOCK Heat Regulator Configuration Lock +** <14> 1 FRCSLWEN Force SLOW Enable +** <15> 1 FRCSLWLOCK Force Slow Lock +** +** <8:13> Reserved +*/ +#define PMC_HRCR_REG 0x005 +#define PMC_HRCR_INIT 0x0000 +#define HRCR_V_HTRGDLY 0 +#define HRCR_M_HTRGDLY 0x7 << HRCR_V_HTRGDLY +#define HRCR_V_HTRGDLY0 0 +#define HRCR_M_HTRGDLY0 1 << HRCR_V_HTRGDLY0 +#define HRCR_V_HTRGDLY1 1 +#define HRCR_M_HTRGDLY1 1 << HRCR_V_HTRGDLY1 +#define HRCR_V_HTRGDLY2 2 +#define HRCR_M_HTRGDLY2 1 << HRCR_V_HTRGDLY2 +#define HRCR_V_HTRGRAT 3 +#define HRCR_M_HTRGRAT 0x7 << HRCR_V_HTRGRAT +#define HRCR_V_HTRGRAT0 3 +#define HRCR_M_HTRGRAT0 1 << HRCR_V_HTRGRAT0 +#define HRCR_V_HTRGRAT1 4 +#define HRCR_M_HTRGRAT1 1 << HRCR_V_HTRGRAT1 +#define HRCR_V_HTRGRAT2 5 +#define HRCR_M_HTRGRAT2 1 << HRCR_V_HTRGRAT2 +#define HRCR_V_HTRGEN 6 +#define HRCR_M_HTRGEN 1 << HRCR_V_HTRGEN +#define HRCR_V_HTRGLOCK 7 +#define HRCR_M_HTRGLOCK 1 << HRCR_V_HTRGLOCK +#define HRCR_V_FRCSLWEN 14 +#define HRCR_M_FRCSLWEN 1 << HRCR_V_FRCSLWEN +#define HRCR_V_FRCSLWLOCK 15 +#define HRCR_M_FRCSLWLOCK 1 << HRCR_V_FRCSLWLOCK + +/* +** Heater Regulator Delay +*/ +#define HTRGDLY_16SEC 0x000 +#define HTRGDLY_32SEC HRCR_M_HTRGDLY0 +#define HTRGDLY_60SEC HRCR_M_HTRGDLY1 +#define HTRGDLY_120SEC HRCR_M_HTRGDLY2 +#define HTRGDLY_240SEC (HRCR_M_HTRGDLY1 | HRCR_M_HTRGDLY2) +#define HTRGDLY_480SEC (HRCR_M_HTRGDLY0 | HRCR_M_HTRGDLY1 | HRCR_M_HTRGDLY2) + +/* +** Heater Regulator Ratio (Percent) +*/ +#define HTRGRAT_50 0x000 +#define HTRGRAT_66 HRCR_M_HTRGRAT0 +#define HTRGRAT_80 HRCR_M_HTRGRAT1 +#define HTRGRAT_90 (HRCR_M_HTRGRAT0 | HRCR_M_HTRGRAT1) + +/* +** +** PMI Mask and Control Register (PMIMCR) - Index 0x006 +** +** Loc Size Name Function +** ----- ---- ---- --------------------------------- +** <0> 1 IMSKSQ2PMI Mask SEQUOIA-2 Source from PMI +** <1> 1 IMSKLB Mask Low Battery from PMI +** <2> 1 IMSKSPNDTO Mask Suspend Time-out from PMI +** <3> 1 IMSKSLPTO Mask Sleep Time-out from PMI +** <4> 1 IMSKDZTO Mask Doze Time-out from PMI +** <5> 1 IMSKGENTO Mask Generic Time-out from PMI +** <6> 1 IMSKACTV Mask Generic Activity from PMI +** <7> 1 IMSKPACTV Mask Primary Activity from PMI +** <8> 1 IMSKSACTV Mask Secondary Activity from PMI +** <10> 1 IMSKSWSTBY Mask SWTCH from PMI +** <11> 1 IMSKACPWR Mask ACPWR from PMI +** <12> 1 IMSKPROGTO Mask Programmable Time-out from PMI +** <13> 1 IMSKGPTMR Mask GP Timer from PMI +** +** <9><14:15> Reserved +*/ +#define PMC_PMIMCR_REG 0x006 +#define PMC_PMIMCR_INIT ( PMIMCR_M_IMSKSQ2PMI | PMIMCR_M_IMSKLB | \ + PMIMCR_M_IMSKSPNDTO | PMIMCR_M_IMSKSLPTO | \ + PMIMCR_M_IMSKDZTO | PMIMCR_M_IMSKGENTO | \ + PMIMCR_M_IMSKACTV | PMIMCR_M_IMSKPACTV | \ + PMIMCR_M_IMSKSACTV | PMIMCR_M_IMSKSWSTBY | \ + PMIMCR_M_IMSKACPWR | PMIMCR_M_IMSKPROGTO | \ + PMIMCR_M_IMSKGPTMR ) +#define PMIMCR_V_IMSKSQ2PMI 0 +#define PMIMCR_M_IMSKSQ2PMI 1 << PMIMCR_V_IMSKSQ2PMI +#define PMIMCR_V_IMSKLB 1 +#define PMIMCR_M_IMSKLB 1 << PMIMCR_V_IMSKLB +#define PMIMCR_V_IMSKSPNDTO 2 +#define PMIMCR_M_IMSKSPNDTO 1 << PMIMCR_V_IMSKSPNDTO +#define PMIMCR_V_IMSKSLPTO 3 +#define PMIMCR_M_IMSKSLPTO 1 << PMIMCR_V_IMSKSLPTO +#define PMIMCR_V_IMSKDZTO 4 +#define PMIMCR_M_IMSKDZTO 1 << PMIMCR_V_IMSKDZTO +#define PMIMCR_V_IMSKGENTO 5 +#define PMIMCR_M_IMSKGENTO 1 << PMIMCR_V_IMSKGENTO +#define PMIMCR_V_IMSKACTV 6 +#define PMIMCR_M_IMSKACTV 1 << PMIMCR_V_IMSKACTV +#define PMIMCR_V_IMSKPACTV 7 +#define PMIMCR_M_IMSKPACTV 1 << PMIMCR_V_IMSKPACTV +#define PMIMCR_V_IMSKSACTV 8 +#define PMIMCR_M_IMSKSACTV 1 << PMIMCR_V_IMSKSACTV +#define PMIMCR_V_IMSKSWSTBY 10 +#define PMIMCR_M_IMSKSWSTBY 1 << PMIMCR_V_IMSKSWSTBY +#define PMIMCR_V_IMSKACPWR 11 +#define PMIMCR_M_IMSKACPWR 1 << PMIMCR_V_IMSKACPWR +#define PMIMCR_V_IMSKPROGTO 12 +#define PMIMCR_M_IMSKPROGTO 1 << PMIMCR_V_IMSKPROGTO +#define PMIMCR_V_IMSKGPTMR 13 +#define PMIMCR_M_IMSKGPTMR 1 << PMIMCR_V_IMSKGPTMR + +/* +** +** General Purpose Control Register (GPCR) - Index 0x007 +** +** Loc Size Name Function +** ----- ---- ---- --------------------------------- +** <0> 1 ACDISCNSRV ACPWR Disable Conserve Mode +** <1> 1 ACON ACPWR On +** <2> 1 REFRPRD0 Refresh Period 0 +** <3> 1 REFRPRD1 Refresh Period 1 +** <4> 1 REFRPRD2 Refresh Period 2 +** <5> 1 SLFREFEN Self Refresh Enable +** <6> 1 RINGS0 Modem RING Select 0 +** <7> 1 RINGS1 Modem RING Select 1 +** <8> 1 GPIODATA0 General Purpose I/O Data 0 +** <9> 1 GPIODATA1 General Purpose I/O Data 1 +** <10> 1 GPIODATA2 General Purpose I/O Data 2 +** <11> 1 GPIODATA3 General Purpose I/O Data 3 +** <12> 1 GPIODIR0 General Purpose I/O Direction 0 +** <13> 1 GPIODIR1 General Purpose I/O Direction 1 +** <14> 1 GPIODIR2 General Purpose I/O Direction 2 +** <15> 1 GPIODIR3 General Purpose I/O Direction 3 +** +*/ +#define PMC_GPCR_REG 0x007 +#define PMC_GPCR_INIT ( REFRPRD_STOPPED | GPCR_M_GPIODIR0 | \ + GPCR_M_GPIODIR1 ) +#define GPCR_V_ACDISCNSRV 0 +#define GPCR_M_ACDISCNSRV 1 << GPCR_V_ACDISCNSRV +#define GPCR_V_ACON 1 +#define GPCR_M_ACON 1 << GPCR_V_ACON +#define GPCR_V_REFRPRD 2 +#define GPCR_M_REFRPRD 0x7 << GPCR_V_REFRPRD +#define GPCR_V_REFRPRD0 2 +#define GPCR_M_REFRPRD0 1 << GPCR_V_REFRPRD0 +#define GPCR_V_REFRPRD1 3 +#define GPCR_M_REFRPRD1 1 << GPCR_V_REFRPRD1 +#define GPCR_V_REFRPRD2 4 +#define GPCR_M_REFRPRD2 1 << GPCR_V_REFRPRD2 +#define GPCR_V_SLFREFEN 5 +#define GPCR_M_SLFREFEN 1 << GPCR_V_SLFREFEN +#define GPCR_V_RINGS 6 +#define GPCR_M_RINGS 0x3 << GPCR_V_RINGS +#define GPCR_V_GPIODATA 8 +#define GPCR_M_GPIODATA 0xF << GPCR_V_GPIODATA +#define GPCR_V_GPIODATA0 8 +#define GPCR_M_GPIODATA0 1 << GPCR_V_GPIODATA0 +#define GPCR_V_GPIODATA1 9 +#define GPCR_M_GPIODATA1 1 << GPCR_V_GPIODATA1 +#define GPCR_V_GPIODATA2 10 +#define GPCR_M_GPIODATA2 1 << GPCR_V_GPIODATA2 +#define GPCR_V_GPIODATA3 11 +#define GPCR_M_GPIODATA3 1 << GPCR_V_GPIODATA3 +#define GPCR_V_GPIODIR 12 +#define GPCR_M_GPIODIR 0xF << GPCR_V_GPIODIR +#define GPCR_V_GPIODIR0 12 +#define GPCR_M_GPIODIR0 1 << GPCR_V_GPIODIR0 +#define GPCR_V_GPIODIR1 13 +#define GPCR_M_GPIODIR1 1 << GPCR_V_GPIODIR1 +#define GPCR_V_GPIODIR2 14 +#define GPCR_M_GPIODIR2 1 << GPCR_V_GPIODIR2 +#define GPCR_V_GPIODIR3 15 +#define GPCR_M_GPIODIR3 1 << GPCR_V_GPIODIR3 + +/* +** Refresh Period +*/ +#define REFRPRD_15US 0x000 +#define REFRPRD_30US GPCR_M_REFRPRD0 +#define REFRPRD_120US GPCR_M_REFRPRD1 +#define REFRPRD_STOPPED GPCR_M_REFRPRD2 +#define REFRPRD_60US (GPCR_M_REFRPRD1 | GPCR_M_REFRPRD2) + +/* +** +** Stop Clock Control Register (SCCR) - Index 0x008 +** +** Loc Size Name Function +** ----- ---- ---- --------------------------------- +** <0> 1 STPGLBEN Stop Clock Global Enable +** <1> 1 MORESTOP More Stop Enable +** <2> 1 STPRELDLY0 STPCLK Release Delay 0 +** <3> 1 STPRELDLY1 STPCLK Release Delay 1 +** <4> 1 GRNTDLY0 STPCLK Latency Delay Select 0 +** <5> 1 GRNTDLY1 STPCLK Latency Delay Select 1 +** <6> 1 WMSKINTR Wake Mask INTR +** <7> 1 WAIT4GRNT Wait for Stop Grant +** <9> 1 IOTRAPDIS I/O Trap Disable +** <10> 1 SVNCLKPLS SMI PULSE Width Select +** <11> 1 PCSTGSEL0 PC Staggering Select 0 +** <12> 1 PCSTGSEL1 PC Staggering Select 1 +** <13> 1 PCSTGDIS PC Stagger Disable +** <14> 1 PCSLWEN PC Slow Enable +** +** <8><15> Reserved +*/ +#define PMC_SCCR_REG 0x008 +#define PMC_SCCR_INIT SCCR_M_WMSKINTR +#define SCCR_V_STPGLBEN 0 +#define SCCR_M_STPGLBEN 1 << SCCR_V_STPGLBEN +#define SCCR_V_MORESTOP 1 +#define SCCR_M_MORESTOP 1 << SCCR_V_MORESTOP +#define SCCR_V_STPRELDLY 2 +#define SCCR_M_STPRELDLY 0x3 << SCCR_V_STPRELDLY +#define SCCR_V_STPRELDLY0 2 +#define SCCR_M_STPRELDLY0 1 << SCCR_V_STPRELDLY0 +#define SCCR_V_STPRELDLY1 3 +#define SCCR_M_STPRELDLY1 1 << SCCR_V_STPRELDLY1 +#define SCCR_V_GRNTDLY 4 +#define SCCR_M_GRNTDLY 0x3 << SCCR_V_GRNTDLY +#define SCCR_V_GRNTDLY0 4 +#define SCCR_M_GRNTDLY0 1 << SCCR_V_GRNTDLY0 +#define SCCR_V_GRNTDLY1 5 +#define SCCR_M_GRNTDLY1 1 << SCCR_V_GRNTDLY1 +#define SCCR_V_WMSKINTR 6 +#define SCCR_M_WMSKINTR 1 << SCCR_V_WMSKINTR +#define SCCR_V_WAIT4GRNT 7 +#define SCCR_M_WAIT4GRNT 1 << SCCR_V_WAIT4GRNT +#define SCCR_V_IOTRAPDIS 9 +#define SCCR_M_IOTRAPDIS 1 << SCCR_V_IOTRAPDIS +#define SCCR_V_SVNCLKPLS 10 +#define SCCR_M_SVNCLKPLS 1 << SCCR_V_SVNCLKPLS +#define SCCR_V_PCSTGSEL 11 +#define SCCR_M_PCSTGSEL 0x3 << SCCR_V_PCSTGSEL +#define SCCR_V_PCSTGSEL0 11 +#define SCCR_M_PCSTGSEL0 1 << SCCR_V_PCSTGSEL0 +#define SCCR_V_PCSTGSEL1 12 +#define SCCR_M_PCSTGSEL1 1 << SCCR_V_PCSTGSEL1 +#define SCCR_V_PCSTGDIS 13 +#define SCCR_M_PCSTGDIS 1 << SCCR_V_PCSTGDIS +#define SCCR_V_PCSLWEN 14 +#define SCCR_M_PCSLWEN 1 << SCCR_V_PCSLWEN + +/* +** STPCLK Release Delay +*/ +#define STPRELDLY_0S 0x000 +#define STPRELDLY_1US SCCR_M_STPRELDLY0 +#define STPRELDLY_45US SCCR_M_STPRELDLY1 +#define STPRELDLY_1MS (SCCR_M_STPRELDLY0 | SCCR_M_STPRELDLY1) + +/* +** STPCLK Release Delay Select +*/ +#define GRNTDLY_GRANTBUS 0x000 +#define GRNTDLY_30US SCCR_M_GRNTDLY0 +#define GRNTDLY_125US SCCR_M_GRNTDLY1 +#define GRNTDLY_1MS (SCCR_M_GRNTDLY0 | SCCR_M_GRNTDLY1) + +/* +** PC Staggering Select +*/ +#define PCSTGSEL_240US 0x000 +#define PCSTGSEL_4US SCCR_M_PCSTGSEL0 +#define PCSTGSEL_16US SCCR_M_PCSTGSEL1 +#define PCSTGSEL_64MS (SCCR_M_PCSTGSEL0 | SCCR_M_PCSTGSEL1) + +/* +** +** Fully-On Mode Power Control Register (FOMPCR) - Index 0x009 +** +** Loc Size Name Function +** ----- ---- ---- --------------------------------- +** <0> 1 PCON0 Power Control Fully-On Mode 0 +** <1> 1 PCON1 Power Control Fully-On Mode 1 +** <2> 1 PCON2 Power Control Fully-On Mode 2 +** <3> 1 PCON3 Power Control Fully-On Mode 3 +** <4> 1 PCON4 Power Control Fully-On Mode 4 +** <5> 1 PCON5 Power Control Fully-On Mode 5 +** <6> 1 PCON6 Power Control Fully-On Mode 6 +** <7> 1 PCON7 Power Control Fully-On Mode 7 +** <8> 1 PCON8 Power Control Fully-On Mode 8 +** <9> 1 PCON9 Power Control Fully-On Mode 9 +** <10> 1 GLBLPCEN Global Power Control Enable +** +** <11:15> Reserved +*/ +#define PMC_FOMPCR_REG 0x009 +#define PMC_FOMPCR_INIT ( FOMPCR_M_PCON0 | FOMPCR_M_PCON1 ) +#define FOMPCR_V_PCON 0 +#define FOMPCR_M_PCON 0x3FF << FOMPCR_V_PCON +#define FOMPCR_V_PCON0 0 +#define FOMPCR_M_PCON0 1 << FOMPCR_V_PCON0 +#define FOMPCR_V_PCON1 1 +#define FOMPCR_M_PCON1 1 << FOMPCR_V_PCON1 +#define FOMPCR_V_PCON2 2 +#define FOMPCR_M_PCON2 1 << FOMPCR_V_PCON2 +#define FOMPCR_V_PCON3 3 +#define FOMPCR_M_PCON3 1 << FOMPCR_V_PCON3 +#define FOMPCR_V_PCON4 4 +#define FOMPCR_M_PCON4 1 << FOMPCR_V_PCON4 +#define FOMPCR_V_PCON5 5 +#define FOMPCR_M_PCON5 1 << FOMPCR_V_PCON5 +#define FOMPCR_V_PCON6 6 +#define FOMPCR_M_PCON6 1 << FOMPCR_V_PCON6 +#define FOMPCR_V_PCON7 7 +#define FOMPCR_M_PCON7 1 << FOMPCR_V_PCON7 +#define FOMPCR_V_PCON8 8 +#define FOMPCR_M_PCON8 1 << FOMPCR_V_PCON8 +#define FOMPCR_V_PCON9 9 +#define FOMPCR_M_PCON9 1 << FOMPCR_V_PCON9 +#define FOMPCR_V_GLBLPCEN 10 +#define FOMPCR_M_GLBLPCEN 1 << FOMPCR_V_GLBLPCEN + +/* +** +** Doze Mode Power Control Register (DZMPCR) - Index 0x00A +** +** Loc Size Name Function +** ----- ---- ---- --------------------------------- +** <0> 1 PCDZ0 Power Control Doze Mode 0 +** <1> 1 PCDZ1 Power Control Doze Mode 1 +** <2> 1 PCDZ2 Power Control Doze Mode 2 +** <3> 1 PCDZ3 Power Control Doze Mode 3 +** <4> 1 PCDZ4 Power Control Doze Mode 4 +** <5> 1 PCDZ5 Power Control Doze Mode 5 +** <6> 1 PCDZ6 Power Control Doze Mode 6 +** <7> 1 PCDZ7 Power Control Doze Mode 7 +** <8> 1 PCDZ8 Power Control Doze Mode 8 +** <9> 1 PCDZ9 Power Control Doze Mode 9 +** <10> 1 SPNDDLY Suspend Delay +** <11> 1 STRTDLY Start Delay +** +** <12:15> Reserved +*/ +#define PMC_DZMPCR_REG 0x00A +#define PMC_DZMPCR_INIT ( DZMPCR_M_PCDZ0 | DZMPCR_M_PCDZ1 | \ + DZMPCR_M_PCDZ2 ) +#define DZMPCR_V_PCDZ 0 +#define DZMPCR_M_PCDZ 0x3FF << DZMPCR_V_PCDZ +#define DZMPCR_V_PCDZ0 0 +#define DZMPCR_M_PCDZ0 1 << DZMPCR_V_PCDZ0 +#define DZMPCR_V_PCDZ1 1 +#define DZMPCR_M_PCDZ1 1 << DZMPCR_V_PCDZ1 +#define DZMPCR_V_PCDZ2 2 +#define DZMPCR_M_PCDZ2 1 << DZMPCR_V_PCDZ2 +#define DZMPCR_V_PCDZ3 3 +#define DZMPCR_M_PCDZ3 1 << DZMPCR_V_PCDZ3 +#define DZMPCR_V_PCDZ4 4 +#define DZMPCR_M_PCDZ4 1 << DZMPCR_V_PCDZ4 +#define DZMPCR_V_PCDZ5 5 +#define DZMPCR_M_PCDZ5 1 << DZMPCR_V_PCDZ5 +#define DZMPCR_V_PCDZ6 6 +#define DZMPCR_M_PCDZ6 1 << DZMPCR_V_PCDZ6 +#define DZMPCR_V_PCDZ7 7 +#define DZMPCR_M_PCDZ7 1 << DZMPCR_V_PCDZ7 +#define DZMPCR_V_PCDZ8 8 +#define DZMPCR_M_PCDZ8 1 << DZMPCR_V_PCDZ8 +#define DZMPCR_V_PCDZ9 9 +#define DZMPCR_M_PCDZ9 1 << DZMPCR_V_PCDZ9 +#define DZMPCR_V_SPNDDLY 10 +#define DZMPCR_M_SPNDDLY 1 << DZMPCR_V_SPNDDLY +#define DZMPCR_V_STRTDLY 11 +#define DZMPCR_M_STRTDLY 1 << DZMPCR_V_STRTDLY + +/* +** +** Sleep Mode Power Control Register (SLPMPCR) - Index 0x00B +** +** Loc Size Name Function +** ----- ---- ---- --------------------------------- +** <0> 1 PCSLP0 Power Control Sleep Mode 0 +** <1> 1 PCSLP1 Power Control Sleep Mode 1 +** <2> 1 PCSLP2 Power Control Sleep Mode 2 +** <3> 1 PCSLP3 Power Control Sleep Mode 3 +** <4> 1 PCSLP4 Power Control Sleep Mode 4 +** <5> 1 PCSLP5 Power Control Sleep Mode 5 +** <6> 1 PCSLP6 Power Control Sleep Mode 6 +** <7> 1 PCSLP7 Power Control Sleep Mode 7 +** <8> 1 PCSLP8 Power Control Sleep Mode 8 +** <9> 1 PCSLP9 Power Control Sleep Mode 9 +** <10> 1 LBLEDFLSH Low Battery LED Flasher Enable +** <11> 1 LBFLSHRAT0 Low Battery LED Flash Rate Selects 0 +** <12> 1 LBFLSHRAT1 Low Battery LED Flash Rate Selects 1 +** <13> 1 LBFLSHDUR0 Low Battery LED Flash Rate Duration 0 +** <14> 1 LBFLSHDUR1 Low Battery LED Flash Rate Duration 1 +** <15> 1 VLBFLSHEN Very Low Battery Flash Enable +** +*/ +#define PMC_SLPMPCR_REG 0x00B +#define PMC_SLPMPCR_INIT ( SLPMPCR_M_PCSLP0 | SLPMPCR_M_PCSLP1 | \ + SLPMPCR_M_PCSLP2 | LBFLSHRAT_2HZ | \ + LBFLSHDUR_62PT5MS ) +#define SLPMPCR_V_PCSLP 0 +#define SLPMPCR_M_PCSLP 0x3FF << SLPMPCR_V_PCSLP +#define SLPMPCR_V_PCSLP0 0 +#define SLPMPCR_M_PCSLP0 1 << SLPMPCR_V_PCSLP0 +#define SLPMPCR_V_PCSLP1 1 +#define SLPMPCR_M_PCSLP1 1 << SLPMPCR_V_PCSLP1 +#define SLPMPCR_V_PCSLP2 2 +#define SLPMPCR_M_PCSLP2 1 << SLPMPCR_V_PCSLP2 +#define SLPMPCR_V_PCSLP3 3 +#define SLPMPCR_M_PCSLP3 1 << SLPMPCR_V_PCSLP3 +#define SLPMPCR_V_PCSLP4 4 +#define SLPMPCR_M_PCSLP4 1 << SLPMPCR_V_PCSLP4 +#define SLPMPCR_V_PCSLP5 5 +#define SLPMPCR_M_PCSLP5 1 << SLPMPCR_V_PCSLP5 +#define SLPMPCR_V_PCSLP6 6 +#define SLPMPCR_M_PCSLP6 1 << SLPMPCR_V_PCSLP6 +#define SLPMPCR_V_PCSLP7 7 +#define SLPMPCR_M_PCSLP7 1 << SLPMPCR_V_PCSLP7 +#define SLPMPCR_V_PCSLP8 8 +#define SLPMPCR_M_PCSLP8 1 << SLPMPCR_V_PCSLP8 +#define SLPMPCR_V_PCSLP9 9 +#define SLPMPCR_M_PCSLP9 1 << SLPMPCR_V_PCSLP9 +#define SLPMPCR_V_LBLEDFLSH 10 +#define SLPMPCR_M_LBLEDFLSH 1 << SLPMPCR_V_LBLEDFLSH +#define SLPMPCR_V_LBFLSHRAT 11 +#define SLPMPCR_M_LBFLSHRAT 0x3 << SLPMPCR_V_LBFLSHRAT +#define SLPMPCR_V_LBFLSHRAT0 11 +#define SLPMPCR_M_LBFLSHRAT0 1 << SLPMPCR_V_LBFLSHRAT0 +#define SLPMPCR_V_LBFLSHRAT1 12 +#define SLPMPCR_M_LBFLSHRAT1 1 << SLPMPCR_V_LBFLSHRAT1 +#define SLPMPCR_V_LBFLSHDUR 13 +#define SLPMPCR_M_LBFLSHDUR 0x3 << SLPMPCR_V_LBFLSHDUR +#define SLPMPCR_V_LBFLSHDUR0 13 +#define SLPMPCR_M_LBFLSHDUR0 1 << SLPMPCR_V_LBFLSHDUR0 +#define SLPMPCR_V_LBFLSHDUR1 14 +#define SLPMPCR_M_LBFLSHDUR1 1 << SLPMPCR_V_LBFLSHDUR1 +#define SLPMPCR_V_VLBFLSHEN 15 +#define SLPMPCR_M_VLBFLSHEN 1 << SLPMPCR_V_VLBFLSHEN + +/* +** Low Battery LED Flash Rate Selects +*/ +#define LBFLSHRAT_HLFHZ 0x000 +#define LBFLSHRAT_1HZ SLPMPCR_M_LBFLSHRAT0 +#define LBFLSHRAT_2HZ SLPMPCR_M_LBFLSHRAT1 +#define LBFLSHRAT_4HZ (SLPMPCR_M_LBFLSHRAT0 | SLPMPCR_M_LBFLSHRAT1) + +/* +** Low Battery LED Flash Rate Duration (milliseconds) +*/ +#define LBFLSHDUR_256MS 0x000 +#define LBFLSHDUR_128MS SLPMPCR_M_LBFLSHDUR0 +#define LBFLSHDUR_62PT5MS SLPMPCR_M_LBFLSHDUR1 +#define LBFLSHDUR_31PT25MS (SLPMPCR_M_LBFLSHDUR0 | SLPMPCR_M_LBFLSHDUR1) + + +/* +** +** Suspend Mode Power Control Register (SPNDMPCR) - Index 0x00C +** +** Loc Size Name Function +** ----- ---- ---- --------------------------------- +** <0> 1 PCSPND0 Power Control Suspend Mode 0 +** <1> 1 PCSPND1 Power Control Suspend Mode 1 +** <2> 1 PCSPND2 Power Control Suspend Mode 2 +** <3> 1 PCSPND3 Power Control Suspend Mode 3 +** <4> 1 PCSPND4 Power Control Suspend Mode 4 +** <5> 1 PCSPND5 Power Control Suspend Mode 5 +** <6> 1 PCSPND6 Power Control Suspend Mode 6 +** <7> 1 PCSPND7 Power Control Suspend Mode 7 +** <8> 1 PCSPND8 Power Control Suspend Mode 8 +** <9> 1 PCSPND9 Power Control Suspend Mode 9 +** <10> 1 SPLEDFLSH Suspend LED Flasher Enable +** <11> 1 SPFLSHRAT0 Suspend LED Flash Rate Selects 0 +** <12> 1 SPFLSHRAT1 Suspend LED Flash Rate Selects 1 +** <13> 1 SPFLSHDUR0 Suspend LED Flash Rate Duration 0 +** <14> 1 SPFLSHDUR1 Suspend LED Flash Rate Duration 1 +** +** <15> Reserved +** +*/ +#define PMC_SPNDMPCR_REG 0x00c +#define PMC_SPNDMPCR_INIT ( SPNDMPCR_M_PCSPND0 | SPNDMPCR_M_PCSPND1 | \ + SPNDMPCR_M_PCSPND2 | SPFLSHRAT_2HZ | \ + SPFLSHDUR_62PT5MS ) +#define SPNDMPCR_V_PCSPND 0 +#define SPNDMPCR_M_PCSPND 0x3FF << SPNDMPCR_V_PCSPND +#define SPNDMPCR_V_PCSPND0 0 +#define SPNDMPCR_M_PCSPND0 1 << SPNDMPCR_V_PCSPND0 +#define SPNDMPCR_V_PCSPND1 1 +#define SPNDMPCR_M_PCSPND1 1 << SPNDMPCR_V_PCSPND1 +#define SPNDMPCR_V_PCSPND2 2 +#define SPNDMPCR_M_PCSPND2 1 << SPNDMPCR_V_PCSPND2 +#define SPNDMPCR_V_PCSPND3 3 +#define SPNDMPCR_M_PCSPND3 1 << SPNDMPCR_V_PCSPND3 +#define SPNDMPCR_V_PCSPND4 4 +#define SPNDMPCR_M_PCSPND4 1 << SPNDMPCR_V_PCSPND4 +#define SPNDMPCR_V_PCSPND5 5 +#define SPNDMPCR_M_PCSPND5 1 << SPNDMPCR_V_PCSPND5 +#define SPNDMPCR_V_PCSPND6 6 +#define SPNDMPCR_M_PCSPND6 1 << SPNDMPCR_V_PCSPND6 +#define SPNDMPCR_V_PCSPND7 7 +#define SPNDMPCR_M_PCSPND7 1 << SPNDMPCR_V_PCSPND7 +#define SPNDMPCR_V_PCSPND8 8 +#define SPNDMPCR_M_PCSPND8 1 << SPNDMPCR_V_PCSPND8 +#define SPNDMPCR_V_PCSPND9 9 +#define SPNDMPCR_M_PCSPND9 1 << SPNDMPCR_V_PCSPND9 +#define SPNDMPCR_V_SPLEDFLSH 10 +#define SPNDMPCR_M_SPLEDFLSH 1 << SPNDMPCR_V_SPLEDFLSH +#define SPNDMPCR_V_SPFLSHRAT 11 +#define SPNDMPCR_M_SPFLSHRAT 0x3 << SPNDMPCR_V_SPFLSHRAT +#define SPNDMPCR_V_SPFLSHRAT0 11 +#define SPNDMPCR_M_SPFLSHRAT0 1 << SPNDMPCR_V_SPFLSHRAT0 +#define SPNDMPCR_V_SPFLSHRAT1 12 +#define SPNDMPCR_M_SPFLSHRAT1 1 << SPNDMPCR_V_SPFLSHRAT1 +#define SPNDMPCR_V_SPFLSHDUR 13 +#define SPNDMPCR_M_SPFLSHDUR 0x3 << SPNDMPCR_V_SPFLSHDUR +#define SPNDMPCR_V_SPFLSHDUR0 13 +#define SPNDMPCR_M_SPFLSHDUR0 1 << SPNDMPCR_V_SPFLSHDUR0 +#define SPNDMPCR_V_SPFLSHDUR1 14 +#define SPNDMPCR_M_SPFLSHDUR1 1 << SPNDMPCR_V_SPFLSHDUR1 + +/* +** Suspend LED Flash Rate Selects +*/ +#define SPFLSHRAT_HLFHZ 0x000 +#define SPFLSHRAT_1HZ SPNDMPCR_M_SPFLSHRAT0 +#define SPFLSHRAT_2HZ SPNDMPCR_M_SPFLSHRAT1 +#define SPFLSHRAT_4HZ (SPNDMPCR_M_SPFLSHRAT0 | SPNDMPCR_M_SPFLSHRAT1) + +/* +** Suspend LED Flash Rate Duration (milliseconds) +*/ +#define SPFLSHDUR_256MS 0x000 +#define SPFLSHDUR_128MS SPNDMPCR_M_SPFLSHDUR0 +#define SPFLSHDUR_62PT5MS SPNDMPCR_M_SPFLSHDUR1 +#define SPFLSHDUR_31PT25MS (SPNDMPCR_M_SPFLSHDUR0 | SPNDMPCR_M_SPFLSHDUR1) + +/* +** +** Timer Register (TIMERR) - Index 0x00D +** +** Loc Size Name Function +** ----- ---- ---- --------------------------------- +** <0> 1 GENTMR0 Generic Timer 0 +** <1> 1 GENTMR1 Generic Timer 1 +** <2> 1 GENTMR2 Generic Timer 2 +** <3> 1 GENTMR3 Generic Timer 3 +** <4> 1 SPMDTMR0 Suspend Mode Timer 0 +** <5> 1 SPMDTMR1 Suspend Mode Timer 1 +** <6> 1 SPMDTMR2 Suspend Mode Timer 2 +** <7> 1 SLPTMR0 Sleep Mode Timer 0 +** <8> 1 SLPTMR1 Sleep Mode Timer 1 +** <9> 1 SLPTMR2 Sleep Mode Timer 2 +** <10> 1 DZTMR0 Doze Mode Timer 0 +** <11> 1 DZTMR1 Doze Mode Timer 1 +** <12> 1 DZTMR2 Doze Mode Timer 2 +** <15> 1 GTRSTPADIS Generic Timer Reset by PA Disable +** +** <13:14> Reserved +** +*/ +#define PMC_TIMERR_REG 0x00D +#define PMC_TIMERR_INIT 0x0000 +#define TIMERR_V_GENTMR 0 +#define TIMERR_M_GENTMR 0xF << TIMERR_V_GENTMR +#define TIMERR_V_GENTMR0 0 +#define TIMERR_M_GENTMR0 1 << TIMERR_V_GENTMR0 +#define TIMERR_V_GENTMR1 1 +#define TIMERR_M_GENTMR1 1 << TIMERR_V_GENTMR1 +#define TIMERR_V_GENTMR2 2 +#define TIMERR_M_GENTMR2 1 << TIMERR_V_GENTMR2 +#define TIMERR_V_GENTMR3 3 +#define TIMERR_M_GENTMR3 1 << TIMERR_V_GENTMR3 +#define TIMERR_V_SPMDTMR 4 +#define TIMERR_M_SPMDTMR 0x7 << TIMERR_V_SPMDTMR +#define TIMERR_V_SPMDTMR0 4 +#define TIMERR_M_SPMDTMR0 1 << TIMERR_V_SPMDTMR0 +#define TIMERR_V_SPMDTMR1 5 +#define TIMERR_M_SPMDTMR1 1 << TIMERR_V_SPMDTMR1 +#define TIMERR_V_SPMDTMR2 6 +#define TIMERR_M_SPMDTMR2 1 << TIMERR_V_SPMDTMR2 +#define TIMERR_V_SLPTMR 7 +#define TIMERR_M_SLPTMR 0x7 << TIMERR_V_SLPTMR +#define TIMERR_V_SLPTMR0 7 +#define TIMERR_M_SLPTMR0 1 << TIMERR_V_SLPTMR0 +#define TIMERR_V_SLPTMR1 8 +#define TIMERR_M_SLPTMR1 1 << TIMERR_V_SLPTMR1 +#define TIMERR_V_SLPTMR2 9 +#define TIMERR_M_SLPTMR2 1 << TIMERR_V_SLPTMR2 +#define TIMERR_V_DZTMR 10 +#define TIMERR_M_DZTMR 0x7 << TIMERR_V_DZTMR +#define TIMERR_V_DZTMR0 10 +#define TIMERR_M_DZTMR0 1 << TIMERR_V_DZTMR0 +#define TIMERR_V_DZTMR1 11 +#define TIMERR_M_DZTMR1 1 << TIMERR_V_DZTMR1 +#define TIMERR_V_DZTMR2 12 +#define TIMERR_M_DZTMR2 1 << TIMERR_V_DZTMR2 +#define TIMERR_V_GTRSTPADIS 15 +#define TIMERR_M_GTRSTPADIS 1 << TIMERR_V_GTRSTPADIS + +/* +** Generic Timer (Seconds) +*/ +#define GENTMR_DISABLE 0x000 +#define GENTMR_2S TIMERR_M_GENTMR0 +#define GENTMR_4S TIMERR_M_GENTMR1 +#define GENTMR_6S (TIMERR_M_GENTMR0 | TIMERR_M_GENTMR1) +#define GENTMR_8S TIMERR_M_GENTMR2 +#define GENTMR_10S (TIMERR_M_GENTMR0 | TIMERR_M_GENTMR2) +#define GENTMR_15S (TIMERR_M_GENTMR1 | TIMERR_M_GENTMR2) +#define GENTMR_20S (TIMERR_M_GENTMR0 | TIMERR_M_GENTMR1 | TIMERR_M_GENTMR2) +#define GENTMR_25S TIMERR_M_GENTMR3 +#define GENTMR_30S (TIMERR_M_GENTMR0 | TIMERR_M_GENTMR3) +#define GENTMR_40S (TIMERR_M_GENTMR1 | TIMERR_M_GENTMR3) +#define GENTMR_50S (TIMERR_M_GENTMR0 | TIMERR_M_GENTMR1 | TIMERR_M_GENTMR3) +#define GENTMR_60S (TIMERR_M_GENTMR2 | TIMERR_M_GENTMR3) +#define GENTMR_75S (TIMERR_M_GENTMR0 | TIMERR_M_GENTMR2 | TIMERR_M_GENTMR3) +#define GENTMR_90S (TIMERR_M_GENTMR1 | TIMERR_M_GENTMR2 | TIMERR_M_GENTMR3) +#define GENTMR_120S (TIMERR_M_GENTMR0 | TIMERR_M_GENTMR1 | TIMERR_M_GENTMR2 | TIMERR_M_GENTMR3) + +/* +** Suspend Mode Timer (Minutes) +*/ +#define SPMDTMR_DISABLE 0x000 +#define SPMDTMR_5MIN TIMERR_M_SPMDTMR0 +#define SPMDTMR_10MIN TIMERR_M_SPMDTMR1 +#define SPMDTMR_15MIN (TIMERR_M_SPMDTMR0 | TIMERR_M_SPMDTMR1) +#define SPMDTMR_20MIN TIMERR_M_SPMDTMR2 +#define SPMDTMR_30MIN (TIMERR_M_SPMDTMR0 | TIMERR_M_SPMDTMR2) +#define SPMDTMR_40MIN (TIMERR_M_SPMDTMR1 | TIMERR_M_SPMDTMR2) +#define SPMDTMR_60MIN (TIMERR_M_SPMDTMR0 | TIMERR_M_SPMDTMR1 | TIMERR_M_SPMDTMR2) + +/* +** Sleep Mode Timer (Minutes) +*/ +#define SLPTMR_DISABLE 0x000 +#define SLPTMR_1MIN TIMERR_M_SLPTMR0 +#define SLPTMR_2MIN TIMERR_M_SLPTMR1 +#define SLPTMR_4MIN (TIMERR_M_SLPTMR0 | TIMERR_M_SLPTMR1) +#define SLPTMR_6MIN TIMERR_M_SLPTMR2 +#define SLPTMR_8MIN (TIMERR_M_SLPTMR0 | TIMERR_M_SLPTMR2) +#define SLPTMR_12MIN (TIMERR_M_SLPTMR1 | TIMERR_M_SLPTMR2) +#define SLPTMR_16MIN (TIMERR_M_SLPTMR0 | TIMERR_M_SLPTMR1 | TIMERR_M_SLPTMR2) + +/* +** Doze Mode Timer (Seconds) +*/ +#define DZTMR_DISABLE 0x000 +#define DZTMR_PT125S TIMERR_M_DZTMR0 +#define DZTMR_PT250S TIMERR_M_DZTMR1 +#define DZTMR_PT500S (TIMERR_M_DZTMR0 | TIMERR_M_DZTMR1) +#define DZTMR_1S TIMERR_M_DZTMR2 +#define DZTMR_4S (TIMERR_M_DZTMR0 | TIMERR_M_DZTMR2) +#define DZTMR_8S (TIMERR_M_DZTMR1 | TIMERR_M_DZTMR2) +#define DZTMR_16S (TIMERR_M_DZTMR0 | TIMERR_M_DZTMR1 | TIMERR_M_DZTMR2) + +/* +** +** PMC Miscellaneous Control 1 Register (PMCMCR1) - Index 0x00E +** +** Loc Size Name Function +** ----- ---- ---- --------------------------------- +** <2> 1 GPCTSEL0 General Purpose Counter/Timer Select 0 +** <3> 1 GPCTSEL1 General Purpose Counter/Timer Select 1 +** <4> 1 GPCTEN Generic Purpose Counter/Timer Enable +** <5> 1 WMSKVLBNAC Wake Mask VLB if Not ACPWR +** <6> 1 WAKE0MSK WAKE0 Mask +** <7> 1 WAKE1MSK WAKE1 Mask +** <8> 1 WMSKRING Wake Mask RING +** <9> 1 WMSKRTC Wake Mask RTC +** <11> 1 WMSKTMR Wake Mask GP Timer +** <12> 1 PRDCTID0 Product Identification 0 +** <13> 1 PRDCTID1 Product Identification 1 +** <14> 1 PRDCTID2 Product Identification 2 +** <15> 1 PRDCTID3 Product Identification 3 +** +** <0:1><10> Reserved +** +*/ +#define PMC_PMCMCR1_REG 0x00E +#define PMC_PMCMCR1_INIT ( PMCMCR1_M_WMSKVLBNAC | PMCMCR1_M_WAKE0MSK | \ + PMCMCR1_M_WAKE1MSK | PMCMCR1_M_WMSKRING | \ + PMCMCR1_M_WMSKRTC | PMCMCR1_M_WMSKTMR ) +#define PMCMCR1_V_GPCTSEL0 2 +#define PMCMCR1_M_GPCTSEL0 1 << PMCMCR1_V_GPCTSEL0 +#define PMCMCR1_V_GPCTSEL1 3 +#define PMCMCR1_M_GPCTSEL1 1 << PMCMCR1_V_GPCTSEL1 +#define PMCMCR1_V_GPCTEN 4 +#define PMCMCR1_M_GPCTEN 1 << PMCMCR1_V_GPCTEN +#define PMCMCR1_V_WMSKVLBNAC 5 +#define PMCMCR1_M_WMSKVLBNAC 1 << PMCMCR1_V_WMSKVLBNAC +#define PMCMCR1_V_WAKE0MSK 6 +#define PMCMCR1_M_WAKE0MSK 1 << PMCMCR1_V_WAKE0MSK +#define PMCMCR1_V_WAKE1MSK 7 +#define PMCMCR1_M_WAKE1MSK 1 << PMCMCR1_V_WAKE1MSK +#define PMCMCR1_V_WMSKRING 8 +#define PMCMCR1_M_WMSKRING 1 << PMCMCR1_V_WMSKRING +#define PMCMCR1_V_WMSKRTC 9 +#define PMCMCR1_M_WMSKRTC 1 << PMCMCR1_V_WMSKRTC +#define PMCMCR1_V_WMSKTMR 11 +#define PMCMCR1_M_WMSKTMR 1 << PMCMCR1_V_WMSKTMR +#define PMCMCR1_V_PRDCTID 12 +#define PMCMCR1_M_PRDCTID 0xF << PMCMCR1_V_PRDCTID + +/* +** +** GP Counter/Timer Register (GPCTR) - Index 0x010 +** +** Loc Size Name Function +** ----- ---- ---- --------------------------------- +** <0> 1 GPCT0 General Purpose Counter/Timer 0 +** <1> 1 GPCT1 General Purpose Counter/Timer 1 +** <2> 1 GPCT2 General Purpose Counter/Timer 2 +** <3> 1 GPCT3 General Purpose Counter/Timer 3 +** <4> 1 GPCT4 General Purpose Counter/Timer 4 +** <5> 1 GPCT5 General Purpose Counter/Timer 5 +** <6> 1 GPCT6 General Purpose Counter/Timer 6 +** <7> 1 GPCT7 General Purpose Counter/Timer 7 +** <8> 1 GPCT8 General Purpose Counter/Timer 8 +** <9> 1 GPCT9 General Purpose Counter/Timer 9 +** <10> 1 GPCT10 General Purpose Counter/Timer 10 +** <11> 1 GPCT11 General Purpose Counter/Timer 11 +** <12> 1 GPCT12 General Purpose Counter/Timer 12 +** <13> 1 GPCT13 General Purpose Counter/Timer 13 +** <14> 1 GPCT14 General Purpose Counter/Timer 14 +** <15> 1 GPCT15 General Purpose Counter/Timer 15 +** +*/ +#define PMC_GPCTR_REG 0x010 +#define GPCTR_M_GPCTR 0xFFFFFFFF + +/* +** +** GP Timer Compare Register (GPTMRCMPR) - Index 0x011 +** +** Loc Size Name Function +** ----- ---- ---- --------------------------------- +** <0> 1 GPTMRCMP0 GP Counter/Timer Compare 0 +** <1> 1 GPTMRCMP1 GP Counter/Timer Compare 1 +** <2> 1 GPTMRCMP2 GP Counter/Timer Compare 2 +** <3> 1 GPTMRCMP3 GP Counter/Timer Compare 3 +** <4> 1 GPTMRCMP4 GP Counter/Timer Compare 4 +** <5> 1 GPTMRCMP5 GP Counter/Timer Compare 5 +** <6> 1 GPTMRCMP6 GP Counter/Timer Compare 6 +** <7> 1 GPTMRCMP7 GP Counter/Timer Compare 7 +** <8> 1 GPTMRCMP8 GP Counter/Timer Compare 8 +** <9> 1 GPTMRCMP9 GP Counter/Timer Compare 9 +** <10> 1 GPTMRCMP10 GP Counter/Timer Compare 10 +** <11> 1 GPTMRCMP11 GP Counter/Timer Compare 11 +** <12> 1 GPTMRCMP12 GP Counter/Timer Compare 12 +** <13> 1 GPTMRCMP13 GP Counter/Timer Compare 13 +** <14> 1 GPTMRCMP14 GP Counter/Timer Compare 14 +** <15> 1 GPTMRCMP15 GP Counter/Timer Compare 15 +** +*/ +#define PMC_GPTMRCMPR_REG 0x010 +#define GPTMRCMPR_M_GPTMRCMPR 0xFFFFFFFF + +/* +** +** Debounce Control Register (DBCR) - Index 0x012 +** +** Loc Size Name Function +** ----- ---- ---- --------------------------------- +** <0> 1 DBDIS0 Debounce Disable 0 +** <2> 1 DBDIS1 Debounce Disable 1 +** <3> 1 DBTMDR1 Debounce Time Duration 1 +** <4> 1 DBDIS2 Debounce Disable 2 +** <5> 1 DBTMDR2 Debounce Time Duration 2 +** <6> 1 DBDIS3 Debounce Disable 3 +** <7> 1 DBTMDR3 Debounce Time Duration 3 +** <12> 1 WAKE0DBDIS WAKE0 Debounce Disable +** <13> 1 WAKE0DBTMDR WAKE0 Debounce Time Duration +** <14> 1 WAKE1DBDIS WAKE1 Debounce Disable +** <15> 1 WAKE1DBTMDR WAKE1 Debounce Time Duration +** +** <1><8:11> Reserved +** +*/ +#define PMC_DBCR_REG 0x012 +#define PMC_DBCR_INIT 0x0000 +#define DBCR_V_DBDIS0 0 +#define DBCR_M_DBDIS0 1 << DBCR_V_DBDIS0 +#define DBCR_V_DBDIS1 2 +#define DBCR_M_DBDIS1 1 << DBCR_V_DBDIS1 +#define DBCR_V_DBTMDR1 3 +#define DBCR_M_DBTMDR1 1 << DBCR_V_DBTMDR1 +#define DBCR_V_DBDIS2 4 +#define DBCR_M_DBDIS2 1 << DBCR_V_DBDIS2 +#define DBCR_V_DBTMDR2 5 +#define DBCR_M_DBTMDR2 1 << DBCR_V_DBTMDR2 +#define DBCR_V_DBDIS3 6 +#define DBCR_M_DBDIS3 1 << DBCR_V_DBDIS3 +#define DBCR_V_DBTMDR3 7 +#define DBCR_M_DBTMDR3 1 << DBCR_V_DBTMDR3 +#define DBCR_V_WAKE0DBDIS 12 +#define DBCR_M_WAKE0DBDIS 1 << DBCR_V_WAKE0DBDIS +#define DBCR_V_WAKE0DBTMDR 13 +#define DBCR_M_WAKE0DBTMDR 1 << DBCR_V_WAKE0DBTMDR +#define DBCR_V_WAKE1DBDIS 14 +#define DBCR_M_WAKE1DBDIS 1 << DBCR_V_WAKE1DBDIS +#define DBCR_V_WAKE1DBTMDR 15 +#define DBCR_M_WAKE1DBTMDR 1 << DBCR_V_WAKE1DBTMDR + +/* +** +** PMC Miscellaneous Control 2 Register (PMCMCR2) - Index 0x013 +** +** Loc Size Name Function +** ----- ---- ---- --------------------------------- +** <1> 1 SMIRDYEN SMIRDY# Enable +** <2> 1 PWRGDSTBYDIS PWRGOOD Standby Disable +** <3> 1 GLBLRSTEN Global Reset Enable +** <4> 1 PMCRSTEN PMC Reset Enable +** <7> 1 SPSRESETDIS Disable SRESET Upon Resume +** <8> 1 SPRSTDRVDIS Disable RSTDRV Upon Resume +** <9> 1 WAKE0TOGL WAKE0 Toggle Select +** <10> 1 WAKE1TOGL WAKE1 Toggle Select +** <14> 1 SWTCHEN SWTCH Enable +** <15> 1 RSTCPUFLG RSTCPU Flag +** +** <0><5:6><11:13> Reserved +** +*/ +#define PMC_PMCMCR2_REG 0x013 +#define PMC_PMCMCR2_INIT ( PMCMCR2_M_PWRGDSTBYDIS | PMCMCR2_M_GLBLRSTEN | \ + PMCMCR2_M_PMCRSTEN | \ + PMCMCR2_M_SPSRESETDIS ) +#define PMCMCR2_V_GPCTSEL0 1 +#define PMCMCR2_M_GPCTSEL0 1 << PMCMCR2_V_SMIRDYEN +#define PMCMCR2_V_PWRGDSTBYDIS 2 +#define PMCMCR2_M_PWRGDSTBYDIS 1 << PMCMCR2_V_PWRGDSTBYDIS +#define PMCMCR2_V_GLBLRSTEN 3 +#define PMCMCR2_M_GLBLRSTEN 1 << PMCMCR2_V_GLBLRSTEN +#define PMCMCR2_V_PMCRSTEN 4 +#define PMCMCR2_M_PMCRSTEN 1 << PMCMCR2_V_PMCRSTEN +#define PMCMCR2_V_SPSRESETDIS 7 +#define PMCMCR2_M_SPSRESETDIS 1 << PMCMCR2_V_SPSRESETDIS +#define PMCMCR2_V_SPRSTDRVDIS 8 +#define PMCMCR2_M_SPRSTDRVDIS 1 << PMCMCR2_V_SPRSTDRVDIS +#define PMCMCR2_V_WAKE0TOGL 9 +#define PMCMCR2_M_WAKE0TOGL 1 << PMCMCR2_V_WAKE0TOGL +#define PMCMCR2_V_WAKE1TOGL 10 +#define PMCMCR2_M_WAKE1TOGL 1 << PMCMCR2_V_WAKE1TOGL +#define PMCMCR2_V_SWTCHEN 14 +#define PMCMCR2_M_SWTCHEN 1 << PMCMCR2_V_SWTCHEN +#define PMCMCR2_V_RSTCPUFLG 15 +#define PMCMCR2_M_RSTCPUFLG 1 << PMCMCR2_V_RSTCPUFLG + +/* +** +** Optional GPIO Control Register 2 (GPIOCR2) - Index 0x014 +** +** Loc Size Name Function +** ----- ---- ---- --------------------------------- +** <0> 1 GPIOADATA0 General Purpose I/O A Data 0 +** <1> 1 GPIOADATA1 General Purpose I/O A Data 1 +** <2> 1 GPIOADIR0 General Purpose I/O A Direction 0 +** <3> 1 GPIOADIR1 General Purpose I/O A Direction 1 +** <4> 1 GPIOBDATA0 General Purpose I/O B Data 0 +** <5> 1 GPIOBDATA1 General Purpose I/O B Data 1 +** <6> 1 GPIOBDIR0 General Purpose I/O B Direction 0 +** <7> 1 GPIOBDIR1 General Purpose I/O B Direction 1 +** <8> 1 GPIOCDATA0 General Purpose I/O C Data 0 +** <9> 1 GPIOCDATA1 General Purpose I/O C Data 1 +** <10> 1 GPIOCDIR0 General Purpose I/O C Direction 0 +** <11> 1 GPIOCDIR1 General Purpose I/O C Direction 1 +** +** <12:15> Reserved +** +*/ +#define PMC_GPIOCR2_REG 0x014 +#define PMC_GPIOCR2_INIT ( GPIOCR2_M_GPIOADIR0 | GPIOCR2_M_GPIOADIR1 | \ + GPIOCR2_M_GPIOBDIR1 | GPIOCR2_M_GPIOCDATA0 | \ + GPIOCR2_M_GPIOCDIR0 | GPIOCR2_M_GPIOCDIR1 ) +#define GPIOCR2_V_GPIOADATA 0 +#define GPIOCR2_M_GPIOADATA 0x3 << GPIOCR2_V_GPIOADATA +#define GPIOCR2_V_GPIOADATA0 0 +#define GPIOCR2_M_GPIOADATA0 1 << GPIOCR2_V_GPIOADATA0 +#define GPIOCR2_V_GPIOADATA1 1 +#define GPIOCR2_M_GPIOADATA1 1 << GPIOCR2_V_GPIOADATA1 +#define GPIOCR2_V_GPIOADIR 2 +#define GPIOCR2_M_GPIOADIR 0x3 << GPIOCR2_V_GPIOADIR +#define GPIOCR2_V_GPIOADIR0 2 +#define GPIOCR2_M_GPIOADIR0 1 << GPIOCR2_V_GPIOADIR0 +#define GPIOCR2_V_GPIOADIR1 3 +#define GPIOCR2_M_GPIOADIR1 1 << GPIOCR2_V_GPIOADIR1 +#define GPIOCR2_V_GPIOBDATA 4 +#define GPIOCR2_M_GPIOBDATA 0x3 << GPIOCR2_V_GPIOBDATA +#define GPIOCR2_V_GPIOBDATA0 4 +#define GPIOCR2_M_GPIOBDATA0 1 << GPIOCR2_V_GPIOBDATA0 +#define GPIOCR2_V_GPIOBDATA1 5 +#define GPIOCR2_M_GPIOBDATA1 1 << GPIOCR2_V_GPIOBDATA1 +#define GPIOCR2_V_GPIOBDIR 6 +#define GPIOCR2_M_GPIOBDIR 0x3 << GPIOCR2_V_GPIOBDIR +#define GPIOCR2_V_GPIOBDIR0 6 +#define GPIOCR2_M_GPIOBDIR0 1 << GPIOCR2_V_GPIOBDIR0 +#define GPIOCR2_V_GPIOBDIR1 7 +#define GPIOCR2_M_GPIOBDIR1 1 << GPIOCR2_V_GPIOBDIR1 +#define GPIOCR2_V_GPIOCDATA 8 +#define GPIOCR2_M_GPIOCDATA 0x3 << GPIOCR2_V_GPIOCDATA +#define GPIOCR2_V_GPIOCDATA0 8 +#define GPIOCR2_M_GPIOCDATA0 1 << GPIOCR2_V_GPIOCDATA0 +#define GPIOCR2_V_GPIOCDATA1 9 +#define GPIOCR2_M_GPIOCDATA1 1 << GPIOCR2_V_GPIOCDATA1 +#define GPIOCR2_V_GPIOCDIR 10 +#define GPIOCR2_M_GPIOCDIR 0x3 << GPIOCR2_V_GPIOCDIR +#define GPIOCR2_V_GPIOCDIR0 10 +#define GPIOCR2_M_GPIOCDIR0 1 << GPIOCR2_V_GPIOCDIR0 +#define GPIOCR2_V_GPIOCDIR1 11 +#define GPIOCR2_M_GPIOCDIR1 1 << GPIOCR2_V_GPIOCDIR1 + +/* +** +** Leakage Control Register (LKCR) - Index 0x015 +** +** Loc Size Name Function +** ----- ---- ---- --------------------------------- +** <0> 1 CPULCDIS CPU Interface Leakage Control Disable +** <1> 1 DRAMLCDIS DRAM Interface Leakage Control Disable +** <2> 1 L2CACHELCDIS L2 Cache Leakage Control Disable +** <3> 1 ATLCDIS AT Bus Interface Leakage Control Disable +** <4> 1 BBUSLCDIS Burst Bus Interface Leakage Control Disable +** <5> 1 GPIOLCDIS GPIO Interface Leakage Control Disable +** <6> 1 PC49LCDIS PC4 to PC9 Leakage Control Disable +** <7> 1 LEDLCDIS LED Interface Leakage Control Disable +** <8> 1 BMLCDIS Battery Management Leakage Control Disable +** <9> 1 PC03LCDIS PC0 to PC3 Leakage Control Disable +** <14> 1 PWRGDLCDIS Enable Leakage Control +** <15> 1 LCDIS Global Leakage Control +** +** <10:13> Reserved +** +*/ +#define PMC_LKCR_REG 0x015 +#define PMC_LKCR_INIT ( LKCR_M_CPULCDIS | LKCR_M_DRAMLCDIS | \ + LKCR_M_L2CACHELCDIS | LKCR_M_ATLCDIS | \ + LKCR_M_BBUSLCDIS | LKCR_M_GPIOLCDIS | \ + LKCR_M_PC49LCDIS | LKCR_M_LEDLCDIS | \ + LKCR_M_BMLCDIS | LKCR_M_PC03LCDIS | \ + LKCR_M_PWRGDLCDIS | LKCR_M_LCDIS ) +#define LKCR_V_CPULCDIS 0 +#define LKCR_M_CPULCDIS 1 << LKCR_V_CPULCDIS +#define LKCR_V_DRAMLCDIS 1 +#define LKCR_M_DRAMLCDIS 1 << LKCR_V_DRAMLCDIS +#define LKCR_V_L2CACHELCDIS 2 +#define LKCR_M_L2CACHELCDIS 1 << LKCR_V_L2CACHELCDIS +#define LKCR_V_ATLCDIS 3 +#define LKCR_M_ATLCDIS 1 << LKCR_V_ATLCDIS +#define LKCR_V_BBUSLCDIS 4 +#define LKCR_M_BBUSLCDIS 1 << LKCR_V_BBUSLCDIS +#define LKCR_V_GPIOLCDIS 5 +#define LKCR_M_GPIOLCDIS 1 << LKCR_V_GPIOLCDIS +#define LKCR_V_PC49LCDIS 6 +#define LKCR_M_PC49LCDIS 1 << LKCR_V_PC49LCDIS +#define LKCR_V_LEDLCDIS 7 +#define LKCR_M_LEDLCDIS 1 << LKCR_V_LEDLCDIS +#define LKCR_V_BMLCDIS 8 +#define LKCR_M_BMLCDIS 1 << LKCR_V_BMLCDIS +#define LKCR_V_PC03LCDIS 9 +#define LKCR_M_PC03LCDIS 1 << LKCR_V_PC03LCDIS +#define LKCR_V_PWRGDLCDIS 14 +#define LKCR_M_PWRGDLCDIS 1 << LKCR_V_PWRGDLCDIS +#define LKCR_V_LCDIS 15 +#define LKCR_M_LCDIS 1 << LKCR_V_LCDIS + +/* +** +** SEQUOIA-1 Miscellaneous Register 1 (SEQMR1) - Index 0x016 +** +** Loc Size Name Function +** ----- ---- ---- --------------------------------- +** <11> 1 DISCREADS Driving EADS# on Non-Cacheable Region +** <12> 1 FRCBLASTDIS Forcing BLAST low During Reset +** <14> 1 P92B3EN Enable Control Bit for Port 92 Bit 3 Function +** <15> 1 SWTSTBYDIS Disable Standby on SWTCH +** +** <0:10><13> Reserved +** +*/ +#define PMC_SEQMR1_REG 0x016 +#define PMC_SEQMR1_INIT 0x0000 +#define SEQMR1_V_DISCREADS 11 +#define SEQMR1_M_DISCREADS 1 << SEQMR1_V_DISCREADS +#define SEQMR1_V_FRCBLASTDIS 12 +#define SEQMR1_M_FRCBLASTDIS 1 << SEQMR1_V_FRCBLASTDIS +#define SEQMR1_V_P92B3EN 14 +#define SEQMR1_M_P92B3EN 1 << SEQMR1_V_P92B3EN +#define SEQMR1_V_SWTSTBYDIS 15 +#define SEQMR1_M_SWTSTBYDIS 1 << SEQMR1_V_SWTSTBYDIS + +/* +** +** SEQUOIA-1 Miscellaneous Register 2 (SEQMR2) - Index 0x017 +** +** Loc Size Name Function +** ----- ---- ---- --------------------------------- +** <0> 1 DLYWCASEN Delay Write CAS Enable +** <1> 1 SMMWTEN SMM Write-Through Enable +** <2> 1 STATICSPNDEN Static Suspend Enable +** +** <3:15> Reserved +** +*/ +#define PMC_SEQMR2_REG 0x017 +#define PMC_SEQMR2_INIT 0x0000 +#define SEQMR2_V_DLYWCASEN 0 +#define SEQMR2_M_DLYWCASEN 1 << SEQMR2_V_DLYWCASEN +#define SEQMR2_V_SMMWTEN 1 +#define SEQMR2_M_SMMWTEN 1 << SEQMR2_V_SMMWTEN +#define SEQMR2_V_STATICSPNDEN 2 +#define SEQMR2_M_STATICSPNDEN 1 << SEQMR2_V_STATICSPNDEN + +/* +** +** Secondary Activity Mask Register (SAMR) - Index 0x019 +** +** Loc Size Name Function +** ----- ---- ---- --------------------------------- +** <0> 1 SAMSKVID Secondary Activity Mask Video Accesses +** <3> 1 SAMSKKBD Secondary Activity Mask Keyboard Accesses +** <6> 1 SAMSKPROG0 Secondary Activity Mask PR 0 +** <7> 1 SAMSKPROG1 Secondary Activity Mask PR 1 +** <8> 1 SAMSKPROG2 Secondary Activity Mask PR 2 +** <9> 1 SAMSKPROG3 Secondary Activity Mask PR 3 +** <12> 1 SAMSKEACT0 Secondary Activity Mask EXTACT0 +** <13> 1 SAMSKEACT1 Secondary Activity Mask EXTACT1 +** <14> 1 SAMSKEACT2 Secondary Activity Mask EXTACT2 +** <15> 1 SAMSKEACT3 Secondary Activity Mask EXTACT3 +** +** <1:2><4:5><10:11> Reserved +** +*/ +#define PMC_SAMR_REG 0x019 +#define PMC_SAMR_INIT ( SAMR_M_SAMSKVID | SAMR_M_SAMSKKBD | \ + SAMR_M_SAMSKPROG0 | SAMR_M_SAMSKPROG1 | \ + SAMR_M_SAMSKPROG2 | SAMR_M_SAMSKPROG3 | \ + SAMR_M_SAMSKEACT0 | SAMR_M_SAMSKEACT1 | \ + SAMR_M_SAMSKEACT2 | SAMR_M_SAMSKEACT3 ) +#define SAMR_V_SAMSKVID 0 +#define SAMR_M_SAMSKVID 1 << SAMR_V_SAMSKVID +#define SAMR_V_SAMSKKBD 3 +#define SAMR_M_SAMSKKBD 1 << SAMR_V_SAMSKKBD +#define SAMR_V_SAMSKPROG0 6 +#define SAMR_M_SAMSKPROG0 1 << SAMR_V_SAMSKPROG0 +#define SAMR_V_SAMSKPROG1 7 +#define SAMR_M_SAMSKPROG1 1 << SAMR_V_SAMSKPROG1 +#define SAMR_V_SAMSKPROG2 8 +#define SAMR_M_SAMSKPROG2 1 << SAMR_V_SAMSKPROG2 +#define SAMR_V_SAMSKPROG3 9 +#define SAMR_M_SAMSKPROG3 1 << SAMR_V_SAMSKPROG3 +#define SAMR_V_SAMSKEACT0 12 +#define SAMR_M_SAMSKEACT0 1 << SAMR_V_SAMSKEACT0 +#define SAMR_V_SAMSKEACT1 13 +#define SAMR_M_SAMSKEACT1 1 << SAMR_V_SAMSKEACT1 +#define SAMR_V_SAMSKEACT2 14 +#define SAMR_M_SAMSKEACT2 1 << SAMR_V_SAMSKEACT2 +#define SAMR_V_SAMSKEACT3 15 +#define SAMR_M_SAMSKEACT3 1 << SAMR_V_SAMSKEACT3 + +/* +** +** Additional Activity Source Register (AASR) - Index 0x01A +** +** Loc Size Name Function +** ----- ---- ---- --------------------------------- +** <0> 1 WAKE0ACTV WAKE0 Active +** <1> 1 WAKE1ACTV WAKE1 Active +** <2> 1 INTRACTV Interrupt Active +** <4> 1 DZTO Doze Time-out Status +** <5> 1 SLPTO Sleep Time-out Status +** <6> 1 SPNDTO Suspend Time-out Status +** <7> 1 GENTO Generic Timer Time-out Status +** <8> 1 PRTMR0TO Programmable Timer 0 Time-out Status +** <9> 1 PRTMR1TO Programmable Timer 1 Time-out Status +** <10> 1 PRTMR2TO Programmable Timer 2 Time-out Status +** <11> 1 PRTMR3TO Programmable Timer 3 Time-out Status +** <12> 1 PRTOPMI0 Programmable Timer 0 PMI Flag +** <13> 1 PRTOPMI1 Programmable Timer 1 PMI Flag +** <14> 1 PRTOPMI2 Programmable Timer 2 PMI Flag +** <15> 1 PRTOPMI3 Programmable Timer 3 PMI Flag +** +** <3> Reserved +** +*/ +#define PMC_AASR_REG 0x01A +#define PMC_AASR_INIT 0x0000 +#define AASR_V_WAKE0ACTV 0 +#define AASR_M_WAKE0ACTV 1 << AASR_V_WAKE0ACTV +#define AASR_V_WAKE1ACTV 1 +#define AASR_M_WAKE1ACTV 1 << AASR_V_WAKE1ACTV +#define AASR_V_INTRACTV 2 +#define AASR_M_INTRACTV 1 << AASR_V_INTRACTV +#define AASR_V_DZTO 4 +#define AASR_M_DZTO 1 << AASR_V_DZTO +#define AASR_V_SLPTO 5 +#define AASR_M_SLPTO 1 << AASR_V_SLPTO +#define AASR_V_SPNDTO 6 +#define AASR_M_SPNDTO 1 << AASR_V_SPNDTO +#define AASR_V_GENTO 7 +#define AASR_M_GENTO 1 << AASR_V_GENTO +#define AASR_V_PRTMR0TO 8 +#define AASR_M_PRTMR0TO 1 << AASR_V_PRTMR0TO +#define AASR_V_PRTMR1TO 9 +#define AASR_M_PRTMR1TO 1 << AASR_V_PRTMR0T1 +#define AASR_V_PRTMR2TO 10 +#define AASR_M_PRTMR2TO 1 << AASR_V_PRTMR0T2 +#define AASR_V_PRTMR3TO 11 +#define AASR_M_PRTMR3TO 1 << AASR_V_PRTMR0T3 +#define AASR_V_PRTOPMI0 12 +#define AASR_M_PRTOPMI0 1 << AASR_V_PRTOPMI0 +#define AASR_V_PRTOPMI1 13 +#define AASR_M_PRTOPMI1 1 << AASR_V_PRTOPMI1 +#define AASR_V_PRTOPMI2 14 +#define AASR_M_PRTOPMI2 1 << AASR_V_PRTOPMI2 +#define AASR_V_PRTOPMI3 15 +#define AASR_M_PRTOPMI3 1 << AASR_V_PRTOPMI3 + +/* +** +** Additional Primary Activity Mask Register (APAMR) - Index 0x01B +** +** Loc Size Name Function +** ----- ---- ---- --------------------------------- +** <0> 1 PAMSKWAKE0 Primary Activity Mask WAKE0 +** <1> 1 PAMSKWAKE1 Primary Activity Mask WAKE1 +** <2> 1 PAMSKINTR Primary Activity Mask INTR +** <3> 1 PAMSKPMI Primary Activity Mask PMI +** <4> 1 PAMSKHOLD Primary Activity Mask HOLD Request +** <5> 1 PAMSKNMI Primary Activity Mask NMI +** <6> 1 PAMSKDMA Primary Activity Mask DMA +** <7> 1 PAMSKMSTR Primary Activity Mask MASTER +** <11> 1 DISPACTVON Disable Primary Activity On +** <14> 1 HD2EN Hard Disk Secondar Enable +** <15> 1 LMTPACTV Limited Primary Activity PMI +** +** <8:10><12:13> Reserved +** +*/ +#define PMC_APAMR_REG 0x01B +#define PMC_APAMR_INIT ( APAMR_M_PAMSKWAKE0 | APAMR_M_PAMSKWAKE1 | \ + APAMR_M_PAMSKINTR | APAMR_M_PAMSKPMI | \ + APAMR_M_PAMSKHOLD | APAMR_M_PAMSKNMI | \ + APAMR_M_PAMSKDMA | APAMR_M_PAMSKMSTR | \ + APAMR_M_LMTPACTV ) +#define APAMR_V_PAMSKWAKE0 0 +#define APAMR_M_PAMSKWAKE0 1 << APAMR_V_PAMSKWAKE0 +#define APAMR_V_PAMSKWAKE1 1 +#define APAMR_M_PAMSKWAKE1 1 << APAMR_V_PAMSKWAKE1 +#define APAMR_V_PAMSKINTR 2 +#define APAMR_M_PAMSKINTR 1 << APAMR_V_PAMSKINTR +#define APAMR_V_PAMSKPMI 3 +#define APAMR_M_PAMSKPMI 1 << APAMR_V_PAMSKPMI +#define APAMR_V_PAMSKHOLD 4 +#define APAMR_M_PAMSKHOLD 1 << APAMR_V_PAMSKHOLD +#define APAMR_V_PAMSKNMI 5 +#define APAMR_M_PAMSKNMI 1 << APAMR_V_PAMSKNMI +#define APAMR_V_PAMSKDMA 6 +#define APAMR_M_PAMSKDMA 1 << APAMR_V_PAMSKDMA +#define APAMR_V_PAMSKMSTR 7 +#define APAMR_M_PAMSKMSTR 1 << APAMR_V_PAMSKMSTR +#define APAMR_V_DISPACTVON 11 +#define APAMR_M_DISPACTVON 1 << APAMR_V_DISPACTVON +#define APAMR_V_HD2EN 14 +#define APAMR_M_HD2EN 1 << APAMR_V_HD2EN +#define APAMR_V_LMTPACTV 15 +#define APAMR_M_LMTPACTV 1 << APAMR_V_LMTPACTV + +/* +** +** Additional Secondary Control Register (ASCR) - Index 0x01C +** +** Loc Size Name Function +** ----- ---- ---- --------------------------------- +** <0> 1 SAMSKWAKE0 Secondary Activity Mask WAKE0 +** <1> 1 SAMSKWAKE1 Secondary Activity Mask WAKE1 +** <2> 1 SAMSKINTR Secondary Activity Mask INTR +** <3> 1 SAMSKPMI Secondary Activity Mask PMI +** <4> 1 SAMSKIRQ0 Secondary Activity Mask IRQ0 +** <6> 1 SAMSKDMA Secondary Activity Mask DMA +** <7> 1 SAMSKMSTR Secondary Activity Mask MASTER +** <9> 1 SACTVTMR0 Secondary Activity Timer 0 +** <10> 1 SACTVTMR1 Secondary Activity Timer 1 +** <11> 1 SACTVTMR2 Secondary Activity Timer 2 +** <15> 1 LMTSACTV Limited Secondary Activity PMI +** +** <5><8><12:14> Reserved +** +*/ +#define PMC_ASCR_REG 0x01C +#define PMC_ASCR_INIT ( ASCR_M_SAMSKWAKE0 | ASCR_M_SAMSKWAKE1 | \ + ASCR_M_SAMSKINTR | ASCR_M_SAMSKPMI | \ + ASCR_M_SAMSKIRQ0 | ASCR_M_SAMSKDMA | \ + ASCR_M_SAMSKMSTR | ASCR_M_SACTVTMR2 | \ + ASCR_M_LMTSACTV ) +#define ASCR_V_SAMSKWAKE0 0 +#define ASCR_M_SAMSKWAKE0 1 << ASCR_V_SAMSKWAKE0 +#define ASCR_V_SAMSKWAKE1 1 +#define ASCR_M_SAMSKWAKE1 1 << ASCR_V_SAMSKWAKE1 +#define ASCR_V_SAMSKINTR 2 +#define ASCR_M_SAMSKINTR 1 << ASCR_V_SAMSKINTR +#define ASCR_V_SAMSKPMI 3 +#define ASCR_M_SAMSKPMI 1 << ASCR_V_SAMSKPMI +#define ASCR_V_SAMSKIRQ0 4 +#define ASCR_M_SAMSKIRQ0 1 << ASCR_V_SAMSKIRQ0 +#define ASCR_V_SAMSKDMA 6 +#define ASCR_M_SAMSKDMA 1 << ASCR_V_SAMSKDMA +#define ASCR_V_SAMSKMSTR 7 +#define ASCR_M_SAMSKMSTR 1 << ASCR_V_SAMSKMSTR +#define ASCR_V_SACTVTMR 9 +#define ASCR_M_SACTVTMR 0x7 << ASCR_V_SACTVTMR +#define ASCR_V_SACTVTMR0 9 +#define ASCR_M_SACTVTMR0 1 << ASCR_V_SACTVTMR0 +#define ASCR_V_SACTVTMR1 10 +#define ASCR_M_SACTVTMR1 1 << ASCR_V_SACTVTMR1 +#define ASCR_V_SACTVTMR2 11 +#define ASCR_M_SACTVTMR2 1 << ASCR_V_SACTVTMR2 +#define ASCR_V_LMTSACTV 15 +#define ASCR_M_LMTSACTV 1 << ASCR_V_LMTSACTV + +/* +** Secondary Activity Timer +*/ +#define SACTVTMR_125US 0x000 +#define SACTVTMR_1MS ASCR_M_SACTVTMR0 +#define SACTVTMR_2MS ASCR_M_SACTVTMR1 +#define SACTVTMR_4MS (ASCR_M_SACTVTMR0 | ASCR_M_SACTVTMR1) +#define SACTVTMR_8MS ASCR_M_SACTVTMR2 +#define SACTVTMR_16MS (ASCR_M_SACTVTMR0 | ASCR_M_SACTVTMR2) +#define SACTVTMR_32MS (ASCR_M_SACTVTMR1 | ASCR_M_SACTVTMR2) +#define SACTVTMR_64MS (ASCR_M_SACTVTMR0 | ASCR_M_SACTVTMR1 | ASCR_M_SACTVTMR2) + +/* +** +** Additional PMI Mask Register (APMIMR) - Index 0x01D +** +** Loc Size Name Function +** ----- ---- ---- --------------------------------- +** <0> 1 IMSKWAKE0 Mask WAKE0 from PMI +** <1> 1 IMSKWAKE1 Mask WAKE1 from PMI +** <3> 1 IMSKRTC Mask RTC from PMI +** <4> 1 RESCHED0 Reschedule PMI 0 +** <5> 1 RESCHED1 Reschedule PMI 1 +** <6> 1 SFTSMI Soft SMI +** <8> 1 IMSKPRTMR0TO Mask Programmable Time 0 Time-out from PMI +** <9> 1 IMSKPRTMR1TO Mask Programmable Time 1 Time-out from PMI +** <10> 1 IMSKPRTMR2TO Mask Programmable Time 2 Time-out from PMI +** <11> 1 IMSKPRTMR3TO Mask Programmable Time 3 Time-out from PMI +** +** <2><7><12:15> Reserved +** +*/ +#define PMC_APMIMR_REG 0x01D +#define PMC_APMIMR_INIT ( APMIMR_M_IMSKWAKE0 | APMIMR_M_IMSKWAKE1 | \ + APMIMR_M_IMSKRTC | APMIMR_M_IMSKPRTMR0TO| \ + APMIMR_M_IMSKPRTMR1TO | \ + APMIMR_M_IMSKPRTMR2TO | \ + APMIMR_M_IMSKPRTMR3TO ) +#define APMIMR_V_IMSKWAKE0 0 +#define APMIMR_M_IMSKWAKE0 1 << APMIMR_V_IMSKWAKE0 +#define APMIMR_V_IMSKWAKE1 1 +#define APMIMR_M_IMSKWAKE1 1 << APMIMR_V_IMSKWAKE1 +#define APMIMR_V_IMSKRTC 3 +#define APMIMR_M_IMSKRTC 1 << APMIMR_V_IMSKRTC +#define APMIMR_V_RESCHED 4 +#define APMIMR_M_RESCHED 0x3 << APMIMR_V_RESCHED +#define APMIMR_V_RESCHED0 4 +#define APMIMR_M_RESCHED0 1 << APMIMR_V_RESCHED0 +#define APMIMR_V_RESCHED1 5 +#define APMIMR_M_RESCHED1 1 << APMIMR_V_RESCHED1 +#define APMIMR_V_SFTSMI 6 +#define APMIMR_M_SFTSMI 1 << APMIMR_V_SFTSMI +#define APMIMR_V_IMSKPRTMR0TO 8 +#define APMIMR_M_IMSKPRTMR0TO 1 << APMIMR_V_IMSKPRTMR0TO +#define APMIMR_V_IMSKPRTMR1TO 9 +#define APMIMR_M_IMSKPRTMR1TO 1 << APMIMR_V_IMSKPRTMR1TO +#define APMIMR_V_IMSKPRTMR2TO 10 +#define APMIMR_M_IMSKPRTMR2TO 1 << APMIMR_V_IMSKPRTMR2TO +#define APMIMR_V_IMSKPRTMR3TO 11 +#define APMIMR_M_IMSKPRTMR3TO 1 << APMIMR_V_IMSKPRTMR3TO + +/* +** Reschedule PMI +*/ +#define RESCHED_DISABLE 0x000 +#define RESCHED_64MS APMIMR_M_RESCHED0 +#define RESCHED_1MS APMIMR_M_RESCHED1 +#define RESCHED_1S (APMIMR_M_RESCHED0 | APMIMR_M_RESCHED1) + +/* +** +** Miscellaneous Control Register (MCR) - Index 0x01E +** +** Loc Size Name Function +** ----- ---- ---- --------------------------------- +** <0> 1 PMIFLGEN PMI Flag Enable +** <1> 1 PAFLGEN Primary Activity Flag Enable +** <2> 1 SAFLGEN Secondary Activity Flag Enable +** +** <3:15> Reserved +** +*/ +#define PMC_MCR_REG 0x01E +#define PMC_MCR_INIT 0x0000 +#define MCR_V_PMIFLGEN 0 +#define MCR_M_PMIFLGEN 1 << MCR_V_PMIFLGEN +#define MCR_V_PAFLGEN 1 +#define MCR_M_PAFLGEN 1 << MCR_V_PAFLGEN +#define MCR_V_SAFLGEN 2 +#define MCR_M_SAFLGEN 1 << MCR_V_SAFLGEN + +/* +** +** SEQUOIA-1 Identification Register (SEQIDR) - Index 0x01F +** +** Loc Size Name Function +** ----- ---- ---- --------------------------------- +** <0> 1 SQ1ID0 SEQUOIA-1 Revision Number ID 0 +** <1> 1 SQ1ID1 SEQUOIA-1 Revision Number ID 1 +** <2> 1 SQ1ID2 SEQUOIA-1 Revision Number ID 2 +** <3> 1 SQ1ID3 SEQUOIA-1 Revision Number ID 3 +** +** <4:15> Reserved +** +*/ +#define PMC_SEQIDR_REG 0x01F +#define SEQIDR_V_SQ1ID 0 +#define SEQIDR_M_SQ1ID 0xF << SEQIDR_V_SQ1ID + +/* +** +** Programmable Range Address Register 0 (PRAR0) - Index 0x020 +** +** Loc Size Name Function +** ----- ---- ---- --------------------------------- +** <0> 9 PRMA PRM 0 Address +** <14> 1 PROSHDW0EN Programmable Shadow Register 0 Enable +** <15> 1 PROCS0EN Programmable Chip Select 0 Enable +** +** <10:13> Reserved +** +*/ +#define PMC_PRAR0_REG 0x020 +#define PMC_PRAR0_INIT 0x0000 +#define PRAR0_V_PRMA 0 +#define PRAR0_M_PRMA 0x3FF << PRAR0_V_PRMA +#define PRAR0_V_PROSHDW0EN 14 +#define PRAR0_M_PROSHDW0EN 1 << PRAR0_V_PROSHDW0EN +#define PRAR0_V_PROCS0EN 15 +#define PRAR0_M_PROCS0EN 1 << PRAR0_V_PROCS0EN + +/* +** +** Programmable Range Compare Register 0 (PRCR0) - Index 0x021 +** +** Loc Size Name Function +** ----- ---- ---- --------------------------------- +** <0> 1 PRMCMPEN00 PRM 0 Compare Enable 0 +** <1> 1 PRMCMPEN01 PRM 0 Compare Enable 1 +** <2> 1 PRMCMPEN02 PRM 0 Compare Enable 2 +** <3> 1 PRMCMPEN03 PRM 0 Compare Enable 3 +** <4> 1 PRMCMPEN04 PRM 0 Compare Enable 4 +** <5> 1 PRMCMPEN05 PRM 0 Compare Enable 5 +** <6> 1 PRMCMPEN06 PRM 0 Compare Enable 6 +** <7> 1 PRMCMPEN07 PRM 0 Compare Enable 7 +** <8> 1 PRMCMPEN08 PRM 0 Compare Enable 8 +** <9> 1 PRMCMPEN09 PRM 0 Compare Enable 9 +** <10> 1 PRMWR0EN PRM 0 Compare Write Enable +** <11> 1 PRMRD0EN PRM 0 Compare Read Enable +** <12> 1 PRM0MIO PRM 0 Memory or I/O Compare Enable +** <13> 1 PRM0EN PRM 0 Enable +** +** <14:15> Reserved +** +*/ +#define PMC_PRCR0_REG 0x021 +#define PMC_PRCR0_INIT 0x0000 +#define PRCR0_V_PRMCMPEN 0 +#define PRCR0_M_PRMCMPEN 0x3FF << PRCR0_V_PRMCMPEN +#define PRCR0_V_PRMCMPEN00 0 +#define PRCR0_M_PRMCMPEN00 1 << PRCR0_V_PRMCMPEN00 +#define PRCR0_V_PRMCMPEN01 1 +#define PRCR0_M_PRMCMPEN01 1 << PRCR0_V_PRMCMPEN01 +#define PRCR0_V_PRMCMPEN02 2 +#define PRCR0_M_PRMCMPEN02 1 << PRCR0_V_PRMCMPEN02 +#define PRCR0_V_PRMCMPEN03 3 +#define PRCR0_M_PRMCMPEN03 1 << PRCR0_V_PRMCMPEN03 +#define PRCR0_V_PRMCMPEN04 4 +#define PRCR0_M_PRMCMPEN04 1 << PRCR0_V_PRMCMPEN04 +#define PRCR0_V_PRMCMPEN05 5 +#define PRCR0_M_PRMCMPEN05 1 << PRCR0_V_PRMCMPEN05 +#define PRCR0_V_PRMCMPEN06 6 +#define PRCR0_M_PRMCMPEN06 1 << PRCR0_V_PRMCMPEN06 +#define PRCR0_V_PRMCMPEN07 7 +#define PRCR0_M_PRMCMPEN07 1 << PRCR0_V_PRMCMPEN07 +#define PRCR0_V_PRMCMPEN08 8 +#define PRCR0_M_PRMCMPEN08 1 << PRCR0_V_PRMCMPEN08 +#define PRCR0_V_PRMCMPEN09 9 +#define PRCR0_M_PRMCMPEN09 1 << PRCR0_V_PRMCMPEN09 +#define PRCR0_V_PRMWR0EN 10 +#define PRCR0_M_PRMWR0EN 1 << PRCR0_V_PRMWR0EN +#define PRCR0_V_PRMRD0EN 11 +#define PRCR0_M_PRMRD0EN 1 << PRCR0_V_PRMRD0EN +#define PRCR0_V_PRM0MIO 12 +#define PRCR0_M_PRM0MIO 1 << PRCR0_V_PRM0MIO +#define PRCR0_V_PRM0EN 13 +#define PRCR0_M_PRM0EN 1 << PRCR0_V_PRM0EN + +/* +** +** Programmable Range Address Register 1 (PRAR1) - Index 0x022 +** +** Loc Size Name Function +** ----- ---- ---- --------------------------------- +** <0> 9 PRMA PRM 1 Address +** <14> 1 PROSHDW1EN Programmable Shadow Register 1 Enable +** <15> 1 PROCS1EN Programmable Chip Select 1 Enable +** +** <10:13> Reserved +** +*/ +#define PMC_PRAR1_REG 0x022 +#define PRAR1_V_PRMA 0 +#define PRAR1_M_PRMA 0x3FF << PRAR1_V_PRMA +#define PRAR1_V_PROSHDW1EN 14 +#define PRAR1_M_PROSHDW1EN 1 << PRAR1_V_PROSHDW1EN +#define PRAR1_V_PROCS1EN 15 +#define PRAR1_M_PROCS1EN 1 << PRAR1_V_PROCS1EN + +/* +** +** Programmable Range Compare Register 1 (PRCR1) - Index 0x023 +** +** Loc Size Name Function +** ----- ---- ---- --------------------------------- +** <0> 1 PRMCMPEN10 PRM 1 Compare Enable 0 +** <1> 1 PRMCMPEN11 PRM 1 Compare Enable 1 +** <2> 1 PRMCMPEN12 PRM 1 Compare Enable 2 +** <3> 1 PRMCMPEN13 PRM 1 Compare Enable 3 +** <4> 1 PRMCMPEN14 PRM 1 Compare Enable 4 +** <5> 1 PRMCMPEN15 PRM 1 Compare Enable 5 +** <6> 1 PRMCMPEN16 PRM 1 Compare Enable 6 +** <7> 1 PRMCMPEN17 PRM 1 Compare Enable 7 +** <8> 1 PRMCMPEN18 PRM 1 Compare Enable 8 +** <9> 1 PRMCMPEN19 PRM 1 Compare Enable 9 +** <10> 1 PRMWR1EN PRM 1 Compare Write Enable +** <11> 1 PRMRD1EN PRM 1 Compare Read Enable +** <12> 1 PRM1MIO PRM 1 Memory or I/O Compare Enable +** <13> 1 PRM1EN PRM 1 Enable +** +** <14:15> Reserved +** +*/ +#define PMC_PRCR1_REG 0x023 +#define PMC_PRCR1_INIT 0x0000 +#define PRCR1_V_PRMCMPEN 0 +#define PRCR1_M_PRMCMPEN 0x3FF << PRCR1_V_PRMCMPEN +#define PRCR1_V_PRMCMPEN10 0 +#define PRCR1_M_PRMCMPEN10 1 << PRCR1_V_PRMCMPEN10 +#define PRCR1_V_PRMCMPEN11 1 +#define PRCR1_M_PRMCMPEN11 1 << PRCR1_V_PRMCMPEN11 +#define PRCR1_V_PRMCMPEN12 2 +#define PRCR1_M_PRMCMPEN12 1 << PRCR1_V_PRMCMPEN12 +#define PRCR1_V_PRMCMPEN13 3 +#define PRCR1_M_PRMCMPEN13 1 << PRCR1_V_PRMCMPEN13 +#define PRCR1_V_PRMCMPEN14 4 +#define PRCR1_M_PRMCMPEN14 1 << PRCR1_V_PRMCMPEN14 +#define PRCR1_V_PRMCMPEN15 5 +#define PRCR1_M_PRMCMPEN15 1 << PRCR1_V_PRMCMPEN15 +#define PRCR1_V_PRMCMPEN16 6 +#define PRCR1_M_PRMCMPEN16 1 << PRCR1_V_PRMCMPEN16 +#define PRCR1_V_PRMCMPEN17 7 +#define PRCR1_M_PRMCMPEN17 1 << PRCR1_V_PRMCMPEN17 +#define PRCR1_V_PRMCMPEN18 8 +#define PRCR1_M_PRMCMPEN18 1 << PRCR1_V_PRMCMPEN18 +#define PRCR1_V_PRMCMPEN19 9 +#define PRCR1_M_PRMCMPEN19 1 << PRCR1_V_PRMCMPEN19 +#define PRCR1_V_PRMWR1EN 10 +#define PRCR1_M_PRMWR1EN 1 << PRCR1_V_PRMWR1EN +#define PRCR1_V_PRMRD1EN 11 +#define PRCR1_M_PRMRD1EN 1 << PRCR1_V_PRMRD1EN +#define PRCR1_V_PRM1MIO 12 +#define PRCR1_M_PRM1MIO 1 << PRCR1_V_PRM1MIO +#define PRCR1_V_PRM1EN 13 +#define PRCR1_M_PRM1EN 1 << PRCR1_V_PRM1EN + +/* +** +** Programmable Range Address Register 2 (PRAR2) - Index 0x024 +** +** Loc Size Name Function +** ----- ---- ---- --------------------------------- +** <0> 9 PRMA PRM 2 Address +** <14> 1 PROSHDW2EN Programmable Shadow Register 2 Enable +** <15> 1 PROCS2EN Programmable Chip Select 2 Enable +** +** <10:13> Reserved +** +*/ +#define PMC_PRAR2_REG 0x024 +#define PRAR2_V_PRMA 0 +#define PRAR2_M_PRMA 0x3FF << PRAR2_V_PRMA +#define PRAR2_V_PROSHDW2EN 14 +#define PRAR2_M_PROSHDW2EN 1 << PRAR2_V_PROSHDW2EN +#define PRAR2_V_PROCS2EN 15 +#define PRAR2_M_PROCS2EN 1 << PRAR2_V_PROCS2EN + +/* +** +** Programmable Range Compare Register 2 (PRCR2) - Index 0x025 +** +** Loc Size Name Function +** ----- ---- ---- --------------------------------- +** <0> 1 PRMCMPEN10 PRM 2 Compare Enable 0 +** <1> 1 PRMCMPEN11 PRM 2 Compare Enable 1 +** <2> 1 PRMCMPEN12 PRM 2 Compare Enable 2 +** <3> 1 PRMCMPEN13 PRM 2 Compare Enable 3 +** <4> 1 PRMCMPEN14 PRM 2 Compare Enable 4 +** <5> 1 PRMCMPEN15 PRM 2 Compare Enable 5 +** <6> 1 PRMCMPEN16 PRM 2 Compare Enable 6 +** <7> 1 PRMCMPEN17 PRM 2 Compare Enable 7 +** <8> 1 PRMCMPEN18 PRM 2 Compare Enable 8 +** <9> 1 PRMCMPEN19 PRM 2 Compare Enable 9 +** <10> 1 PRMWR2EN PRM 2 Compare Write Enable +** <11> 1 PRMRD2EN PRM 2 Compare Read Enable +** <12> 1 PRM2MIO PRM 2 Memory or I/O Compare Enable +** <13> 1 PRM2EN PRM 2 Enable +** +** <14:15> Reserved +** +*/ +#define PMC_PRCR2_REG 0x025 +#define PMC_PRCR2_INIT 0x0000 +#define PRCR2_V_PRMCMPEN 0 +#define PRCR2_M_PRMCMPEN 0x3FF << PRCR2_V_PRMCMPEN +#define PRCR2_V_PRMCMPEN10 0 +#define PRCR2_M_PRMCMPEN10 1 << PRCR2_V_PRMCMPEN10 +#define PRCR2_V_PRMCMPEN11 1 +#define PRCR2_M_PRMCMPEN11 1 << PRCR2_V_PRMCMPEN11 +#define PRCR2_V_PRMCMPEN12 2 +#define PRCR2_M_PRMCMPEN12 1 << PRCR2_V_PRMCMPEN12 +#define PRCR2_V_PRMCMPEN13 3 +#define PRCR2_M_PRMCMPEN13 1 << PRCR2_V_PRMCMPEN13 +#define PRCR2_V_PRMCMPEN14 4 +#define PRCR2_M_PRMCMPEN14 1 << PRCR2_V_PRMCMPEN14 +#define PRCR2_V_PRMCMPEN15 5 +#define PRCR2_M_PRMCMPEN15 1 << PRCR2_V_PRMCMPEN15 +#define PRCR2_V_PRMCMPEN16 6 +#define PRCR2_M_PRMCMPEN16 1 << PRCR2_V_PRMCMPEN16 +#define PRCR2_V_PRMCMPEN17 7 +#define PRCR2_M_PRMCMPEN17 1 << PRCR2_V_PRMCMPEN17 +#define PRCR2_V_PRMCMPEN18 8 +#define PRCR2_M_PRMCMPEN18 1 << PRCR2_V_PRMCMPEN18 +#define PRCR2_V_PRMCMPEN19 9 +#define PRCR2_M_PRMCMPEN19 1 << PRCR2_V_PRMCMPEN19 +#define PRCR2_V_PRMWR2EN 10 +#define PRCR2_M_PRMWR2EN 1 << PRCR2_V_PRMWR2EN +#define PRCR2_V_PRMRD2EN 11 +#define PRCR2_M_PRMRD2EN 1 << PRCR2_V_PRMRD2EN +#define PRCR2_V_PRM2MIO 12 +#define PRCR2_M_PRM2MIO 1 << PRCR2_V_PRM2MIO +#define PRCR2_V_PRM2EN 13 +#define PRCR2_M_PRM2EN 1 << PRCR2_V_PRM2EN + +/* +** +** Programmable Range Address Register 3 (PRAR3) - Index 0x026 +** +** Loc Size Name Function +** ----- ---- ---- --------------------------------- +** <0> 9 PRMA PRM 3 Address +** <14> 1 PROSHDW3EN Programmable Shadow Register 3 Enable +** <15> 1 PROCS3EN Programmable Chip Select 3 Enable +** +** <10:13> Reserved +** +*/ +#define PMC_PRAR3_REG 0x026 +#define PMC_PRAR3_INIT 0x0000 +#define PRAR3_V_PRMA 0 +#define PRAR3_M_PRMA 0x3FF << PRAR3_V_PRMA +#define PRAR3_V_PROSHDW3EN 14 +#define PRAR3_M_PROSHDW3EN 1 << PRAR3_V_PROSHDW3EN +#define PRAR3_V_PROCS3EN 15 +#define PRAR3_M_PROCS3EN 1 << PRAR3_V_PROCS3EN + +/* +** +** Programmable Range Compare Register 3 (PRCR3) - Index 0x027 +** +** Loc Size Name Function +** ----- ---- ---- --------------------------------- +** <0> 1 PRMCMPEN10 PRM 3 Compare Enable 0 +** <1> 1 PRMCMPEN11 PRM 3 Compare Enable 1 +** <2> 1 PRMCMPEN12 PRM 3 Compare Enable 2 +** <3> 1 PRMCMPEN13 PRM 3 Compare Enable 3 +** <4> 1 PRMCMPEN14 PRM 3 Compare Enable 4 +** <5> 1 PRMCMPEN15 PRM 3 Compare Enable 5 +** <6> 1 PRMCMPEN16 PRM 3 Compare Enable 6 +** <7> 1 PRMCMPEN17 PRM 3 Compare Enable 7 +** <8> 1 PRMCMPEN18 PRM 3 Compare Enable 8 +** <9> 1 PRMCMPEN19 PRM 3 Compare Enable 9 +** <10> 1 PRMWR3EN PRM 3 Compare Write Enable +** <11> 1 PRMRD3EN PRM 3 Compare Read Enable +** <12> 1 PRM3MIO PRM 3 Memory or I/O Compare Enable +** <13> 1 PRM3EN PRM 3 Enable +** +** <14:15> Reserved +** +*/ +#define PMC_PRCR3_REG 0x027 +#define PMC_PRCR3_INIT 0x0000 +#define PRCR3_V_PRMCMPEN 0 +#define PRCR3_M_PRMCMPEN 0x3FF << PRCR3_V_PRMCMPEN +#define PRCR3_V_PRMCMPEN10 0 +#define PRCR3_M_PRMCMPEN10 1 << PRCR3_V_PRMCMPEN10 +#define PRCR3_V_PRMCMPEN11 1 +#define PRCR3_M_PRMCMPEN11 1 << PRCR3_V_PRMCMPEN11 +#define PRCR3_V_PRMCMPEN12 2 +#define PRCR3_M_PRMCMPEN12 1 << PRCR3_V_PRMCMPEN12 +#define PRCR3_V_PRMCMPEN13 3 +#define PRCR3_M_PRMCMPEN13 1 << PRCR3_V_PRMCMPEN13 +#define PRCR3_V_PRMCMPEN14 4 +#define PRCR3_M_PRMCMPEN14 1 << PRCR3_V_PRMCMPEN14 +#define PRCR3_V_PRMCMPEN15 5 +#define PRCR3_M_PRMCMPEN15 1 << PRCR3_V_PRMCMPEN15 +#define PRCR3_V_PRMCMPEN16 6 +#define PRCR3_M_PRMCMPEN16 1 << PRCR3_V_PRMCMPEN16 +#define PRCR3_V_PRMCMPEN17 7 +#define PRCR3_M_PRMCMPEN17 1 << PRCR3_V_PRMCMPEN17 +#define PRCR3_V_PRMCMPEN18 8 +#define PRCR3_M_PRMCMPEN18 1 << PRCR3_V_PRMCMPEN18 +#define PRCR3_V_PRMCMPEN19 9 +#define PRCR3_M_PRMCMPEN19 1 << PRCR3_V_PRMCMPEN19 +#define PRCR3_V_PRMWR3EN 10 +#define PRCR3_M_PRMWR3EN 1 << PRCR3_V_PRMWR3EN +#define PRCR3_V_PRMRD3EN 11 +#define PRCR3_M_PRMRD3EN 1 << PRCR3_V_PRMRD3EN +#define PRCR3_V_PRM3MIO 12 +#define PRCR3_M_PRM3MIO 1 << PRCR3_V_PRM3MIO +#define PRCR3_V_PRM3EN 13 +#define PRCR3_M_PRM3EN 1 << PRCR3_V_PRM3EN + +/* +** +** Programmable Time-out Timer Register 0 (PTOTR0) - Index 0x028 +** +** Loc Size Name Function +** ----- ---- ---- --------------------------------- +** <0> 1 PROGTMR00 Programmable Time-out Timer 0 0 +** <1> 1 PROGTMR01 Programmable Time-out Timer 0 1 +** <2> 1 PROGTMR02 Programmable Time-out Timer 0 2 +** <3> 1 PROGTMR03 Programmable Time-out Timer 0 3 +** <7> 1 TMR0SOURCE Clock Source for Timer 0 +** <14> 1 TMR0PC2EN Time-out Timer 0 to PC2 Enable +** <15> 1 TMR0EN Programmable Timer 0 Enable +** +** <4:6><8:13> Reserved +** +*/ +#define PMC_PTOTR0_REG 0x028 +#define PMC_PTOTR0_INIT 0x0000 +#define PTOTR0_V_PROGTMR0 0 +#define PTOTR0_M_PROGTMR0 0xF << PTOTR0_V_PROGTMR0 +#define PTOTR0_V_PROGTMR00 0 +#define PTOTR0_M_PROGTMR00 1 << PTOTR0_V_PROGTMR00 +#define PTOTR0_V_PROGTMR01 1 +#define PTOTR0_M_PROGTMR01 1 << PTOTR0_V_PROGTMR01 +#define PTOTR0_V_PROGTMR02 2 +#define PTOTR0_M_PROGTMR02 1 << PTOTR0_V_PROGTMR02 +#define PTOTR0_V_PROGTMR03 3 +#define PTOTR0_M_PROGTMR03 1 << PTOTR0_V_PROGTMR03 +#define PTOTR0_V_TMR0SOURCE 7 +#define PTOTR0_M_TMR0SOURCE 1 << PTOTR0_V_TMR0SOURCE +#define PTOTR0_V_TMR0PC2EN 14 +#define PTOTR0_M_TMR0PC2EN 1 << PTOTR0_V_TMR0PC2EN +#define PTOTR0_V_TMR0EN 15 +#define PTOTR0_M_TMR0EN 1 << PTOTR0_V_TMR0EN + +/* +** Progammable Time-out Timer 0 +*/ +#define PROGTMR0_2S 0x000 +#define PROGTMR0_5S PTOTR0_M_PROGTMR00 +#define PROGTMR0_10S PTOTR0_M_PROGTMR01 +#define PROGTMR0_15S (PTOTR0_M_PROGTMR00 | PTOTR0_M_PROGTMR01) +#define PROGTMR0_30S PTOTR0_M_PROGTMR02 +#define PROGTMR0_45S (PTOTR0_M_PROGTMR00 | PTOTR0_M_PROGTMR02) +#define PROGTMR0_60S (PTOTR0_M_PROGTMR01 | PTOTR0_M_PROGTMR02) +#define PROGTMR0_90S (PTOTR0_M_PROGTMR00 | PTOTR0_M_PROGTMR01 | PTOTR0_M_PROGTMR02) +#define PROGTMR0_2MIN PTOTR0_M_PROGTMR03 +#define PROGTMR0_3MIN (PTOTR0_M_PROGTMR00 | PTOTR0_M_PROGTMR03) +#define PROGTMR0_4MIN (PTOTR0_M_PROGTMR01 | PTOTR0_M_PROGTMR03) +#define PROGTMR0_6MIN (PTOTR0_M_PROGTMR00 | PTOTR0_M_PROGTMR01 | PTOTR0_M_PROGTMR03 +#define PROGTMR0_8MIN (PTOTR0_M_PROGTMR02 | PTOTR0_M_PROGTMR03) +#define PROGTMR0_10MIN (PTOTR0_M_PROGTMR00 | PTOTR0_M_PROGTMR02 | PTOTR0_M_PROGTMR03) +#define PROGTMR0_15MIN (PTOTR0_M_PROGTMR01 | PTOTR0_M_PROGTMR02 | PTOTR0_M_PROGTMR03) +#define PROGTMR0_20MIN (PTOTR0_M_PROGTMR00 | PTOTR0_M_PROGTMR01 | PTOTR0_M_PROGTMR02 | PTOTR0_M_PROGTMR03) + +/* +** +** Programmable Time-out Timer Register 1 (PTOTR1) - Index 0x029 +** +** Loc Size Name Function +** ----- ---- ---- --------------------------------- +** <0> 1 PROGTMR10 Programmable Time-out Timer 1 0 +** <1> 1 PROGTMR11 Programmable Time-out Timer 1 1 +** <2> 1 PROGTMR12 Programmable Time-out Timer 1 2 +** <3> 1 PROGTMR13 Programmable Time-out Timer 1 3 +** <7> 1 TMR1SOURCE Clock Source for Timer 1 +** <14> 1 TMR1PC3EN Time-out Timer 1 to PC3 Enable +** <15> 1 TMR1EN Programmable Timer 1 Enable +** +** <4:6><8:13> Reserved +** +*/ +#define PMC_PTOTR1_REG 0x029 +#define PMC_PTOTR1_INIT 0x0000 +#define PTOTR1_V_PROGTMR1 0 +#define PTOTR1_M_PROGTMR1 0xF << PTOTR1_V_PROGTMR1 +#define PTOTR1_V_PROGTMR10 0 +#define PTOTR1_M_PROGTMR10 1 << PTOTR1_V_PROGTMR10 +#define PTOTR1_V_PROGTMR11 1 +#define PTOTR1_M_PROGTMR11 1 << PTOTR1_V_PROGTMR11 +#define PTOTR1_V_PROGTMR12 2 +#define PTOTR1_M_PROGTMR12 1 << PTOTR1_V_PROGTMR12 +#define PTOTR1_V_PROGTMR13 3 +#define PTOTR1_M_PROGTMR13 1 << PTOTR1_V_PROGTMR13 +#define PTOTR1_V_TMR1SOURCE 7 +#define PTOTR1_M_TMR1SOURCE 1 << PTOTR1_V_TMR1SOURCE +#define PTOTR1_V_TMR1PC3EN 14 +#define PTOTR1_M_TMR1PC3EN 1 << PTOTR1_V_TMR1PC3EN +#define PTOTR1_V_TMR1EN 15 +#define PTOTR1_M_TMR1EN 1 << PTOTR1_V_TMR1EN + +/* +** Progammable Time-out Timer 1 +*/ +#define PROGTMR1_2S 0x000 +#define PROGTMR1_5S PTOTR1_M_PROGTMR10 +#define PROGTMR1_10S PTOTR1_M_PROGTMR11 +#define PROGTMR1_15S (PTOTR1_M_PROGTMR10 | PTOTR1_M_PROGTMR11) +#define PROGTMR1_30S PTOTR1_M_PROGTMR12 +#define PROGTMR1_45S (PTOTR1_M_PROGTMR10 | PTOTR1_M_PROGTMR12) +#define PROGTMR1_60S (PTOTR1_M_PROGTMR11 | PTOTR1_M_PROGTMR12) +#define PROGTMR1_90S (PTOTR1_M_PROGTMR10 | PTOTR1_M_PROGTMR11 | PTOTR1_M_PROGTMR12) +#define PROGTMR1_2MIN PTOTR1_M_PROGTMR13 +#define PROGTMR1_3MIN (PTOTR1_M_PROGTMR10 | PTOTR1_M_PROGTMR13) +#define PROGTMR1_4MIN (PTOTR1_M_PROGTMR11 | PTOTR1_M_PROGTMR13) +#define PROGTMR1_6MIN (PTOTR1_M_PROGTMR10 | PTOTR1_M_PROGTMR11 | PTOTR1_M_PROGTMR13 +#define PROGTMR1_8MIN (PTOTR1_M_PROGTMR12 | PTOTR1_M_PROGTMR13) +#define PROGTMR1_10MIN (PTOTR1_M_PROGTMR10 | PTOTR1_M_PROGTMR12 | PTOTR1_M_PROGTMR13) +#define PROGTMR1_15MIN (PTOTR1_M_PROGTMR11 | PTOTR1_M_PROGTMR12 | PTOTR1_M_PROGTMR13) +#define PROGTMR1_20MIN (PTOTR1_M_PROGTMR10 | PTOTR1_M_PROGTMR11 | PTOTR1_M_PROGTMR12 | PTOTR0_M_PROGTMR13) + +/* +** +** Programmable Time-out Timer Register 2 (PTOTR2) - Index 0x02A +** +** Loc Size Name Function +** ----- ---- ---- --------------------------------- +** <0> 1 PROGTMR20 Programmable Time-out Timer 2 0 +** <1> 1 PROGTMR21 Programmable Time-out Timer 2 1 +** <2> 1 PROGTMR22 Programmable Time-out Timer 2 2 +** <3> 1 PROGTMR23 Programmable Time-out Timer 2 3 +** <7> 1 TMR2SOURCE Clock Source for Timer 2 +** <14> 1 TMR2PC8EN Time-out Timer 2 to PC8 Enable +** <15> 1 TMR2EN Programmable Timer 2 Enable +** +** <4:6><8:13> Reserved +** +*/ +#define PMC_PTOTR2_REG 0x02A +#define PMC_PTOTR2_INIT 0x0000 +#define PTOTR2_V_PROGTMR2 0 +#define PTOTR2_M_PROGTMR2 0xF << PTOTR2_V_PROGTMR2 +#define PTOTR2_V_PROGTMR20 0 +#define PTOTR2_M_PROGTMR20 1 << PTOTR2_V_PROGTMR20 +#define PTOTR2_V_PROGTMR21 1 +#define PTOTR2_M_PROGTMR21 1 << PTOTR2_V_PROGTMR21 +#define PTOTR2_V_PROGTMR22 2 +#define PTOTR2_M_PROGTMR22 1 << PTOTR2_V_PROGTMR22 +#define PTOTR2_V_PROGTMR23 3 +#define PTOTR2_M_PROGTMR23 1 << PTOTR2_V_PROGTMR23 +#define PTOTR2_V_TMR2SOURCE 7 +#define PTOTR2_M_TMR2SOURCE 1 << PTOTR2_V_TMR2SOURCE +#define PTOTR2_V_TMR2PC8EN 14 +#define PTOTR2_M_TMR2PC8EN 1 << PTOTR2_V_TMR2PC8EN +#define PTOTR2_V_TMR2EN 15 +#define PTOTR2_M_TMR2EN 1 << PTOTR2_V_TMR2EN + +/* +** Progammable Time-out Timer 2 +*/ +#define PROGTMR2_2S 0x000 +#define PROGTMR2_5S PTOTR2_M_PROGTMR20 +#define PROGTMR2_10S PTOTR2_M_PROGTMR21 +#define PROGTMR2_15S (PTOTR2_M_PROGTMR20 | PTOTR2_M_PROGTMR21) +#define PROGTMR2_30S PTOTR2_M_PROGTMR22 +#define PROGTMR2_45S (PTOTR2_M_PROGTMR20 | PTOTR2_M_PROGTMR22) +#define PROGTMR2_60S (PTOTR2_M_PROGTMR21 | PTOTR2_M_PROGTMR22) +#define PROGTMR2_90S (PTOTR2_M_PROGTMR20 | PTOTR2_M_PROGTMR21 | PTOTR2_M_PROGTMR22) +#define PROGTMR2_2MIN PTOTR2_M_PROGTMR23 +#define PROGTMR2_3MIN (PTOTR2_M_PROGTMR20 | PTOTR2_M_PROGTMR23) +#define PROGTMR2_4MIN (PTOTR2_M_PROGTMR21 | PTOTR2_M_PROGTMR23) +#define PROGTMR2_6MIN (PTOTR2_M_PROGTMR20 | PTOTR2_M_PROGTMR21 | PTOTR2_M_PROGTMR23 +#define PROGTMR2_8MIN (PTOTR2_M_PROGTMR22 | PTOTR2_M_PROGTMR23) +#define PROGTMR2_10MIN (PTOTR2_M_PROGTMR20 | PTOTR2_M_PROGTMR22 | PTOTR2_M_PROGTMR23) +#define PROGTMR2_15MIN (PTOTR2_M_PROGTMR21 | PTOTR2_M_PROGTMR22 | PTOTR2_M_PROGTMR23) +#define PROGTMR2_20MIN (PTOTR2_M_PROGTMR20 | PTOTR2_M_PROGTMR21 | PTOTR2_M_PROGTMR22 | PTOTR0_M_PROGTMR23) + +/* +** +** Programmable Time-out Timer Register 3 (PTOTR3) - Index 0x02B +** +** Loc Size Name Function +** ----- ---- ---- --------------------------------- +** <0> 1 PROGTMR30 Programmable Time-out Timer 3 0 +** <1> 1 PROGTMR31 Programmable Time-out Timer 3 1 +** <2> 1 PROGTMR32 Programmable Time-out Timer 3 2 +** <3> 1 PROGTMR33 Programmable Time-out Timer 3 3 +** <7> 1 TMR3SOURCE Clock Source for Timer 3 +** <14> 1 TMR3PC9EN Time-out Timer 3 to PC9 Enable +** <15> 1 TMR3EN Programmable Timer 3 Enable +** +** <4:6><8:13> Reserved +** +*/ +#define PMC_PTOTR3_REG 0x02B +#define PMC_PTOTR3_INIT 0x0000 +#define PTOTR3_V_PROGTMR3 0 +#define PTOTR3_M_PROGTMR3 0xF << PTOTR3_V_PROGTMR3 +#define PTOTR3_V_PROGTMR30 0 +#define PTOTR3_M_PROGTMR30 1 << PTOTR3_V_PROGTMR30 +#define PTOTR3_V_PROGTMR31 1 +#define PTOTR3_M_PROGTMR31 1 << PTOTR3_V_PROGTMR31 +#define PTOTR3_V_PROGTMR32 2 +#define PTOTR3_M_PROGTMR32 1 << PTOTR3_V_PROGTMR32 +#define PTOTR3_V_PROGTMR33 3 +#define PTOTR3_M_PROGTMR33 1 << PTOTR3_V_PROGTMR33 +#define PTOTR3_V_TMR3SOURCE 7 +#define PTOTR3_M_TMR3SOURCE 1 << PTOTR3_V_TMR3SOURCE +#define PTOTR3_V_TMR3PC9EN 14 +#define PTOTR3_M_TMR3PC9EN 1 << PTOTR3_V_TMR3PC9EN +#define PTOTR3_V_TMR3EN 15 +#define PTOTR3_M_TMR3EN 1 << PTOTR3_V_TMR3EN + +/* +** Progammable Time-out Timer 3 +*/ +#define PROGTMR3_2S 0x000 +#define PROGTMR3_5S PTOTR3_M_PROGTMR30 +#define PROGTMR3_10S PTOTR3_M_PROGTMR31 +#define PROGTMR3_15S (PTOTR3_M_PROGTMR30 | PTOTR3_M_PROGTMR31) +#define PROGTMR3_30S PTOTR3_M_PROGTMR32 +#define PROGTMR3_45S (PTOTR3_M_PROGTMR30 | PTOTR3_M_PROGTMR32) +#define PROGTMR3_60S (PTOTR3_M_PROGTMR31 | PTOTR3_M_PROGTMR32) +#define PROGTMR3_90S (PTOTR3_M_PROGTMR30 | PTOTR3_M_PROGTMR31 | PTOTR3_M_PROGTMR32) +#define PROGTMR3_2MIN PTOTR3_M_PROGTMR33 +#define PROGTMR3_3MIN (PTOTR3_M_PROGTMR30 | PTOTR3_M_PROGTMR33) +#define PROGTMR3_4MIN (PTOTR3_M_PROGTMR31 | PTOTR3_M_PROGTMR33) +#define PROGTMR3_6MIN (PTOTR3_M_PROGTMR30 | PTOTR3_M_PROGTMR31 | PTOTR3_M_PROGTMR33 +#define PROGTMR3_8MIN (PTOTR3_M_PROGTMR32 | PTOTR3_M_PROGTMR33) +#define PROGTMR3_10MIN (PTOTR3_M_PROGTMR30 | PTOTR3_M_PROGTMR32 | PTOTR3_M_PROGTMR33) +#define PROGTMR3_15MIN (PTOTR3_M_PROGTMR31 | PTOTR3_M_PROGTMR32 | PTOTR3_M_PROGTMR33) +#define PROGTMR3_20MIN (PTOTR3_M_PROGTMR30 | PTOTR3_M_PROGTMR31 | PTOTR3_M_PROGTMR32 | PTOTR0_M_PROGTMR33) + +/* +** +** Programmable Time-out Timer Source Register 1 (PTOTSR1) - Index 0x02C +** +** Loc Size Name Function +** ----- ---- ---- --------------------------------- +** <0> 1 VDTMRSEL0 Video Activity Time-out Timer Select 0 +** <1> 1 VDTMRSEL1 Video Activity Time-out Timer Select 1 +** <3> 1 VDTMRSELEN Video Activity Time-out Timer Select Enable +** <4> 1 HDTMRSEL0 Hard Drive Activity Time-out Timer Select 0 +** <5> 1 HDTMRSEL1 Hard Drive Activity Time-out Timer Select 1 +** <7> 1 HDTMRSELEN Hard Drive Activity Time-out Timer Select Enable +** <8> 1 FDTMRSEL0 Floppy Drive Activity Time-out Timer Select 0 +** <9> 1 FDTMRSEL1 Floppy Drive Activity Time-out Timer Select 1 +** <11> 1 FDTMRSELEN Floppy Drive Activity Time-out Timer Select Enable +** <12> 1 KBTMRSEL0 Keyboard Activity Time-out Timer Select 0 +** <13> 1 KBTMRSEL1 Keyboard Activity Time-out Timer Select 1 +** <15> 1 KBTMRSELEN Keyboard Activity Time-out Timer Select Enable +** +** <2><6><10><14> Reserved +** +*/ +#define PMC_PTOTSR1_REG 0x02C +#define PMC_PTOTSR1_INIT 0x0000 +#define PTOTSR1_V_VDTMRSEL 0 +#define PTOTSR1_M_VDTMRSEL 0x3 << PTOTSR1_V_VDTMRSEL +#define PTOTSR1_V_VDTMRSEL0 0 +#define PTOTSR1_M_VDTMRSEL0 1 << PTOTSR1_V_VDTMRSEL0 +#define PTOTSR1_V_VDTMRSEL1 1 +#define PTOTSR1_M_VDTMRSEL1 1 << PTOTSR1_V_VDTMRSEL1 +#define PTOTSR1_V_VDTMRSELEN 3 +#define PTOTSR1_M_VDTMRSELEN 1 << PTOTSR1_V_VDTMRSELEN +#define PTOTSR1_V_HDTMRSEL 4 +#define PTOTSR1_M_HDTMRSEL 0x3 << PTOTSR1_V_HDTMRSEL +#define PTOTSR1_V_HDTMRSEL0 4 +#define PTOTSR1_M_HDTMRSEL0 1 << PTOTSR1_V_HDTMRSEL0 +#define PTOTSR1_V_HDTMRSEL1 5 +#define PTOTSR1_M_HDTMRSEL1 1 << PTOTSR1_V_HDTMRSEL1 +#define PTOTSR1_V_HDTMRSELEN 7 +#define PTOTSR1_M_HDTMRSELEN 1 << PTOTSR1_V_HDTMRSELEN +#define PTOTSR1_V_FDTMRSEL 8 +#define PTOTSR1_M_FDTMRSEL 0x3 << PTOTSR1_V_FDTMRSEL +#define PTOTSR1_V_FDTMRSEL0 8 +#define PTOTSR1_M_FDTMRSEL0 1 << PTOTSR1_V_FDTMRSEL0 +#define PTOTSR1_V_FDTMRSEL1 9 +#define PTOTSR1_M_FDTMRSEL1 1 << PTOTSR1_V_FDTMRSEL1 +#define PTOTSR1_V_FDTMRSELEN 11 +#define PTOTSR1_M_FDTMRSELEN 1 << PTOTSR1_V_FDTMRSELEN +#define PTOTSR1_V_KBTMRSEL 12 +#define PTOTSR1_M_KBTMRSEL 0x3 << PTOTSR1_V_KBTMRSEL +#define PTOTSR1_V_KBTMRSEL0 12 +#define PTOTSR1_M_KBTMRSEL0 1 << PTOTSR1_V_KBTMRSEL0 +#define PTOTSR1_V_KBTMRSEL1 13 +#define PTOTSR1_M_KBTMRSEL1 1 << PTOTSR1_V_KBTMRSEL1 +#define PTOTSR1_V_KBTMRSELEN 15 +#define PTOTSR1_M_KBTMRSELEN 1 << PTOTSR1_V_KBTMRSELEN + +/* +** Video Activity Progammable Time-out Timer +*/ +#define VDTMRSEL_0 0x000 +#define VDTMRSEL_1 PTOTSR1_M_VDTMRSEL0 +#define VDTMRSEL_2 PTOTSR1_M_VDTMRSEL1 +#define VDTMRSEL_3 (PTOTSR1_M_VDTMRSEL0 | PTOTSR1_M_VDTMRSEL1) + +/* +** Hard Drive Activity Progammable Time-out Timer +*/ +#define HDTMRSEL_0 0x000 +#define HDTMRSEL_1 PTOTSR1_M_HDTMRSEL0 +#define HDTMRSEL_2 PTOTSR1_M_HDTMRSEL1 +#define HDTMRSEL_3 (PTOTSR1_M_HDTMRSEL0 | PTOTSR1_M_HDTMRSEL1) + +/* +** Floppy Drive Activity Progammable Time-out Timer +*/ +#define FDTMRSEL_0 0x000 +#define FDTMRSEL_1 PTOTSR1_M_FDTMRSEL0 +#define FDTMRSEL_2 PTOTSR1_M_FDTMRSEL1 +#define FDTMRSEL_3 (PTOTSR1_M_FDTMRSEL0 | PTOTSR1_M_FDTMRSEL1) + +/* +** Keyboard Activity Progammable Time-out Timer +*/ +#define KBTMRSEL_0 0x000 +#define KBTMRSEL_1 PTOTSR1_M_KBTMRSEL0 +#define KBTMRSEL_2 PTOTSR1_M_KBTMRSEL1 +#define KBTMRSEL_3 (PTOTSR1_M_KBTMRSEL0 | PTOTSR1_M_KBTMRSEL1) + +/* +** +** Programmable Time-out Timer Source Register 2 (PTOTSR2) - Index 0x02D +** +** Loc Size Name Function +** ----- ---- ---- --------------------------------- +** <0> 1 SIOTMRSEL0 Serial Port Activity Time-out Timer Select 0 +** <1> 1 SIOTMRSEL1 Serial Port Activity Time-out Timer Select 1 +** <3> 1 SIOTMRSELEN Serial Port Activity Time-out Timer Select Enable +** <4> 1 PIOTMRSEL0 Parallel Port Activity Time-out Timer Select 0 +** <5> 1 PIOTMRSEL1 Parallel Port Activity Time-out Timer Select 1 +** <7> 1 PIOTMRSELEN Parallel Port Activity Time-out Timer Select Enable +** <8> 1 PR0TMRSEL0 PRM 0 Activity Time-out Timer Select 0 +** <9> 1 PR0TMRSEL1 PRM 0 Activity Time-out Timer Select 1 +** <11> 1 PR0TMRSELEN PRM 0 Activity Time-out Timer Select Enable +** <12> 1 PR1TMRSEL0 PRM 1 Activity Time-out Timer Select 0 +** <13> 1 PR1TMRSEL1 PRM 1 Activity Time-out Timer Select 1 +** <15> 1 PR1TMRSELEN PRM 1 Activity Time-out Timer Select Enable +** +** <2><6><10><14> Reserved +** +*/ +#define PMC_PTOTSR2_REG 0x02D +#define PMC_PTOTSR2_INIT 0x0000 +#define PTOTSR2_V_SIOTMRSEL 0 +#define PTOTSR2_M_SIOTMRSEL 0x3 << PTOTSR2_V_SIOTMRSEL +#define PTOTSR2_V_SIOTMRSEL0 0 +#define PTOTSR2_M_SIOTMRSEL0 1 << PTOTSR2_V_SIOTMRSEL0 +#define PTOTSR2_V_SIOTMRSEL1 1 +#define PTOTSR2_M_SIOTMRSEL1 1 << PTOTSR2_V_SIOTMRSEL1 +#define PTOTSR2_V_SIOTMRSELEN 3 +#define PTOTSR2_M_SIOTMRSELEN 1 << PTOTSR2_V_SIOTMRSELEN +#define PTOTSR2_V_PIOTMRSEL 4 +#define PTOTSR2_M_PIOTMRSEL 0x3 << PTOTSR2_V_PIOTMRSEL +#define PTOTSR2_V_PIOTMRSEL0 4 +#define PTOTSR2_M_PIOTMRSEL0 1 << PTOTSR2_V_PIOTMRSEL0 +#define PTOTSR2_V_PIOTMRSEL1 5 +#define PTOTSR2_M_PIOTMRSEL1 1 << PTOTSR2_V_PIOTMRSEL1 +#define PTOTSR2_V_PIOTMRSELEN 7 +#define PTOTSR2_M_PIOTMRSELEN 1 << PTOTSR2_V_PIOTMRSELEN +#define PTOTSR2_V_PR0TMRSEL 8 +#define PTOTSR2_M_PR0TMRSEL 0x3 << PTOTSR2_V_PR0TMRSEL +#define PTOTSR2_V_PR0TMRSEL0 8 +#define PTOTSR2_M_PR0TMRSEL0 1 << PTOTSR2_V_PR0TMRSEL0 +#define PTOTSR2_V_PR0TMRSEL1 9 +#define PTOTSR2_M_PR0TMRSEL1 1 << PTOTSR2_V_PR0TMRSEL1 +#define PTOTSR2_V_PR0TMRSELEN 11 +#define PTOTSR2_M_PR0TMRSELEN 1 << PTOTSR2_V_PR0TMRSELEN +#define PTOTSR2_V_PR1TMRSEL 12 +#define PTOTSR2_M_PR1TMRSEL 0x3 << PTOTSR2_V_PR1TMRSEL +#define PTOTSR2_V_PR1TMRSEL0 12 +#define PTOTSR2_M_PR1TMRSEL0 1 << PTOTSR2_V_PR1TMRSEL0 +#define PTOTSR2_V_PR1TMRSEL1 13 +#define PTOTSR2_M_PR1TMRSEL1 1 << PTOTSR2_V_PR1TMRSEL1 +#define PTOTSR2_V_PR1TMRSELEN 15 +#define PTOTSR2_M_PR1TMRSELEN 1 << PTOTSR2_V_PR1TMRSELEN + +/* +** Serial Port Activity Progammable Time-out Timer +*/ +#define SIOTMRSEL_0 0x000 +#define SIOTMRSEL_1 PTOTSR2_M_SIOTMRSEL0 +#define SIOTMRSEL_2 PTOTSR2_M_SIOTMRSEL1 +#define SIOTMRSEL_3 (PTOTSR2_M_SIOTMRSEL0 | PTOTSR2_M_SIOTMRSEL1) + +/* +** Parallel Port Activity Progammable Time-out Timer +*/ +#define PIOTMRSEL_0 0x000 +#define PIOTMRSEL_1 PTOTSR2_M_PIOTMRSEL0 +#define PIOTMRSEL_2 PTOTSR2_M_PIOTMRSEL1 +#define PIOTMRSEL_3 (PTOTSR2_M_PIOTMRSEL0 | PTOTSR2_M_PIOTMRSEL1) + +/* +** PRM 0 Activity Progammable Time-out Timer +*/ +#define PR0TMRSEL_0 0x000 +#define PR0TMRSEL_1 PTOTSR2_M_PR0TMRSEL0 +#define PR0TMRSEL_2 PTOTSR2_M_PR0TMRSEL1 +#define PR0TMRSEL_3 (PTOTSR2_M_PR0TMRSEL0 | PTOTSR2_M_PR0TMRSEL1) + +/* +** PRM 1 Activity Progammable Time-out Timer +*/ +#define PR1TMRSEL_0 0x000 +#define PR1TMRSEL_1 PTOTSR2_M_PR1TMRSEL0 +#define PR1TMRSEL_2 PTOTSR2_M_PR1TMRSEL1 +#define PR1TMRSEL_3 (PTOTSR2_M_PR1TMRSEL0 | PTOTSR2_M_PR1TMRSEL1) + +/* +** +** Programmable Time-out Timer Source Register 3 (PTOTSR3) - Index 0x02E +** +** Loc Size Name Function +** ----- ---- ---- --------------------------------- +** <0> 1 PR2TMRSEL0 PRM 2 Activity Time-out Timer Select 0 +** <1> 1 PR2TMRSEL1 PRM 2 Activity Time-out Timer Select 1 +** <3> 1 PR2TMRSELEN PRM 2 Activity Time-out Timer Select Enable +** <4> 1 PR3TMRSEL0 PRM 3 Activity Time-out Timer Select 0 +** <5> 1 PR3TMRSEL1 PRM 3 Activity Time-out Timer Select 1 +** <7> 1 PR3TMRSELEN PRM 3 Activity Time-out Timer Select Enable +** +** <2><6><8:15> Reserved +** +*/ +#define PMC_PTOTSR3_REG 0x02E +#define PMC_PTOTSR3_INIT 0x0000 +#define PTOTSR3_V_PR2TMRSEL 0 +#define PTOTSR3_M_PR2TMRSEL 0x3 << PTOTSR3_V_PR2TMRSEL +#define PTOTSR3_V_PR2TMRSEL0 0 +#define PTOTSR3_M_PR2TMRSEL0 1 << PTOTSR3_V_PR2TMRSEL0 +#define PTOTSR3_V_PR2TMRSEL1 1 +#define PTOTSR3_M_PR2TMRSEL1 1 << PTOTSR3_V_PR2TMRSEL1 +#define PTOTSR3_V_PR2TMRSELEN 3 +#define PTOTSR3_M_PR2TMRSELEN 1 << PTOTSR3_V_PR2TMRSELEN +#define PTOTSR3_V_PR3TMRSEL 4 +#define PTOTSR3_M_PR3TMRSEL 0x3 << PTOTSR3_V_PR3TMRSEL +#define PTOTSR3_V_PR3TMRSEL0 4 +#define PTOTSR3_M_PR3TMRSEL0 1 << PTOTSR3_V_PR3TMRSEL0 +#define PTOTSR3_V_PR3TMRSEL1 5 +#define PTOTSR3_M_PR3TMRSEL1 1 << PTOTSR3_V_PR3TMRSEL1 +#define PTOTSR3_V_PR3TMRSELEN 7 +#define PTOTSR3_M_PR3TMRSELEN 1 << PTOTSR3_V_PR3TMRSELEN + +/* +** PRM 2 Activity Progammable Time-out Timer +*/ +#define PR2TMRSEL_0 0x000 +#define PR2TMRSEL_1 PTOTSR3_M_PR2TMRSEL0 +#define PR2TMRSEL_2 PTOTSR3_M_PR2TMRSEL1 +#define PR2TMRSEL_3 (PTOTSR3_M_PR2TMRSEL0 | PTOTSR3_M_PR2TMRSEL1) + +/* +** PRM 3 Activity Progammable Time-out Timer +*/ +#define PR3TMRSEL_0 0x000 +#define PR3TMRSEL_1 PTOTSR3_M_PR3TMRSEL0 +#define PR3TMRSEL_2 PTOTSR3_M_PR3TMRSEL1 +#define PR3TMRSEL_3 (PTOTSR3_M_PR3TMRSEL0 | PTOTSR3_M_PR3TMRSEL1) + +/* +** +** Programmable Time-out Timer Source Register 4 (PTOTSR4) - Index 0x02F +** +** Loc Size Name Function +** ----- ---- ---- --------------------------------- +** <0> 1 EXT0TMRSEL0 EXTACT0 Activity Time-out Timer Select 0 +** <1> 1 EXT0TMRSEL1 EXTACT0 Activity Time-out Timer Select 1 +** <3> 1 EXT0TMRSELEN EXTACT0 Activity Time-out Timer Select Enable +** <4> 1 EXT1TMRSEL0 EXTACT1 Activity Time-out Timer Select 0 +** <5> 1 EXT1TMRSEL1 EXTACT1 Activity Time-out Timer Select 1 +** <7> 1 EXT1TMRSELEN EXTACT1 Activity Time-out Timer Select Enable +** <8> 1 EXT2TMRSEL0 EXTACT2 Activity Time-out Timer Select 0 +** <9> 1 EXT2TMRSEL1 EXTACT2 Activity Time-out Timer Select 1 +** <11> 1 EXT2TMRSELEN EXTACT2 Activity Time-out Timer Select Enable +** <12> 1 EXT3TMRSEL0 EXTACT3 Activity Time-out Timer Select 0 +** <13> 1 EXT3TMRSEL1 EXTACT3 Activity Time-out Timer Select 1 +** <15> 1 EXT3TMRSELEN EXTACT3 Activity Time-out Timer Select Enable +** +** <2><6><10><14> Reserved +** +*/ +#define PMC_PTOTSR4_REG 0x02F +#define PMC_PTOTSR4_INIT 0x0000 +#define PTOTSR4_V_EXT0TMRSEL 0 +#define PTOTSR4_M_EXT0TMRSEL 0x3 << PTOTSR4_V_EXT0TMRSEL +#define PTOTSR4_V_EXT0TMRSEL0 0 +#define PTOTSR4_M_EXT0TMRSEL0 1 << PTOTSR4_V_EXT0TMRSEL0 +#define PTOTSR4_V_EXT0TMRSEL1 1 +#define PTOTSR4_M_EXT0TMRSEL1 1 << PTOTSR4_V_EXT0TMRSEL1 +#define PTOTSR4_V_EXT0TMRSELEN 3 +#define PTOTSR4_M_EXT0TMRSELEN 1 << PTOTSR4_V_EXT0TMRSELEN +#define PTOTSR4_V_EXT1TMRSEL 4 +#define PTOTSR4_M_EXT1TMRSEL 0x3 << PTOTSR4_V_EXT1TMRSEL +#define PTOTSR4_V_EXT1TMRSEL0 4 +#define PTOTSR4_M_EXT1TMRSEL0 1 << PTOTSR4_V_EXT1TMRSEL0 +#define PTOTSR4_V_EXT1TMRSEL1 5 +#define PTOTSR4_M_EXT1TMRSEL1 1 << PTOTSR4_V_EXT1TMRSEL1 +#define PTOTSR4_V_EXT1TMRSELEN 7 +#define PTOTSR4_M_EXT1TMRSELEN 1 << PTOTSR4_V_EXT1TMRSELEN +#define PTOTSR4_V_EXT2TMRSEL 8 +#define PTOTSR4_M_EXT2TMRSEL 0x3 << PTOTSR4_V_EXT2TMRSEL +#define PTOTSR4_V_EXT2TMRSEL0 8 +#define PTOTSR4_M_EXT2TMRSEL0 1 << PTOTSR4_V_EXT2TMRSEL0 +#define PTOTSR4_V_EXT2TMRSEL1 9 +#define PTOTSR4_M_EXT2TMRSEL1 1 << PTOTSR4_V_EXT2TMRSEL1 +#define PTOTSR4_V_EXT2TMRSELEN 11 +#define PTOTSR4_M_EXT2TMRSELEN 1 << PTOTSR4_V_EXT2TMRSELEN +#define PTOTSR4_V_EXT3TMRSEL 12 +#define PTOTSR4_M_EXT3TMRSEL 0x3 << PTOTSR4_V_EXT3TMRSEL +#define PTOTSR4_V_EXT3TMRSEL0 12 +#define PTOTSR4_M_EXT3TMRSEL0 1 << PTOTSR4_V_EXT3TMRSEL0 +#define PTOTSR4_V_EXT3TMRSEL1 13 +#define PTOTSR4_M_EXT3TMRSEL1 1 << PTOTSR4_V_EXT3TMRSEL1 +#define PTOTSR4_V_EXT3TMRSELEN 15 +#define PTOTSR4_M_EXT3TMRSELEN 1 << PTOTSR4_V_EXT3TMRSELEN + +/* +** EXTACT0 Activity Progammable Time-out Timer +*/ +#define EXT0TMRSEL_0 0x000 +#define EXT0TMRSEL_1 PTOTSR4_M_EXT0TMRSEL0 +#define EXT0TMRSEL_2 PTOTSR4_M_EXT0TMRSEL1 +#define EXT0TMRSEL_3 (PTOTSR4_M_EXT0TMRSEL0 | PTOTSR4_M_EXT0TMRSEL1) + +/* +** EXTACT1 Activity Progammable Time-out Timer +*/ +#define EXT1TMRSEL_0 0x000 +#define EXT1TMRSEL_1 PTOTSR4_M_EXT1TMRSEL0 +#define EXT1TMRSEL_2 PTOTSR4_M_EXT1TMRSEL1 +#define EXT1TMRSEL_3 (PTOTSR4_M_EXT1TMRSEL0 | PTOTSR4_M_EXT1TMRSEL1) + +/* +** EXTACT2 Activity Progammable Time-out Timer +*/ +#define EXT2TMRSEL_0 0x000 +#define EXT2TMRSEL_1 PTOTSR4_M_EXT2TMRSEL0 +#define EXT2TMRSEL_2 PTOTSR4_M_EXT2TMRSEL1 +#define EXT2TMRSEL_3 (PTOTSR4_M_EXT2TMRSEL0 | PTOTSR4_M_EXT2TMRSEL1) + +/* +** EXTACT3 Activity Progammable Time-out Timer +*/ +#define EXT3TMRSEL_0 0x000 +#define EXT3TMRSEL_1 PTOTSR4_M_EXT3TMRSEL0 +#define EXT3TMRSEL_2 PTOTSR4_M_EXT3TMRSEL1 +#define EXT3TMRSEL_3 (PTOTSR4_M_EXT3TMRSEL0 | PTOTSR4_M_EXT3TMRSEL1) + +/* +** System Registers +** +*/ + +/* +** +** Power-On Register (POR) - Index 0x100 +** +** Loc Size Name Function +** ----- ---- ---- --------------------------------- +** <0> 1 SEQUOIASEL SEQUOIA Select +** <3> 1 DLYBDEN Delay BD Bus Enable +** <4> 1 CPUMODESEL CPU Mode Select +** <6> 1 DLYBDBUSEN Delay BADS# & BDEV# Enable +** <7> 1 MISCCF0 Miscellaneous Configuration 0 +** <8> 1 MISCCF1 Miscellaneous Configuration 1 +** <9> 1 MISCCF2 Miscellaneous Configuration 2 +** <11> 1 EXTRTC Optional External RTC +** <12> 1 1X2XCLKSEL 1X/2X Clock Select +** +** <1:2><5><10><13:15> Reserved +*/ +#define SR_POR_REG 0x100 +#define POR_V_SEQUOIASEL 0 +#define POR_M_SEQUOIASEL 1 << POR_V_SEQUOIASEL +#define POR_V_DLYBDEN 3 +#define POR_M_DLYBDEN 1 << POR_V_DLYBDEN +#define POR_V_CPUMODESEL 4 +#define POR_M_CPUMODESEL 1 << POR_V_CPUMODESEL +#define POR_V_DLYBDBUSEN 6 +#define POR_M_DLYBDBUSEN 1 << POR_V_DLYBDBUSEN +#define POR_V_MISCCF 7 +#define POR_M_MISCCF 0x7 << POR_V_MISCCF +#define POR_V_MISCCF0 7 +#define POR_M_MISCCF0 1 << POR_V_MISCCF0 +#define POR_V_MISCCF1 8 +#define POR_M_MISCCF1 1 << POR_V_MISCCF1 +#define POR_V_MISCCF2 9 +#define POR_M_MISCCF2 1 << POR_V_MISCCF2 +#define POR_V_EXTRTC 11 +#define POR_M_EXTRTC 1 << POR_V_EXTRTC +#define POR_V_1X2XCLKSEL 12 +#define POR_M_1X2XCLKSEL 1 << POR_V_1X2XCLKSEL + +/* +** +** Non-Cacheable Region 1 Register (NCR1R) - Index 0x101 +** +** Loc Size Name Function +** ----- ---- ---- --------------------------------- +** <0> 1 NCR1EN Enable Non-Cacheable Region 1 +** <1> 1 NCR1BS0 Non-Cacheable Region 1 Block Size 0 +** <2> 1 NCR1BS1 Non-Cacheable Region 1 Block Size 1 +** <3> 13 NCR1A Non-Cacheable Region 1 Starting Addr +** +*/ +#define SR_NCR1R_REG 0x101 +#define SR_NCR1R_INIT 0x0000 +#define NCR1R_V_NCR1EN 0 +#define NCR1R_M_NCR1EN 1 << NCR1R_V_NCR1EN +#define NCR1R_V_NCR1BS 1 +#define NCR1R_M_NCR1BS 0x3 << NCR1R_V_NCR1BS +#define NCR1R_V_NCR1BS0 1 +#define NCR1R_M_NCR1BS0 1 << NCR1R_V_NCR1BS0 +#define NCR1R_V_NCR1BS1 1 +#define NCR1R_M_NCR1BS1 1 << NCR1R_V_NCR1BS1 +#define NCR1R_V_NCR1A 3 +#define NCR1R_M_NCR1A 0xFFF8 << NCR1R_V_NCR1A + +/* +** Non-Cacheable Region 1 Block Size (Kbytes) +*/ +#define NCR1BS_32K 0x000 +#define NCR1BS_64K NCR1R_M_NCR1BS0 +#define NCR1BS_128K NCR1R_M_NCR1BS1 +#define NCR1BS_256K (NCR1R_M_NCR1BS0 | NCR1R_M_NCR1BS1) + +/* +** +** Non-Cacheable Region 2 Register (NCR2R) - Index 0x102 +** +** Loc Size Name Function +** ----- ---- ---- --------------------------------- +** <0> 1 NCR2EN Enable Non-Cacheable Region 2 +** <1> 1 NCR2BS0 Non-Cacheable Region 2 Block Size 0 +** <2> 1 NCR2BS1 Non-Cacheable Region 2 Block Size 1 +** <3> 13 NCR2A Non-Cacheable Region 2 Starting Addr +** +*/ +#define SR_NCR2R_REG 0x102 +#define SR_NCR2R_INIT 0x0000 +#define NCR2R_V_NCR2EN 0 +#define NCR2R_M_NCR2EN 1 << NCR2R_V_NCR2EN +#define NCR2R_V_NCR2BS 1 +#define NCR2R_M_NCR2BS 0x3 << NCR2R_V_NCR2BS +#define NCR2R_V_NCR2BS0 1 +#define NCR2R_M_NCR2BS0 1 << NCR2R_V_NCR2BS0 +#define NCR2R_V_NCR2BS1 1 +#define NCR2R_M_NCR2BS1 1 << NCR2R_V_NCR2BS1 +#define NCR2R_V_NCR2A 3 +#define NCR2R_M_NCR2A 0xFFF8 << NCR2R_V_NCR2A + +/* +** Non-Cacheable Region 2 Block Size (Kbytes) +*/ +#define NCR2BS_32K 0x000 +#define NCR2BS_64K NCR2R_M_NCR2BS0 +#define NCR2BS_128K NCR2R_M_NCR2BS1 +#define NCR2BS_256K (NCR2R_M_NCR2BS0 | NCR2R_M_NCR2BS1) + +/* +** +** SYS Miscellaneous Control Register 1 (SYSMCR1) - Index 0x103 +** +** Loc Size Name Function +** ----- ---- ---- --------------------------------- +** <0> 1 LDSMIHLDER Load SMI Handler into SMM Space +** <1> 1 MOVRLYEN Memory Overlay Enable +** <2> 1 SMMMAPSEL SMM Memory Map Select +** <3> 1 SMMDETECT SMM Detect +** <4> 1 FLUSHWSMI Generate FLUSH# with SMI# Active +** <5> 1 SMIFLUSHIN SMI Flush In +** <6> 1 SMIFLUSHOUT SMI Flush Out +** <7> 1 SMMKENDIS SMM KEN Disable +** <8> 1 KDISSMMREG SMM Region KEN Disable +** <9> 1 SMISEL SMI Select +** <10> 1 SMMBLASTL Force BLAST# Low During SMM Cycles Enable +** <11> 1 SMMMSKA20 SMM Mask A20 +** <13> 1 SMMMAPD SMM Memory Map Using D Segment +** <14> 1 SMMMAPE SMM Memory Map Using E Segment +** <15> 1 SMISTRTSEL SMI Start Select +** +** <12> Reserved +*/ +#define SR_SYSMCR1_REG 0x103 +#define SR_SYSMCR1_INIT SYSMCR1_M_SMISEL +#define SYSMCR1_V_LDSMIHLDER 0 +#define SYSMCR1_M_LDSMIHLDER 1 << SYSMCR1_V_LDSMIHLDER +#define SYSMCR1_V_MOVRLYEN 1 +#define SYSMCR1_M_MOVRLYEN 1 << SYSMCR1_V_MOVRLYEN +#define SYSMCR1_V_SMMMAPSEL 2 +#define SYSMCR1_M_SMMMAPSEL 1 << SYSMCR1_V_SMMMAPSEL +#define SYSMCR1_V_SMMDETECT 3 +#define SYSMCR1_M_SMMDETECT 1 << SYSMCR1_V_SMMDETECT +#define SYSMCR1_V_FLUSHWSMI 4 +#define SYSMCR1_M_FLUSHWSMI 1 << SYSMCR1_V_FLUSHWSMI +#define SYSMCR1_V_SMIFLUSHIN 5 +#define SYSMCR1_M_SMIFLUSHIN 1 << SYSMCR1_V_SMIFLUSHIN +#define SYSMCR1_V_SMIFLUSHOUT 6 +#define SYSMCR1_M_SMIFLUSHOUT 1 << SYSMCR1_V_SMIFLUSHOUT +#define SYSMCR1_V_SMMKENDIS 7 +#define SYSMCR1_M_SMMKENDIS 1 << SYSMCR1_V_SMMKENDIS +#define SYSMCR1_V_KDISSMMREG 8 +#define SYSMCR1_M_KDISSMMREG 1 << SYSMCR1_V_KDISSMMREG +#define SYSMCR1_V_SMISEL 9 +#define SYSMCR1_M_SMISEL 1 << SYSMCR1_V_SMISEL +#define SYSMCR1_V_SMMBLASTL 10 +#define SYSMCR1_M_SMMBLASTL 1 << SYSMCR1_V_SMMBLASTL +#define SYSMCR1_V_SMMMSKA20 11 +#define SYSMCR1_M_SMMMSKA20 1 << SYSMCR1_V_SMMMSKA20 +#define SYSMCR1_V_SMMMAPD 13 +#define SYSMCR1_M_SMMMAPD 1 << SYSMCR1_V_SMMMAPD +#define SYSMCR1_V_SMMMAPE 14 +#define SYSMCR1_M_SMMMAPE 1 << SYSMCR1_V_SMMMAPE +#define SYSMCR1_V_SMISTRTSEL 15 +#define SYSMCR1_M_SMISTRTSEL 1 << SYSMCR1_V_SMISTRTSEL + +/* +** +** SYS Miscellaneous Control Register 2 (SYSMCR2) - Index 0x104 +** +** Loc Size Name Function +** ----- ---- ---- --------------------------------- +** <0> 1 SMIHLDOFRST Enable Hold-Off of SRESET During SMI Cycles +** <1> 1 LCLKDIS KEN Disable Always +** <2> 1 KFLUSH Cache Flush +** <4> 1 LSTIOLTCHEN Last I/O Latch Enable +** <6> 1 VLMSTLDOFF Lead-off Wait-State for VL-Master Cycle +** <13> 1 ENRDYN Generate RDY# at the End of a Burst Cycle +** <14> 1 LMABLOCK Local Memory Access at A0000-BFFFFH Lock +** <15> 1 SHDWRLOCK Shadow RAM Write Lock +** +** <3><5><7:12> Reserved +*/ +#define SR_SYSMCR2_REG 0x104 +#define SR_SYSMCR2_INIT ( SYSMCR2_M_SMIHLDOFRST | SYSMCR2_M_VLMSTLDOFF \ + SYSMCR2_M_ENRDYN ) +#define SYSMCR2_V_SMIHLDOFRST 0 +#define SYSMCR2_M_SMIHLDOFRST 1 << SYSMCR2_V_SMIHLDOFRST +#define SYSMCR2_V_LCLKDIS 1 +#define SYSMCR2_M_LCLKDIS 1 << SYSMCR2_V_LCLKDIS +#define SYSMCR2_V_KFLUSH 2 +#define SYSMCR2_M_KFLUSH 1 << SYSMCR2_V_KFLUSH +#define SYSMCR2_V_LSTIOLTCHEN 4 +#define SYSMCR2_M_LSTIOLTCHEN 1 << SYSMCR2_V_LSTIOLTCHEN +#define SYSMCR2_V_VLMSTLDOFF 6 +#define SYSMCR2_M_VLMSTLDOFF 1 << SYSMCR2_V_VLMSTLDOFF +#define SYSMCR2_V_ENRDYN 13 +#define SYSMCR2_M_ENRDYN 1 << SYSMCR2_V_ENRDYN +#define SYSMCR2_V_LMABLOCK 14 +#define SYSMCR2_M_LMABLOCK 1 << SYSMCR2_V_LMABLOCK +#define SYSMCR2_V_SHDWRLOCK 15 +#define SYSMCR2_M_SHDWRLOCK 1 << SYSMCR2_V_SHDWRLOCK + +/* +** +** Parity Address Register 1 (PARADR1) - Index 0x105 +** +** Loc Size Name Function +** ----- ---- ---- --------------------------------- +** <2> 14 PARADR Parity Error Address +** +** <0:1> Reserved +*/ +#define SR_PARADR1_REG 0x105 +#define PARADR1_V_PARADR 2 +#define PARADR1_M_PARADR 0xFFFC << PARADR1_V_PARADR + +/* +** +** Parity Address Register 2 (PARADR2) - Index 0x106 +** +** Loc Size Name Function +** ----- ---- ---- --------------------------------- +** <0> 12 PARADR Parity Error Address +** <12> 1 PARBE0 Byte Enables for Parity Error Address 0 +** <13> 1 PARBE1 Byte Enables for Parity Error Address 1 +** <14> 1 PARBE2 Byte Enables for Parity Error Address 2 +** <15> 1 PARBE3 Byte Enables for Parity Error Address 3 +** +*/ +#define SR_PARADR2_REG 0x106 +#define PARADR2_V_PARADR 0 +#define PARADR2_M_PARADR 0xFFF << PARADR2_V_PARADR +#define PARADR2_V_PARBE 12 +#define PARADR2_M_PARBE 0xF << PARADR2_V_PARBE +#define PARADR2_V_PARBE0 12 +#define PARADR2_M_PARBE0 1 << PARADR2_V_PARBE0 +#define PARADR2_V_PARBE1 13 +#define PARADR2_M_PARBE1 1 << PARADR2_V_PARBE1 +#define PARADR2_V_PARBE2 14 +#define PARADR2_M_PARBE2 1 << PARADR2_V_PARBE2 +#define PARADR2_V_PARBE3 15 +#define PARADR2_M_PARBE3 1 << PARADR2_V_PARBE3 + +/* +** SEQUOIA-1 Pin Function Select Registers +** +*/ + +/* +** +** SEQUOIA-1 Pin Select Register 1 (SEQPSR1) - Index 0x110 +** +** Loc Size Name Function +** ----- ---- ---- --------------------------------- +** <0> 1 NPWRGDDBDIS Negative PWRGD Edge Debounce Disable +** <1> 1 PORT92DIS Port 92 Disable +** <2> 1 TAGCSSEL TAGCS# Select +** <3> 1 LOCKPINSEL LOCK# Pin Select +** <4> 1 CCSPINEN CCS Pin Enable # +** <5> 1 TAGDEN TAG RAM Data Enable # +** <8> 1 GPIOC0PINEN GPIOC0 Pin Enable +** <10> 1 HTRGOUTEN Heat Regulator Output Enable +** <11> 1 GPIOA0PINEN GPIOA0 Pin Enable +** +** <6:7><9><12:15> Reserved +*/ +#define SEQR_SEQPSR1_REG 0x110 +#define SEQR_SEQPSR1_INIT ( SEQPSR1_M_PORT92DIS | SEQPSR1_M_CCSPINEN | \ + SEQPSR1_M_TAGDEN) +#define SEQPSR1_V_NPWRGDDBDIS 0 +#define SEQPSR1_M_NPWRGDDBDIS 1 << SEQPSR1_V_NPWRGDDBDIS +#define SEQPSR1_V_PORT92DIS 1 +#define SEQPSR1_M_PORT92DIS 1 << SEQPSR1_V_PORT92DIS +#define SEQPSR1_V_TAGCSSEL 2 +#define SEQPSR1_M_TAGCSSEL 1 << SEQPSR1_V_TAGCSSEL +#define SEQPSR1_V_LOCKPINSEL 3 +#define SEQPSR1_M_LOCKPINSEL 1 << SEQPSR1_V_LOCKPINSEL +#define SEQPSR1_V_CCSPINEN 4 +#define SEQPSR1_M_CCSPINEN 1 << SEQPSR1_V_CCSPINEN +#define SEQPSR1_V_TAGDEN 5 +#define SEQPSR1_M_TAGDEN 1 << SEQPSR1_V_TAGDEN +#define SEQPSR1_V_GPIOC0PINEN 8 +#define SEQPSR1_M_GPIOC0PINEN 1 << SEQPSR1_V_GPIOC0PINEN +#define SEQPSR1_V_HTRGOUTEN 10 +#define SEQPSR1_M_HTRGOUTEN 1 << SEQPSR1_V_HTRGOUTEN +#define SEQPSR1_V_GPIOA0PINEN 11 +#define SEQPSR1_M_GPIOA0PINEN 1 << SEQPSR1_V_GPIOA0PINEN + +/* +** +** SEQUOIA-1 Pin Select Register 2 (SEQPSR2) - Index 0x111 +** +** Loc Size Name Function +** ----- ---- ---- --------------------------------- +** <0> 1 OPGPEXTEN Optional GPEXT Enable +** <2> 1 EXTACT3PINEN EXTACT3 Pin Enable +** <3> 1 NMIPINEN NMI Pin Enable +** <4> 1 DIRTYPINEN DIRTY Pin Enable # +** <5> 1 GPIOB0PINEN GPIOB0 Pin Enable +** <6> 1 DRTWEPINEN DRTWE# Pin Enable # +** <7> 1 GPIOB1PINEN GPIOB1 Pin Enable +** <8> 1 KBRSTPINEN KB reset Pin Enable +** <11> 1 GPIOC1PINEN GPIOC1 Pin Enable +** <12> 1 GPIO0PINEN GPIO0 Pin Enable # +** <13> 1 GPIO1PINEN GPIO1 Pin Enable # +** <14> 1 GPIO2PINEN GPIO2 Pin Enable # +** <15> 1 GPIO3PINEN GPIO3 Pin Enable # +** +** <1><9:10> Reserved +*/ +#define SEQR_SEQPSR2_REG 0x111 +#define SEQR_SEQPSR2_INIT ( SEQPSR2_M_NMIPINEN | SEQPSR2_M_DIRTYPINEN |\ + SEQPSR2_M_GPIOB0PINEN | SEQPSR2_M_DRTWEPINEN |\ + SEQPSR2_M_GPIOB1PINEN | SEQPSR2_M_KBRSTPINEN |\ + SEQPSR2_M_BIT9 | SEQPSR2_M_BIT10 |\ + SEQPSR2_M_GPIOC1PINEN ) +#define SEQPSR2_V_OPGPEXTEN 0 +#define SEQPSR2_M_OPGPEXTEN 1 << SEQPSR2_V_OPGPEXTEN +#define SEQPSR2_V_EXTACT3PINEN 2 +#define SEQPSR2_M_EXTACT3PINEN 1 << SEQPSR2_V_EXTACT3PINEN +#define SEQPSR2_V_NMIPINEN 3 +#define SEQPSR2_M_NMIPINEN 1 << SEQPSR2_V_NMIPINEN +#define SEQPSR2_V_DIRTYPINEN 4 +#define SEQPSR2_M_DIRTYPINEN 1 << SEQPSR2_V_DIRTYPINEN +#define SEQPSR2_V_GPIOB0PINEN 5 +#define SEQPSR2_M_GPIOB0PINEN 1 << SEQPSR2_V_GPIOB0PINEN +#define SEQPSR2_V_DRTWEPINEN 6 +#define SEQPSR2_M_DRTWEPINEN 1 << SEQPSR2_V_DRTWEPINEN +#define SEQPSR2_V_GPIOB1PINEN 7 +#define SEQPSR2_M_GPIOB1PINEN 1 << SEQPSR2_V_GPIOB1PINEN +#define SEQPSR2_V_KBRSTPINEN 8 +#define SEQPSR2_M_KBRSTPINEN 1 << SEQPSR2_V_KBRSTPINEN +#define SEQPSR2_V_BIT9 9 +#define SEQPSR2_M_BIT9 1 << SEQPSR2_V_BIT9 +#define SEQPSR2_V_BIT10 10 +#define SEQPSR2_M_BIT10 1 << SEQPSR2_V_BIT10 +#define SEQPSR2_V_GPIOC1PINEN 11 +#define SEQPSR2_M_GPIOC1PINEN 1 << SEQPSR2_V_GPIOC1PINEN +#define SEQPSR2_V_GPIO0PINEN 12 +#define SEQPSR2_M_GPIO0PINEN 1 << SEQPSR2_V_GPIO0PINEN +#define SEQPSR2_V_GPIO1PINEN 13 +#define SEQPSR2_M_GPIO1PINEN 1 << SEQPSR2_V_GPIO1PINEN +#define SEQPSR2_V_GPIO2PINEN 14 +#define SEQPSR2_M_GPIO2PINEN 1 << SEQPSR2_V_GPIO2PINEN +#define SEQPSR2_V_GPIO3PINEN 15 +#define SEQPSR2_M_GPIO3PINEN 1 << SEQPSR2_V_GPIO3PINEN + +/* +** +** SEQUOIA-1 Pin Select Register 3 (SEQPSR3) - Index 0x112 +** +** Loc Size Name Function +** ----- ---- ---- --------------------------------- +** <0> 1 PC0PINEN PC0 Pin Enable # +** <2> 1 PC2PINEN PC2 Pin Enable # +** <3> 1 PC3PINEN PC3 Pin Enable # +** <4> 1 PC4PINEN PC4 Pin Enable # +** <5> 1 PC5PINEN PC5 Pin Enable # +** <6> 1 PC6PINEN PC6 Pin Enable # +** <7> 1 PC7PINEN PC7 Pin Enable # +** <8> 1 PC8PINEN PC8 Pin Enable # +** <9> 1 PC9PINEN PC9 Pin Enable # +** <12> 1 EXTACT0PINEN EXTACT0 Pin Enable +** <15> 1 EXTACT1PINEN EXTACT1 Pin Enable +** +** <1><10:11><13:14> Reserved +*/ +#define SEQR_SEQPSR3_REG 0x112 +#define SEQR_SEQPSR3_INIT ( SEQPSR3_M_PC2PINEN | SEQPSR3_M_PC3PINEN | \ + SEQPSR3_M_PC4PINEN | SEQPSR3_M_PC5PINEN | \ + SEQPSR3_M_PC6PINEN | SEQPSR3_M_PC7PINEN | \ + SEQPSR3_M_PC8PINEN | SEQPSR3_M_PC9PINEN ) +#define SEQPSR3_V_PC0PINEN 0 +#define SEQPSR3_M_PC0PINEN 1 << SEQPSR3_V_PC0PINEN +#define SEQPSR3_V_PC2PINEN 2 +#define SEQPSR3_M_PC2PINEN 1 << SEQPSR3_V_PC2PINEN +#define SEQPSR3_V_PC3PINEN 3 +#define SEQPSR3_M_PC3PINEN 1 << SEQPSR3_V_PC3PINEN +#define SEQPSR3_V_PC4PINEN 4 +#define SEQPSR3_M_PC4PINEN 1 << SEQPSR3_V_PC4PINEN +#define SEQPSR3_V_PC5PINEN 5 +#define SEQPSR3_M_PC5PINEN 1 << SEQPSR3_V_PC5PINEN +#define SEQPSR3_V_PC6PINEN 6 +#define SEQPSR3_M_PC6PINEN 1 << SEQPSR3_V_PC6PINEN +#define SEQPSR3_V_PC7PINEN 7 +#define SEQPSR3_M_PC7PINEN 1 << SEQPSR3_V_PC7PINEN +#define SEQPSR3_V_PC8PINEN 8 +#define SEQPSR3_M_PC8PINEN 1 << SEQPSR3_V_PC8PINEN +#define SEQPSR3_V_PC9PINEN 9 +#define SEQPSR3_M_PC9PINEN 1 << SEQPSR3_V_PC9PINEN +#define SEQPSR3_V_EXTACT0PINEN 12 +#define SEQPSR3_M_EXTACT0PINEN 1 << SEQPSR3_V_EXTACT0PINEN +#define SEQPSR3_V_EXTACT1PINEN 15 +#define SEQPSR3_M_EXTACT1PINEN 1 << SEQPSR3_V_EXTACT1PINEN + +/* +** +** Modular Clock Control Register (MODCLKCR) - Index 0x118 +** +** Loc Size Name Function +** ----- ---- ---- --------------------------------- +** <1> 1 VLCLKSTPEN VL Clock Stop Enable +** <5> 1 ADSMDIS ADS Mask Disable +** <8> 1 MDCHGIMD Mode Change Immediate +** <11> 1 SLWATCKEN SLOW AT Clock Enable +** +** <0><2:4><6:7><9:10><12:15> Reserved +*/ +#define SEQR_MODCLKCR_REG 0x118 +#define SEQR_MODCLKCR_INIT MODCLKCR_M_VLCLKSTPEN +#define MODCLKCR_V_VLCLKSTPEN 1 +#define MODCLKCR_M_VLCLKSTPEN 1 << MODCLKCR_V_VLCLKSTPEN +#define MODCLKCR_V_ADSMDIS 5 +#define MODCLKCR_M_ADSMDIS 1 << MODCLKCR_V_ADSMDIS +#define MODCLKCR_V_MDCHGIMD 8 +#define MODCLKCR_M_MDCHGIMD 1 << MODCLKCR_V_MDCHGIMD +#define MODCLKCR_V_SLWATCKEN 11 +#define MODCLKCR_M_SLWWATCKEN 1 << MODCLKCR_V_SLWATCKEN + +/* +** +** Burst Bus Control Register (BBUSCR) - Index 0x180 +** +** Loc Size Name Function +** ----- ---- ---- --------------------------------- +** <3> 1 SQ1GIDEEN SEQUOIA-1 Global Turbo IDE Enable +** <5> 1 RSTREADSEN Restart EADS Enable +** <15> 1 SECIDEN Secondary IDE Drive Enable +** +** <0:2><4><6:14> Reserved +*/ +#define SEQR_BBUSCR_REG 0x180 +#define BBUSCR_V_SQ1GIDEEN 3 +#define BBUSCR_M_SQ1GIDEEN 1 << BBUSCR_V_SQ1GIDEEN +#define BBUSCR_V_RSTREADSEN 5 +#define BBUSCR_M_RSTREADSEN 1 << BBUSCR_V_RSTREADSEN +#define BBUSCR_V_SECIDEN 15 +#define BBUSCR_M_SECIDEN 1 << BBUSCR_V_SECIDEN + +/* +** DRAM Control Registers +** +*/ + +/* +** +** Shadow RAM Read Enable Control Register (SRAMRDENCR) - Index 0x200 +** +** Loc Size Name Function +** ----- ---- ---- --------------------------------- +** <0> 1 LMEMRDEN0 Local Memory C0000H-C3FFFH Read Enable +** <1> 1 LMEMRDEN1 Local Memory C4000H-C7FFFH Read Enable +** <2> 1 LMEMRDEN2 Local Memory C8000H-CBFFFH Read Enable +** <3> 1 LMEMRDEN3 Local Memory CC000H-CFFFFH Read Enable +** <4> 1 LMEMRDEN4 Local Memory D0000H-D3FFFH Read Enable +** <5> 1 LMEMRDEN5 Local Memory D4000H-D7FFFH Read Enable +** <6> 1 LMEMRDEN6 Local Memory D8000H-DBFFFH Read Enable +** <7> 1 LMEMRDEN7 Local Memory DC000H-DFFFFH Read Enable +** <8> 1 LMEMRDEN8 Local Memory E0000H-E3FFFH Read Enable +** <9> 1 LMEMRDEN9 Local Memory E4000H-E7FFFH Read Enable +** <10> 1 LMEMRDEN10 Local Memory E8000H-EBFFFH Read Enable +** <11> 1 LMEMRDEN11 Local Memory EC000H-EFFFFH Read Enable +** <12> 1 LMEMRDEN12 Local Memory F0000H-FFFFFH Read Enable +** +** <13:15> Reserved +*/ +#define DRAMCR_SRAMRDENCR_REG 0x200 +#define DRAMCR_SRAMRDENCR_INIT 0x0000 +#define SRAMRDENCR_V_LMEMRDEN0 0 +#define SRAMRDENCR_M_LMEMRDEN0 1 << SRAMRDENCR_V_LMEMRDEN0 +#define SRAMRDENCR_V_LMEMRDEN1 1 +#define SRAMRDENCR_M_LMEMRDEN1 1 << SRAMRDENCR_V_LMEMRDEN1 +#define SRAMRDENCR_V_LMEMRDEN2 2 +#define SRAMRDENCR_M_LMEMRDEN2 1 << SRAMRDENCR_V_LMEMRDEN2 +#define SRAMRDENCR_V_LMEMRDEN3 3 +#define SRAMRDENCR_M_LMEMRDEN3 1 << SRAMRDENCR_V_LMEMRDEN3 +#define SRAMRDENCR_V_LMEMRDEN4 4 +#define SRAMRDENCR_M_LMEMRDEN4 1 << SRAMRDENCR_V_LMEMRDEN4 +#define SRAMRDENCR_V_LMEMRDEN5 5 +#define SRAMRDENCR_M_LMEMRDEN5 1 << SRAMRDENCR_V_LMEMRDEN5 +#define SRAMRDENCR_V_LMEMRDEN6 6 +#define SRAMRDENCR_M_LMEMRDEN6 1 << SRAMRDENCR_V_LMEMRDEN6 +#define SRAMRDENCR_V_LMEMRDEN7 7 +#define SRAMRDENCR_M_LMEMRDEN7 1 << SRAMRDENCR_V_LMEMRDEN7 +#define SRAMRDENCR_V_LMEMRDEN8 8 +#define SRAMRDENCR_M_LMEMRDEN8 1 << SRAMRDENCR_V_LMEMRDEN8 +#define SRAMRDENCR_V_LMEMRDEN9 9 +#define SRAMRDENCR_M_LMEMRDEN9 1 << SRAMRDENCR_V_LMEMRDEN9 +#define SRAMRDENCR_V_LMEMRDEN10 10 +#define SRAMRDENCR_M_LMEMRDEN10 1 << SRAMRDENCR_V_LMEMRDEN10 +#define SRAMRDENCR_V_LMEMRDEN11 11 +#define SRAMRDENCR_M_LMEMRDEN11 1 << SRAMRDENCR_V_LMEMRDEN11 +#define SRAMRDENCR_V_LMEMRDEN12 12 +#define SRAMRDENCR_M_LMEMRDEN12 1 << SRAMRDENCR_V_LMEMRDEN12 + +/* +** +** Shadow RAM Write Enable Control Register (SRAMWRENCR) - Index 0x201 +** +** Loc Size Name Function +** ----- ---- ---- --------------------------------- +** <0> 1 LMEMWREN0 Local Memory C0000H-C3FFFH Write Enable +** <1> 1 LMEMWREN1 Local Memory C4000H-C7FFFH Write Enable +** <2> 1 LMEMWREN2 Local Memory C8000H-CBFFFH Write Enable +** <3> 1 LMEMWREN3 Local Memory CC000H-CFFFFH Write Enable +** <4> 1 LMEMWREN4 Local Memory D0000H-D3FFFH Write Enable +** <5> 1 LMEMWREN5 Local Memory D4000H-D7FFFH Write Enable +** <6> 1 LMEMWREN6 Local Memory D8000H-DBFFFH Write Enable +** <7> 1 LMEMWREN7 Local Memory DC000H-DFFFFH Write Enable +** <8> 1 LMEMWREN8 Local Memory E0000H-E3FFFH Write Enable +** <9> 1 LMEMWREN9 Local Memory E4000H-E7FFFH Write Enable +** <10> 1 LMEMWREN10 Local Memory E8000H-EBFFFH Write Enable +** <11> 1 LMEMWREN11 Local Memory EC000H-EFFFFH Write Enable +** <12> 1 LMEMWREN12 Local Memory F0000H-FFFFFH Write Enable +** +** <13:15> Reserved +*/ +#define DRAMCR_SRAMWRENCR_REG 0x201 +#define DRAMCR_SRAMWRENCR_INIT 0x0000 +#define SRAMWRENCR_V_LMEMWREN0 0 +#define SRAMWRENCR_M_LMEMWREN0 1 << SRAMWRENCR_V_LMEMWREN0 +#define SRAMWRENCR_V_LMEMWREN1 1 +#define SRAMWRENCR_M_LMEMWREN1 1 << SRAMWRENCR_V_LMEMWREN1 +#define SRAMWRENCR_V_LMEMWREN2 2 +#define SRAMWRENCR_M_LMEMWREN2 1 << SRAMWRENCR_V_LMEMWREN2 +#define SRAMWRENCR_V_LMEMWREN3 3 +#define SRAMWRENCR_M_LMEMWREN3 1 << SRAMWRENCR_V_LMEMWREN3 +#define SRAMWRENCR_V_LMEMWREN4 4 +#define SRAMWRENCR_M_LMEMWREN4 1 << SRAMWRENCR_V_LMEMWREN4 +#define SRAMWRENCR_V_LMEMWREN5 5 +#define SRAMWRENCR_M_LMEMWREN5 1 << SRAMWRENCR_V_LMEMWREN5 +#define SRAMWRENCR_V_LMEMWREN6 6 +#define SRAMWRENCR_M_LMEMWREN6 1 << SRAMWRENCR_V_LMEMWREN6 +#define SRAMWRENCR_V_LMEMWREN7 7 +#define SRAMWRENCR_M_LMEMWREN7 1 << SRAMWRENCR_V_LMEMWREN7 +#define SRAMWRENCR_V_LMEMWREN8 8 +#define SRAMWRENCR_M_LMEMWREN8 1 << SRAMWRENCR_V_LMEMWREN8 +#define SRAMWRENCR_V_LMEMWREN9 9 +#define SRAMWRENCR_M_LMEMWREN9 1 << SRAMWRENCR_V_LMEMWREN9 +#define SRAMWRENCR_V_LMEMWREN10 10 +#define SRAMWRENCR_M_LMEMWREN10 1 << SRAMWRENCR_V_LMEMWREN10 +#define SRAMWRENCR_V_LMEMWREN11 11 +#define SRAMWRENCR_M_LMEMWREN11 1 << SRAMWRENCR_V_LMEMWREN11 +#define SRAMWRENCR_V_LMEMWREN12 12 +#define SRAMWRENCR_M_LMEMWREN12 1 << SRAMWRENCR_V_LMEMWREN12 + +/* +** +** Bank 0 Control Register (BK0CR) - Index 0x202 +** +** Loc Size Name Function +** ----- ---- ---- --------------------------------- +** <0> 8 B0A Bank 0 Starting Address +** <8> 1 B0S0 Bank 0 DRAM Size 0 +** <9> 1 B0S1 Bank 0 DRAM Size 1 +** <10> 1 B0S2 Bank 0 DRAM Size 2 +** <11> 1 BANKEN0 Bank 0 Enable +** <12> 1 ENMDEN0N Enable MDEN# for Bank 0 +** <13> 1 COLADR00 Number of Column Address Bits for Bank 0 0 +** <14> 1 COLADR01 Number of Column Address Bits for Bank 0 1 +** <15> 1 COLADR02 Number of Column Address Bits for Bank 0 2 +** +*/ +#define DRAMCR_BK0CR_REG 0x202 +#define DRAMCR_BK0CR_INIT 0x0000 +#define BK0CR_V_B0A 0 +#define BK0CR_M_B0A 0xFF << BK0CR_V_B0A +#define BK0CR_V_B0S 8 +#define BK0CR_M_B0S 0x7 << BK0CR_V_B0S +#define BK0CR_V_B0S0 8 +#define BK0CR_M_B0S0 1 << BK0CR_V_B0S0 +#define BK0CR_V_B0S1 9 +#define BK0CR_M_B0S1 1 << BK0CR_V_B0S1 +#define BK0CR_V_B0S2 10 +#define BK0CR_M_B0S2 1 << BK0CR_V_B0S2 +#define BK0CR_V_BANKEN0 11 +#define BK0CR_M_BANKEN0 1 << BK0CR_V_BANKEN0 +#define BK0CR_V_ENMDEN0N 12 +#define BK0CR_M_ENMDEN0N 1 << BK0CR_V_ENMDEN0N +#define BK0CR_V_COLADR0 13 +#define BK0CR_M_COLADR0 0xE << BK0CR_V_COLADR0 +#define BK0CR_V_COLADR00 13 +#define BK0CR_M_COLADR00 1 << BK0CR_V_COLADR00 +#define BK0CR_V_COLADR01 14 +#define BK0CR_M_COLADR01 1 << BK0CR_V_COLADR01 +#define BK0CR_V_COLADR02 15 +#define BK0CR_M_COLADR02 1 << BK0CR_V_COLADR02 + +/* +** Bank 0 DRAM Size +*/ +#define B0S_256KB 0x000 +#define B0S_512KB BK0CR_M_B0S0 +#define B0S_1MB BK0CR_M_B0S1 +#define B0S_2MB (BK0CR_M_B0S0 | BK0CR_M_B0S1) +#define B0S_4MB BK0CR_M_B0S2 +#define B0S_16MB (BK0CR_M_B0S1 | BK0CR_M_B0S2) + +/* +** Bank 0 Column Address Bits +*/ +#define COLADR0_8 0x000 +#define COLADR0_9 BK0CR_M_COLADR00 +#define COLADR0_10 BK0CR_M_COLADR01 +#define COLADR0_11 (BK0CR_M_COLADR00 | BK0CR_M_COLADR01) +#define COLADR0_12 BK0CR_M_COLADR02 + +/* +** +** Bank 1 Control Register (BK1CR) - Index 0x203 +** +** Loc Size Name Function +** ----- ---- ---- --------------------------------- +** <0> 8 B1A Bank 1 Starting Address +** <8> 1 B1S0 Bank 1 DRAM Size 0 +** <9> 1 B1S1 Bank 1 DRAM Size 1 +** <10> 1 B1S2 Bank 1 DRAM Size 2 +** <11> 1 BANKEN1 Bank 1 Enable +** <12> 1 ENMDEN1N Enable MDEN# for Bank 1 +** <13> 1 COLADR10 Number of Column Address Bits for Bank 1 0 +** <14> 1 COLADR11 Number of Column Address Bits for Bank 1 1 +** <15> 1 COLADR12 Number of Column Address Bits for Bank 1 2 +** +*/ +#define DRAMCR_BK1CR_REG 0x203 +#define DRAMCR_BK1CR_INIT 0x0000 +#define BK1CR_V_B1A 0 +#define BK1CR_M_B1A 0xFF << BK1CR_V_B1A +#define BK1CR_V_B1S 8 +#define BK1CR_M_B1S 0x7 << BK1CR_V_B1S +#define BK1CR_V_B1S0 8 +#define BK1CR_M_B1S0 1 << BK1CR_V_B1S0 +#define BK1CR_V_B1S1 9 +#define BK1CR_M_B1S1 1 << BK1CR_V_B1S1 +#define BK1CR_V_B1S2 10 +#define BK1CR_M_B1S2 1 << BK1CR_V_B1S2 +#define BK1CR_V_BANKEN1 11 +#define BK1CR_M_BANKEN1 1 << BK1CR_V_BANKEN1 +#define BK1CR_V_ENMDEN1N 12 +#define BK1CR_M_ENMDEN1N 1 << BK1CR_V_ENMDEN1N +#define BK1CR_V_COLADR1 13 +#define BK1CR_M_COLADR1 0xE << BK1CR_V_COLADR1 +#define BK1CR_V_COLADR10 13 +#define BK1CR_M_COLADR10 1 << BK1CR_V_COLADR10 +#define BK1CR_V_COLADR11 14 +#define BK1CR_M_COLADR11 1 << BK1CR_V_COLADR11 +#define BK1CR_V_COLADR12 15 +#define BK1CR_M_COLADR12 1 << BK1CR_V_COLADR12 + +/* +** Bank 1 DRAM Size +*/ +#define B1S_256KB 0x000 +#define B1S_512KB BK1CR_M_B1S0 +#define B1S_1MB BK1CR_M_B1S1 +#define B1S_2MB (BK1CR_M_B1S0 | BK1CR_M_B1S1) +#define B1S_4MB BK1CR_M_B1S2 +#define B1S_16MB (BK1CR_M_B1S1 | BK1CR_M_B1S2) + +/* +** Bank 1 Column Address Bits +*/ +#define COLADR1_8 0x000 +#define COLADR1_9 BK1CR_M_COLADR10 +#define COLADR1_10 BK1CR_M_COLADR11 +#define COLADR1_11 (BK1CR_M_COLADR10 | BK1CR_M_COLADR11) +#define COLADR1_12 BK1CR_M_COLADR12 + +/* +** +** Bank 0/1 Timing Control Register (BK01TCR) - Index 0x204 +** +** Loc Size Name Function +** ----- ---- ---- --------------------------------- +** <0> 1 B01WRCPW0 Bank 0/1 Write CAS Cycle Time 0 +** <1> 1 B01WRCPW1 Bank 0/1 Write CAS Cycle Time 1 +** <2> 1 MA01WRDLY Bank 0/1 Write MA Delay +** <3> 1 B01RDCPW0 Bank 0/1 Read CAS Cycle Time 0 +** <4> 1 B01RDCPW1 Bank 0/1 Read CAS Cycle Time 1 +** <5> 1 MA01RDDLY Bank 0/1 Read MA Delay +** <6> 1 B01CPRE Bank 0/1 CAS Precharge +** <7> 1 B01RTMA Bank 0/1 RAS to CAS Delay +** <8> 1 B01MATC Bank 0/1 MA to CAS Delay +** <9> 1 B01RPRE0 Bank 0/1 RAS Precharge Time 0 +** <10> 1 B01RPRE1 Bank 0/1 RAS Precharge Time 1 +** <11> 1 B01RPRE2 Bank 0/1 RAS Precharge Time 2 +** <12> 1 B01ILAVDT Bank 0/1 Interleave Avoid Time +** <13> 1 BNK01_ITL Bank 0/1 Interleave Enable +** +** <14:15> Reserved +*/ +#define DRAMCR_BK01TCR_REG 0x204 +#define DRAMCR_BK01TCR_INIT ( BK01TCR_M_B01WRCPW | BK01TCR_M_MA01WRDLY | \ + BK01TCR_M_B01RDCPW | BK01TCR_M_MA01RDDLY | \ + BK01TCR_M_B01CPRE | BK01TCR_M_B01RTMA | \ + BK01TCR_M_B01MATC | BK01TCR_M_B01RPRE | \ + BK01TCR_M_B01ILAVDT ) +#define BK01TCR_V_B01WRCPW 0 +#define BK01TCR_M_B01WRCPW 0x3 << BK01TCR_V_B01WRCPW +#define BK01TCR_V_B01WRCPW0 0 +#define BK01TCR_M_B01WRCPW0 1 << BK01TCR_V_B01WRCPW0 +#define BK01TCR_V_B01WRCPW1 1 +#define BK01TCR_M_B01WRCPW1 1 << BK01TCR_V_B01WRCPW1 +#define BK01TCR_V_MA01WRDLY 2 +#define BK01TCR_M_MA01WRDLY 1 << BK01TCR_V_MA01WRDLY +#define BK01TCR_V_B01RDCPW 3 +#define BK01TCR_M_B01RDCPW 0x3 << BK01TCR_V_B01RDCPW +#define BK01TCR_V_B01RDCPW0 3 +#define BK01TCR_M_B01RDCPW0 1 << BK01TCR_V_B01RDCPW0 +#define BK01TCR_V_B01RDCPW1 4 +#define BK01TCR_M_B01RDCPW1 1 << BK01TCR_V_B01RDCPW1 +#define BK01TCR_V_MA01RDDLY 5 +#define BK01TCR_M_MA01RDDLY 1 << BK01TCR_V_MA01RDDLY +#define BK01TCR_V_B01CPRE 6 +#define BK01TCR_M_B01CPRE 1 << BK01TCR_V_B01CPRE +#define BK01TCR_V_B01RTMA 7 +#define BK01TCR_M_B01RTMA 1 << BK01TCR_V_B01RTMA +#define BK01TCR_V_B01MATC 8 +#define BK01TCR_M_B01MATC 1 << BK01TCR_V_B01MATC +#define BK01TCR_V_B01RPRE 9 +#define BK01TCR_M_B01RPRE 0x7 << BK01TCR_V_B01RPRE +#define BK01TCR_V_B01RPRE0 9 +#define BK01TCR_M_B01RPRE0 1 << BK01TCR_V_B01RPRE0 +#define BK01TCR_V_B01RPRE1 10 +#define BK01TCR_M_B01RPRE1 1 << BK01TCR_V_B01RPRE1 +#define BK01TCR_V_B01RPRE2 11 +#define BK01TCR_M_B01RPRE2 1 << BK01TCR_V_B01RPRE2 +#define BK01TCR_V_B01ILAVDT 12 +#define BK01TCR_M_B01ILAVDT 1 << BK01TCR_V_B01ILAVDT +#define BK01TCR_V_BNK01_ITL 13 +#define BK01TCR_M_BNK01_ITL 1 << BK01TCR_V_BNK01_ITL + +/* +** Bank 0/1 Write CAS Cycle Time +*/ +#define B01WRCPW_1T BK01TCR_M_B01WRCPW0 +#define B01WRCPW_2T BK01TCR_M_B01WRCPW1 +#define B01WRCPW_3T (BK01TCR_M_B01WRCPW0 | BK01TCR_M_B01WRCPW1) + +/* +** Bank 0/1 Read CAS Cycle Time +*/ +#define B01RDCPW_1T 0x000 +#define B01RDCPW_2T BK01TCR_M_B01WRCPW0 +#define B01RDCPW_3T BK01TCR_M_B01WRCPW1 +#define B01RDCPW_4T (BK01TCR_M_B01WRCPW0 | BK01TCR_M_B01WRCPW1) + +/* +** Bank 0/1 RAS Precharge Time +*/ +#define B01RPRE_1PT5T BK01TCR_M_B01RPRE1 +#define B01RPRE_2T (BK01TCR_M_B01RPRE0 | BK01TCR_M_B01RPRE1) +#define B01RPRE_2PT5T BK01TCR_M_B01RPRE2 +#define B01RPRE_3T (BK01TCR_M_B01RPRE0 | BK01TCR_M_B01RPRE2) +#define B01RPRE_3PT5T (BK01TCR_M_B01RPRE1 | BK01TCR_M_B01RPRE2) +#define B01RPRE_4T (BK01TCR_M_B01RPRE0 | BK01TCR_M_B01RPRE1 | BK01TCR_M_B01RPRE2) + +/* +** +** Bank 2 Control Register (BK2CR) - Index 0x205 +** +** Loc Size Name Function +** ----- ---- ---- --------------------------------- +** <0> 8 B2A Bank 2 Starting Address +** <8> 1 B2S0 Bank 2 DRAM Size 0 +** <9> 1 B2S1 Bank 2 DRAM Size 1 +** <10> 1 B2S2 Bank 2 DRAM Size 2 +** <11> 1 BANKEN2 Bank 2 Enable +** <12> 1 ENMDEN2N Enable MDEN# for Bank 2 +** <13> 1 COLADR20 Number of Column Address Bits for Bank 2 0 +** <14> 1 COLADR21 Number of Column Address Bits for Bank 2 1 +** <15> 1 COLADR22 Number of Column Address Bits for Bank 2 2 +** +*/ +#define DRAMCR_BK2CR_REG 0x205 +#define DRAMCR_BK2CR_INIT 0x0000 +#define BK2CR_V_B2A 0 +#define BK2CR_M_B2A 0xFF << BK2CR_V_B2A +#define BK2CR_V_B2S 8 +#define BK2CR_M_B2S 0x7 << BK2CR_V_B2S +#define BK2CR_V_B2S0 8 +#define BK2CR_M_B2S0 1 << BK2CR_V_B2S0 +#define BK2CR_V_B2S1 9 +#define BK2CR_M_B2S1 1 << BK2CR_V_B2S1 +#define BK2CR_V_B2S2 10 +#define BK2CR_M_B2S2 1 << BK2CR_V_B2S2 +#define BK2CR_V_BANKEN2 11 +#define BK2CR_M_BANKEN2 1 << BK2CR_V_BANKEN2 +#define BK2CR_V_ENMDEN2N 12 +#define BK2CR_M_ENMDEN2N 1 << BK2CR_V_ENMDEN2N +#define BK2CR_V_COLADR2 13 +#define BK2CR_M_COLADR2 0xE << BK2CR_V_COLADR2 +#define BK2CR_V_COLADR20 13 +#define BK2CR_M_COLADR20 1 << BK2CR_V_COLADR20 +#define BK2CR_V_COLADR21 14 +#define BK2CR_M_COLADR21 1 << BK2CR_V_COLADR21 +#define BK2CR_V_COLADR22 15 +#define BK2CR_M_COLADR22 1 << BK2CR_V_COLADR22 + +/* +** Bank 2 DRAM Size +*/ +#define B2S_256KB 0x000 +#define B2S_512KB BK2CR_M_B2S0 +#define B2S_1MB BK2CR_M_B2S1 +#define B2S_2MB (BK2CR_M_B2S0 | BK2CR_M_B2S1) +#define B2S_4MB BK2CR_M_B2S2 +#define B2S_16MB (BK2CR_M_B2S1 | BK2CR_M_B2S2) + +/* +** Bank 2 Column Address Bits +*/ +#define COLADR2_8 0x000 +#define COLADR2_9 BK2CR_M_COLADR20 +#define COLADR2_10 BK2CR_M_COLADR21 +#define COLADR2_11 (BK2CR_M_COLADR20 | BK2CR_M_COLADR21) +#define COLADR2_12 BK2CR_M_COLADR22 + +/* +** +** Bank 3 Control Register (BK3CR) - Index 0x206 +** +** Loc Size Name Function +** ----- ---- ---- --------------------------------- +** <0> 8 B3A Bank 3 Starting Address +** <8> 1 B3S0 Bank 3 DRAM Size 0 +** <9> 1 B3S1 Bank 3 DRAM Size 1 +** <10> 1 B3S2 Bank 3 DRAM Size 2 +** <11> 1 BANKEN3 Bank 3 Enable +** <12> 1 ENMDEN3N Enable MDEN# for Bank 3 +** <13> 1 COLADR30 Number of Column Address Bits for Bank 3 0 +** <14> 1 COLADR31 Number of Column Address Bits for Bank 3 1 +** <15> 1 COLADR32 Number of Column Address Bits for Bank 3 2 +** +*/ +#define DRAMCR_BK3CR_REG 0x206 +#define DRAMCR_BK3CR_INIT 0x0000 +#define BK3CR_V_B3A 0 +#define BK3CR_M_B3A 0xFF << BK3CR_V_B3A +#define BK3CR_V_B3S 8 +#define BK3CR_M_B3S 0x7 << BK3CR_V_B3S +#define BK3CR_V_B3S0 8 +#define BK3CR_M_B3S0 1 << BK3CR_V_B3S0 +#define BK3CR_V_B3S1 9 +#define BK3CR_M_B3S1 1 << BK3CR_V_B3S1 +#define BK3CR_V_B3S2 10 +#define BK3CR_M_B3S2 1 << BK3CR_V_B3S2 +#define BK3CR_V_BANKEN3 11 +#define BK3CR_M_BANKEN3 1 << BK3CR_V_BANKEN3 +#define BK3CR_V_ENMDEN3N 12 +#define BK3CR_M_ENMDEN3N 1 << BK3CR_V_ENMDEN3N +#define BK3CR_V_COLADR3 13 +#define BK3CR_M_COLADR3 0xE << BK3CR_V_COLADR3 +#define BK3CR_V_COLADR30 13 +#define BK3CR_M_COLADR30 1 << BK3CR_V_COLADR30 +#define BK3CR_V_COLADR31 14 +#define BK3CR_M_COLADR31 1 << BK3CR_V_COLADR31 +#define BK3CR_V_COLADR32 15 +#define BK3CR_M_COLADR32 1 << BK3CR_V_COLADR32 + +/* +** Bank 3 DRAM Size +*/ +#define B3S_256KB 0x000 +#define B3S_512KB BK3CR_M_B3S0 +#define B3S_1MB BK3CR_M_B3S1 +#define B3S_2MB (BK3CR_M_B3S0 | BK3CR_M_B3S1) +#define B3S_4MB BK3CR_M_B3S2 +#define B3S_16MB (BK3CR_M_B3S1 | BK3CR_M_B3S2) + +/* +** Bank 3 Column Address Bits +*/ +#define COLADR3_8 0x000 +#define COLADR3_9 BK3CR_M_COLADR30 +#define COLADR3_10 BK3CR_M_COLADR31 +#define COLADR3_11 (BK3CR_M_COLADR30 | BK3CR_M_COLADR31) +#define COLADR3_12 BK3CR_M_COLADR32 + +/* +** +** Bank 2/3 Timing Control Register (BK23TCR) - Index 0x207 +** +** Loc Size Name Function +** ----- ---- ---- --------------------------------- +** <0> 1 B23WRCPW0 Bank 2/3 Write CAS Cycle Time 0 +** <1> 1 B23WRCPW1 Bank 2/3 Write CAS Cycle Time 1 +** <2> 1 MA23WRDLY Bank 2/3 Write MA Delay +** <3> 1 B23RDCPW0 Bank 2/3 Read CAS Cycle Time 0 +** <4> 1 B23RDCPW1 Bank 2/3 Read CAS Cycle Time 1 +** <5> 1 MA23RDDLY Bank 2/3 Read MA Delay +** <6> 1 B23CPRE Bank 2/3 CAS Precharge +** <7> 1 B23RTMA Bank 2/3 RAS to CAS Delay +** <8> 1 B23MATC Bank 2/3 MA to CAS Delay +** <9> 1 B23RPRE0 Bank 2/3 RAS Precharge Time 0 +** <10> 1 B23RPRE1 Bank 2/3 RAS Precharge Time 1 +** <11> 1 B23RPRE2 Bank 2/3 RAS Precharge Time 2 +** <13> 1 BNK23_ITL Bank 2/3 Interleave Enable +** +** <12><14:15> Reserved +*/ +#define DRAMCR_BK23TCR_REG 0x207 +#define DRAMCR_BK23TCR_INIT ( BK23TCR_M_B23WRCPW | BK23TCR_M_MA23WRDLY | \ + BK23TCR_M_B23RDCPW | BK23TCR_M_MA23RDDLY | \ + BK23TCR_M_B23CPRE | BK23TCR_M_B23RTMA | \ + BK23TCR_M_B23MATC | BK23TCR_M_B23RPRE ) +#define BK23TCR_V_B23WRCPW 0 +#define BK23TCR_M_B23WRCPW 0x3 << BK23TCR_V_B23WRCPW +#define BK23TCR_V_B23WRCPW0 0 +#define BK23TCR_M_B23WRCPW0 1 << BK23TCR_V_B23WRCPW0 +#define BK23TCR_V_B23WRCPW1 1 +#define BK23TCR_M_B23WRCPW1 1 << BK23TCR_V_B23WRCPW1 +#define BK23TCR_V_MA23WRDLY 2 +#define BK23TCR_M_MA23WRDLY 1 << BK23TCR_V_MA23WRDLY +#define BK23TCR_V_B23RDCPW 3 +#define BK23TCR_M_B23RDCPW 0x3 << BK23TCR_V_B23RDCPW +#define BK23TCR_V_B23RDCPW0 3 +#define BK23TCR_M_B23RDCPW0 1 << BK23TCR_V_B23RDCPW0 +#define BK23TCR_V_B23RDCPW1 4 +#define BK23TCR_M_B23RDCPW1 1 << BK23TCR_V_B23RDCPW1 +#define BK23TCR_V_MA23RDDLY 5 +#define BK23TCR_M_MA23RDDLY 1 << BK23TCR_V_MA23RDDLY +#define BK23TCR_V_B23CPRE 6 +#define BK23TCR_M_B23CPRE 1 << BK23TCR_V_B23CPRE +#define BK23TCR_V_B23RTMA 7 +#define BK23TCR_M_B23RTMA 1 << BK23TCR_V_B23RTMA +#define BK23TCR_V_B23MATC 8 +#define BK23TCR_M_B23MATC 1 << BK23TCR_V_B23MATC +#define BK23TCR_V_B23RPRE 9 +#define BK23TCR_M_B23RPRE 0x7 << BK23TCR_V_B23RPRE +#define BK23TCR_V_B23RPRE0 9 +#define BK23TCR_M_B23RPRE0 1 << BK23TCR_V_B23RPRE0 +#define BK23TCR_V_B23RPRE1 10 +#define BK23TCR_M_B23RPRE1 1 << BK23TCR_V_B23RPRE1 +#define BK23TCR_V_B23RPRE2 11 +#define BK23TCR_M_B23RPRE2 1 << BK23TCR_V_B23RPRE2 +#define BK23TCR_V_BNK23_ITL 13 +#define BK23TCR_M_BNK23_ITL 1 << BK23TCR_V_BNK23_ITL + +/* +** Bank 2/3 Write CAS Cycle Time +*/ +#define B23WRCPW_1T BK23TCR_M_B23WRCPW0 +#define B23WRCPW_2T BK23TCR_M_B23WRCPW1 +#define B23WRCPW_3T (BK23TCR_M_B23WRCPW0 | BK23TCR_M_B23WRCPW1) + +/* +** Bank 2/3 Read CAS Cycle Time +*/ +#define B23RDCPW_1T 0x000 +#define B23RDCPW_2T BK23TCR_M_B23RDCPW0 +#define B23RDCPW_3T BK23TCR_M_B23RDCPW1 +#define B23RDCPW_4T (BK23TCR_M_B23RDCPW0 | BK23TCR_M_B23RDCPW1) + +/* +** Bank 2/3 RAS Precharge Time +*/ +#define B23RPRE_1PT5T BK23TCR_M_B23RPRE1 +#define B23RPRE_2T (BK23TCR_M_B23RPRE0 | BK23TCR_M_B23RPRE1) +#define B23RPRE_2PT5T BK23TCR_M_B23RPRE2 +#define B23RPRE_3T (BK23TCR_M_B23RPRE0 | BK23TCR_M_B23RPRE2) +#define B23RPRE_3PT5T (BK23TCR_M_B23RPRE1 | BK23TCR_M_B23RPRE2) +#define B23RPRE_4T (BK23TCR_M_B23RPRE0 | BK23TCR_M_B23RPRE1 | BK23TCR_M_B23RPRE2) + +/* +** +** Bank 4 Control Register (BK4CR) - Index 0x208 +** +** Loc Size Name Function +** ----- ---- ---- --------------------------------- +** <0> 8 B4A Bank 4 Starting Address +** <8> 1 B4S0 Bank 4 DRAM Size 0 +** <9> 1 B4S1 Bank 4 DRAM Size 1 +** <10> 1 B4S2 Bank 4 DRAM Size 2 +** <11> 1 BANKEN4 Bank 4 Enable +** <12> 1 ENMDEN4N Enable MDEN# for Bank 4 +** <13> 1 COLADR40 Number of Column Address Bits for Bank 4 0 +** <14> 1 COLADR41 Number of Column Address Bits for Bank 4 1 +** <15> 1 COLADR42 Number of Column Address Bits for Bank 4 2 +** +*/ +#define DRAMCR_BK4CR_REG 0x208 +#define DRAMCR_BK4CR_INIT 0x0000 +#define BK4CR_V_B4A 0 +#define BK4CR_M_B4A 0xFF << BK4CR_V_B4A +#define BK4CR_V_B4S 8 +#define BK4CR_M_B4S 0x7 << BK4CR_V_B4S +#define BK4CR_V_B4S0 8 +#define BK4CR_M_B4S0 1 << BK4CR_V_B4S0 +#define BK4CR_V_B4S1 9 +#define BK4CR_M_B4S1 1 << BK4CR_V_B4S1 +#define BK4CR_V_B4S2 10 +#define BK4CR_M_B4S2 1 << BK4CR_V_B4S2 +#define BK4CR_V_BANKEN4 11 +#define BK4CR_M_BANKEN4 1 << BK4CR_V_BANKEN4 +#define BK4CR_V_ENMDEN4N 12 +#define BK4CR_M_ENMDEN4N 1 << BK4CR_V_ENMDEN4N +#define BK4CR_V_COLADR4 13 +#define BK4CR_M_COLADR4 0xE << BK4CR_V_COLADR4 +#define BK4CR_V_COLADR40 13 +#define BK4CR_M_COLADR40 1 << BK4CR_V_COLADR40 +#define BK4CR_V_COLADR41 14 +#define BK4CR_M_COLADR41 1 << BK4CR_V_COLADR41 +#define BK4CR_V_COLADR42 15 +#define BK4CR_M_COLADR42 1 << BK4CR_V_COLADR42 + +/* +** Bank 4 DRAM Size +*/ +#define B4S_256KB 0x000 +#define B4S_512KB BK4CR_M_B4S0 +#define B4S_1MB BK4CR_M_B4S1 +#define B4S_2MB (BK4CR_M_B4S0 | BK4CR_M_B4S1) +#define B4S_4MB BK4CR_M_B4S2 +#define B4S_16MB (BK4CR_M_B4S1 | BK4CR_M_B4S2) + +/* +** Bank 4 Column Address Bits +*/ +#define COLADR4_8 0x000 +#define COLADR4_9 BK4CR_M_COLADR40 +#define COLADR4_10 BK4CR_M_COLADR41 +#define COLADR4_11 (BK4CR_M_COLADR40 | BK4CR_M_COLADR41) +#define COLADR4_12 BK4CR_M_COLADR42 + +/* +** +** Bank 5 Control Register (BK5CR) - Index 0x209 +** +** Loc Size Name Function +** ----- ---- ---- --------------------------------- +** <0> 8 B5A Bank 5 Starting Address +** <8> 1 B5S0 Bank 5 DRAM Size 0 +** <9> 1 B5S1 Bank 5 DRAM Size 1 +** <10> 1 B5S2 Bank 5 DRAM Size 2 +** <11> 1 BANKEN5 Bank 5 Enable +** <12> 1 ENMDEN5N Enable MDEN# for Bank 5 +** <13> 1 COLADR50 Number of Column Address Bits for Bank 5 0 +** <14> 1 COLADR51 Number of Column Address Bits for Bank 5 1 +** <15> 1 COLADR52 Number of Column Address Bits for Bank 5 2 +** +*/ +#define DRAMCR_BK5CR_REG 0x209 +#define DRAMCR_BK5CR_INIT 0x0000 +#define BK5CR_V_B5A 0 +#define BK5CR_M_B5A 0xFF << BK5CR_V_B5A +#define BK5CR_V_B5S 8 +#define BK5CR_M_B5S 0x7 << BK5CR_V_B5S +#define BK5CR_V_B5S0 8 +#define BK5CR_M_B5S0 1 << BK5CR_V_B5S0 +#define BK5CR_V_B5S1 9 +#define BK5CR_M_B5S1 1 << BK5CR_V_B5S1 +#define BK5CR_V_B5S2 10 +#define BK5CR_M_B5S2 1 << BK5CR_V_B5S2 +#define BK5CR_V_BANKEN5 11 +#define BK5CR_M_BANKEN5 1 << BK5CR_V_BANKEN5 +#define BK5CR_V_ENMDEN5N 12 +#define BK5CR_M_ENMDEN5N 1 << BK5CR_V_ENMDEN5N +#define BK5CR_V_COLADR5 13 +#define BK5CR_M_COLADR5 0xE << BK5CR_V_COLADR5 +#define BK5CR_V_COLADR50 13 +#define BK5CR_M_COLADR50 1 << BK5CR_V_COLADR50 +#define BK5CR_V_COLADR51 14 +#define BK5CR_M_COLADR51 1 << BK5CR_V_COLADR51 +#define BK5CR_V_COLADR52 15 +#define BK5CR_M_COLADR52 1 << BK5CR_V_COLADR52 + +/* +** Bank 5 DRAM Size +*/ +#define B5S_256KB 0x000 +#define B5S_512KB BK5CR_M_B5S0 +#define B5S_1MB BK5CR_M_B5S1 +#define B5S_2MB (BK5CR_M_B5S0 | BK5CR_M_B5S1) +#define B5S_4MB BK5CR_M_B5S2 +#define B5S_16MB (BK5CR_M_B5S1 | BK5CR_M_B5S2) + +/* +** Bank 5 Column Address Bits +*/ +#define COLADR5_8 0x000 +#define COLADR5_9 BK5CR_M_COLADR50 +#define COLADR5_10 BK5CR_M_COLADR51 +#define COLADR5_11 (BK5CR_M_COLADR50 | BK5CR_M_COLADR51) +#define COLADR5_12 BK5CR_M_COLADR52 + +/* +** +** Bank 4/5 Timing Control Register (BK45TCR) - Index 0x20A +** +** Loc Size Name Function +** ----- ---- ---- --------------------------------- +** <0> 1 B45WRCPW0 Bank 4/5 Write CAS Cycle Time 0 +** <1> 1 B45WRCPW1 Bank 4/5 Write CAS Cycle Time 1 +** <2> 1 MA45WRDLY Bank 4/5 Write MA Delay +** <3> 1 B45RDCPW0 Bank 4/5 Read CAS Cycle Time 0 +** <4> 1 B45RDCPW1 Bank 4/5 Read CAS Cycle Time 1 +** <5> 1 MA45RDDLY Bank 4/5 Read MA Delay +** <6> 1 B45CPRE Bank 4/5 CAS Precharge +** <7> 1 B45RTMA Bank 4/5 RAS to CAS Delay +** <8> 1 B45MATC Bank 4/5 MA to CAS Delay +** <9> 1 B45RPRE0 Bank 4/5 RAS Precharge Time 0 +** <10> 1 B45RPRE1 Bank 4/5 RAS Precharge Time 1 +** <11> 1 B45RPRE2 Bank 4/5 RAS Precharge Time 2 +** <13> 1 BNK45_ITL Bank 4/5 Interleave Enable +** +** <12><14:15> Reserved +*/ +#define DRAMCR_BK45TCR_REG 0x20A +#define DRAMCR_BK45TCR_INIT ( BK45TCR_M_B45WRCPW | BK45TCR_M_MA45WRDLY | \ + BK45TCR_M_B45RDCPW | BK45TCR_M_MA45RDDLY | \ + BK45TCR_M_B45CPRE | BK45TCR_M_B45RTMA | \ + BK45TCR_M_B45MATC | BK45TCR_M_B45RPRE ) +#define BK45TCR_V_B45WRCPW 0 +#define BK45TCR_M_B45WRCPW 0x3 << BK45TCR_V_B45WRCPW +#define BK45TCR_V_B45WRCPW0 0 +#define BK45TCR_M_B45WRCPW0 1 << BK45TCR_V_B45WRCPW0 +#define BK45TCR_V_B45WRCPW1 1 +#define BK45TCR_M_B45WRCPW1 1 << BK45TCR_V_B45WRCPW1 +#define BK45TCR_V_MA45WRDLY 2 +#define BK45TCR_M_MA45WRDLY 1 << BK45TCR_V_MA45WRDLY +#define BK45TCR_V_B45RDCPW 3 +#define BK45TCR_M_B45RDCPW 0x3 << BK45TCR_V_B45RDCPW +#define BK45TCR_V_B45RDCPW0 3 +#define BK45TCR_M_B45RDCPW0 1 << BK45TCR_V_B45RDCPW0 +#define BK45TCR_V_B45RDCPW1 4 +#define BK45TCR_M_B45RDCPW1 1 << BK45TCR_V_B45RDCPW1 +#define BK45TCR_V_MA45RDDLY 5 +#define BK45TCR_M_MA45RDDLY 1 << BK45TCR_V_MA45RDDLY +#define BK45TCR_V_B45CPRE 6 +#define BK45TCR_M_B45CPRE 1 << BK45TCR_V_B45CPRE +#define BK45TCR_V_B45RTMA 7 +#define BK45TCR_M_B45RTMA 1 << BK45TCR_V_B45RTMA +#define BK45TCR_V_B45MATC 8 +#define BK45TCR_M_B45MATC 1 << BK45TCR_V_B45MATC +#define BK45TCR_V_B45RPRE 9 +#define BK45TCR_M_B45RPRE 0x7 << BK45TCR_V_B45RPRE +#define BK45TCR_V_B45RPRE0 9 +#define BK45TCR_M_B45RPRE0 1 << BK45TCR_V_B45RPRE0 +#define BK45TCR_V_B45RPRE1 10 +#define BK45TCR_M_B45RPRE1 1 << BK45TCR_V_B45RPRE1 +#define BK45TCR_V_B45RPRE2 11 +#define BK45TCR_M_B45RPRE2 1 << BK45TCR_V_B45RPRE2 +#define BK45TCR_V_BNK45_ITL 13 +#define BK45TCR_M_BNK45_ITL 1 << BK45TCR_V_BNK45_ITL + +/* +** Bank 4/5 Write CAS Cycle Time +*/ +#define B45WRCPW_1T BK45TCR_M_B45WRCPW0 +#define B45WRCPW_2T BK45TCR_M_B45WRCPW1 +#define B45WRCPW_3T (BK45TCR_M_B45WRCPW0 | BK45TCR_M_B45WRCPW1) + +/* +** Bank 4/5 Read CAS Cycle Time +*/ +#define B45RDCPW_1T 0x000 +#define B45RDCPW_2T BK45TCR_M_B45RDCPW0 +#define B45RDCPW_3T BK45TCR_M_B45RDCPW1 +#define B45RDCPW_4T (BK45TCR_M_B45RDCPW0 | BK45TCR_M_B45RDCPW1) + +/* +** Bank 4/5 RAS Precharge Time +*/ +#define B45RPRE_1PT5T BK45TCR_M_B45RPRE1 +#define B45RPRE_2T (BK45TCR_M_B45RPRE0 | BK45TCR_M_B45RPRE1) +#define B45RPRE_2PT5T BK45TCR_M_B45RPRE2 +#define B45RPRE_3T (BK45TCR_M_B45RPRE0 | BK45TCR_M_B45RPRE2) +#define B45RPRE_3PT5T (BK45TCR_M_B45RPRE1 | BK45TCR_M_B45RPRE2) +#define B45RPRE_4T (BK45TCR_M_B45RPRE0 | BK45TCR_M_B45RPRE1 | BK45TCR_M_B45RPRE2) + +/* +** +** DRAM Configuration Register 1 (DRAMCR1) - Index 0x20B +** +** Loc Size Name Function +** ----- ---- ---- --------------------------------- +** <0> 1 SIXRASEN Six RAS# Control Line Enable +** <3> 1 BRSTWREN Burst WRite Enable +** <4> 1 PS0 DRAM Page Size 0 +** <5> 1 PS1 DRAM Page Size 1 +** <6> 1 PS2 DRAM Page Size 2 +** <7> 1 FSTPHDEC Fast Page Hit Decode +** <9> 1 RONLYRF DRAM Refresh Scheme +** <10> 1 RFRPRE0 RAS Precharge Time for Refresh Cycles 0 +** <11> 1 RFRPRE1 RAS Precharge Time for Refresh Cycles 1 +** <12> 1 RFRPW0 RAS Pulse Width for Refresh Cycles 0 +** <13> 1 RFRPW1 RAS Pulse Width for Refresh Cycles 1 +** <14> 1 XWITDOFFR Extra Wait State for Lead-off Read Cycles +** <15> 1 XWITDOFFW Extra Wait State for Lead-off Write Cycles +** +** <1:2><8> Reserved +*/ +#define DRAMCR_DRAMCR1_REG 0x20B +#define DRAMCR_DRAMCR1_INIT ( DRAMCR1_M_XWITDOFFR | DRAMCR1_M_XWITDOFFW ) +#define DRAMCR1_V_SIXRASEN 0 +#define DRAMCR1_M_SIXRASEN 1 << DRAMCR1_V_SIXRASEN +#define DRAMCR1_V_BRSTWREN 3 +#define DRAMCR1_M_BRSTWREN 1 << DRAMCR1_V_BRSTWREN +#define DRAMCR1_V_PS 4 +#define DRAMCR1_M_PS 0x7 << DRAMCR1_V_PS +#define DRAMCR1_V_PS0 4 +#define DRAMCR1_M_PS0 1 << DRAMCR1_V_PS0 +#define DRAMCR1_V_PS1 5 +#define DRAMCR1_M_PS1 1 << DRAMCR1_V_PS1 +#define DRAMCR1_V_PS2 6 +#define DRAMCR1_M_PS2 1 << DRAMCR1_V_PS2 +#define DRAMCR1_V_FSTPHDEC 7 +#define DRAMCR1_M_FSTPHDEC 1 << DRAMCR1_V_FSTPHDEC +#define DRAMCR1_V_RONLYRF 9 +#define DRAMCR1_M_RONLYRF 1 << DRAMCR1_V_RONLYRF +#define DRAMCR1_V_RFRPRE 10 +#define DRAMCR1_M_RFRPRE 0x3 << DRAMCR1_V_RFRPRE +#define DRAMCR1_V_RFRPRE0 10 +#define DRAMCR1_M_RFRPRE0 1 << DRAMCR1_V_RFRPRE0 +#define DRAMCR1_V_RFRPRE1 11 +#define DRAMCR1_M_RFRPRE1 1 << DRAMCR1_V_RFRPRE1 +#define DRAMCR1_V_RFRPW 12 +#define DRAMCR1_M_RFRPW 0x3 << DRAMCR1_V_RFRPW +#define DRAMCR1_V_RFRPW0 12 +#define DRAMCR1_M_RFRPW0 1 << DRAMCR1_V_RFRPW0 +#define DRAMCR1_V_RFRPW1 13 +#define DRAMCR1_M_RFRPW1 1 << DRAMCR1_V_RFRPW1 +#define DRAMCR1_V_XWITDOFFR 14 +#define DRAMCR1_M_XWITDOFFR 1 << DRAMCR1_V_XWITDOFFR +#define DRAMCR1_V_XWITDOFFW 15 +#define DRAMCR1_M_XWITDOFFW 1 << DRAMCR1_V_XWITDOFFW + +/* +** DRAM Page Size +*/ +#define PS_1KB 0x000 +#define PS_2KB DRAMCR1_M_PS0 +#define PS_4KB DRAMCR1_M_PS1 +#define PS_8KB (DRAMCR1_M_PS0 | DRAMCR1_M_PS1) +#define PS_16KB DRAMCR1_M_PS2 +#define PS_32KB (DRAMCR1_M_PS0 | DRAMCR1_M_PS2) + +/* +** RAS Precharge Time for Refresh Cycles +*/ +#define RFRPRE_5T 0x000 +#define RFRPRE_4T DRAMCR1_M_RFRPRE0 +#define RFRPRE_3T DRAMCR1_M_RFRPRE1 +#define RFRPRE_2T (DRAMCR1_M_RFRPRE0 | DRAMCR1_M_RFRPRE1) + +/* +** RAS Pulse Width for Refresh Cycles +*/ +#define RFRPW_5T 0x000 +#define RFRPW_4T DRAMCR1_M_RFRPW0 +#define RFRPW_3T DRAMCR1_M_RFRPW1 +#define RFRPW_2T (DRAMCR1_M_RFRPW0 | DRAMCR1_M_RFRPW1) + +/* +** +** DRAM Configuration Register 2 (DRAMCR2) - Index 0x20C +** +** Loc Size Name Function +** ----- ---- ---- --------------------------------- +** <9> 1 ENPARADRL Enable Parity Error Address Latch +** <10> 1 ENPARCK0 Enable Parity Check for Bank 0 +** <11> 1 ENPARCK1 Enable Parity Check for Bank 1 +** <12> 1 ENPARCK2 Enable Parity Check for Bank 2 +** <13> 1 ENPARCK3 Enable Parity Check for Bank 3 +** <14> 1 ENPARCK4 Enable Parity Check for Bank 4 +** <15> 1 ENPARCK5 Enable Parity Check for Bank 5 +** +** <0:8> Reserved +*/ +#define DRAMCR_DRAMCR2_REG 0x20C +#define DRAMCR_DRAMCR2_INIT 0x0000 +#define DRAMCR2_V_ENPARADRL 9 +#define DRAMCR2_M_ENPARADRL 1 << DRAMCR2_V_ENPARADRL +#define DRAMCR2_V_ENPARCK0 10 +#define DRAMCR2_M_ENPARCK0 1 << DRAMCR2_V_ENPARCK0 +#define DRAMCR2_V_ENPARCK1 11 +#define DRAMCR2_M_ENPARCK1 1 << DRAMCR2_V_ENPARCK1 +#define DRAMCR2_V_ENPARCK2 12 +#define DRAMCR2_M_ENPARCK2 1 << DRAMCR2_V_ENPARCK2 +#define DRAMCR2_V_ENPARCK3 13 +#define DRAMCR2_M_ENPARCK3 1 << DRAMCR2_V_ENPARCK3 +#define DRAMCR2_V_ENPARCK4 14 +#define DRAMCR2_M_ENPARCK4 1 << DRAMCR2_V_ENPARCK4 +#define DRAMCR2_V_ENPARCK5 15 +#define DRAMCR2_M_ENPARCK5 1 << DRAMCR2_V_ENPARCK5 + +/* +** +** DRAM Configuration Register 3 (DRAMCR3) - Index 0x20D +** +** Loc Size Name Function +** ----- ---- ---- --------------------------------- +** <0> 1 RAS0DRV0 Driving Strength of RAS0# Output 0 +** <1> 1 RAS0DRV1 Driving Strength of RAS0# Output 1 +** <2> 1 RAS0DRV2 Driving Strength of RAS0# Output 2 +** <3> 1 RAS0DRV3 Driving Strength of RAS0# Output 3 +** <4> 1 RAS1DRV0 Driving Strength of RAS1# Output 0 +** <5> 1 RAS1DRV1 Driving Strength of RAS1# Output 1 +** <6> 1 RAS1DRV2 Driving Strength of RAS1# Output 2 +** <7> 1 RAS1DRV3 Driving Strength of RAS1# Output 3 +** <8> 1 RAS2DRV0 Driving Strength of RAS2# Output 0 +** <9> 1 RAS2DRV1 Driving Strength of RAS2# Output 1 +** <10> 1 RAS2DRV2 Driving Strength of RAS2# Output 2 +** <11> 1 RAS2DRV3 Driving Strength of RAS2# Output 3 +** <12> 1 RAS3DRV0 Driving Strength of RAS3# Output 0 +** <13> 1 RAS3DRV1 Driving Strength of RAS3# Output 1 +** <14> 1 RAS3DRV2 Driving Strength of RAS3# Output 2 +** <15> 1 RAS3DRV3 Driving Strength of RAS3# Output 3 +** +*/ +#define DRAMCR_DRAMCR3_REG 0x20D +#define DRAMCR_DRAMCR3_INIT ( DRAMCR3_M_RAS0DRV0 | DRAMCR3_M_RAS0DRV1 | \ + DRAMCR3_M_RAS0DRV2 | DRAMCR3_M_RAS1DRV0 | \ + DRAMCR3_M_RAS1DRV1 | DRAMCR3_M_RAS1DRV2 | \ + DRAMCR3_M_RAS2DRV0 | DRAMCR3_M_RAS2DRV1 | \ + DRAMCR3_M_RAS2DRV2 | DRAMCR3_M_RAS3DRV0 | \ + DRAMCR3_M_RAS3DRV1 | DRAMCR3_M_RAS3DRV2 ) +#define DRAMCR3_V_RAS0DRV 0 +#define DRAMCR3_M_RAS0DRV 0xF << DRAMCR3_V_RAS0DRV +#define DRAMCR3_V_RAS0DRV0 0 +#define DRAMCR3_M_RAS0DRV0 1 << DRAMCR3_V_RAS0DRV0 +#define DRAMCR3_V_RAS0DRV1 1 +#define DRAMCR3_M_RAS0DRV1 1 << DRAMCR3_V_RAS0DRV1 +#define DRAMCR3_V_RAS0DRV2 2 +#define DRAMCR3_M_RAS0DRV2 1 << DRAMCR3_V_RAS0DRV2 +#define DRAMCR3_V_RAS0DRV3 3 +#define DRAMCR3_M_RAS0DRV3 1 << DRAMCR3_V_RAS0DRV3 +#define DRAMCR3_V_RAS1DRV 4 +#define DRAMCR3_M_RAS1DRV 0xF << DRAMCR3_V_RAS1DRV +#define DRAMCR3_V_RAS1DRV0 4 +#define DRAMCR3_M_RAS1DRV0 1 << DRAMCR3_V_RAS1DRV0 +#define DRAMCR3_V_RAS1DRV1 5 +#define DRAMCR3_M_RAS1DRV1 1 << DRAMCR3_V_RAS1DRV1 +#define DRAMCR3_V_RAS1DRV2 6 +#define DRAMCR3_M_RAS1DRV2 1 << DRAMCR3_V_RAS1DRV2 +#define DRAMCR3_V_RAS1DRV3 7 +#define DRAMCR3_M_RAS1DRV3 1 << DRAMCR3_V_RAS1DRV3 +#define DRAMCR3_V_RAS2DRV 8 +#define DRAMCR3_M_RAS2DRV 0xF << DRAMCR3_V_RAS2DRV +#define DRAMCR3_V_RAS2DRV0 8 +#define DRAMCR3_M_RAS2DRV0 1 << DRAMCR3_V_RAS2DRV0 +#define DRAMCR3_V_RAS2DRV1 9 +#define DRAMCR3_M_RAS2DRV1 1 << DRAMCR3_V_RAS2DRV1 +#define DRAMCR3_V_RAS2DRV2 10 +#define DRAMCR3_M_RAS2DRV2 1 << DRAMCR3_V_RAS2DRV2 +#define DRAMCR3_V_RAS2DRV3 11 +#define DRAMCR3_M_RAS2DRV3 1 << DRAMCR3_V_RAS2DRV3 +#define DRAMCR3_V_RAS3DRV 12 +#define DRAMCR3_M_RAS3DRV 0xF << DRAMCR3_V_RAS3DRV +#define DRAMCR3_V_RAS3DRV0 12 +#define DRAMCR3_M_RAS3DRV0 1 << DRAMCR3_V_RAS3DRV0 +#define DRAMCR3_V_RAS3DRV1 13 +#define DRAMCR3_M_RAS3DRV1 1 << DRAMCR3_V_RAS3DRV1 +#define DRAMCR3_V_RAS3DRV2 14 +#define DRAMCR3_M_RAS3DRV2 1 << DRAMCR3_V_RAS3DRV2 +#define DRAMCR3_V_RAS3DRV3 15 +#define DRAMCR3_M_RAS3DRV3 1 << DRAMCR3_V_RAS3DRV3 + +/* +** Driving Strength of RAS0# Output (mA) +*/ +#define RAS0DRV_4MA DRAMCR3_M_RAS0DRV0 +#define RAS0DRV_8MA (DRAMCR3_M_RAS0DRV0 | DRAMCR3_M_RAS0DRV1) +#define RAS0DRV_12MA (DRAMCR3_M_RAS0DRV0 | DRAMCR3_M_RAS0DRV1 | DRAMCR3_M_RAS0DRV2 + +/* +** Driving Strength of RAS1# Output (mA) +*/ +#define RAS1DRV_4MA DRAMCR3_M_RAS1DRV0 +#define RAS1DRV_8MA (DRAMCR3_M_RAS1DRV0 | DRAMCR3_M_RAS1DRV1) +#define RAS1DRV_12MA (DRAMCR3_M_RAS1DRV0 | DRAMCR3_M_RAS1DRV1 | DRAMCR3_M_RAS1DRV2 + +/* +** Driving Strength of RAS2# Output (mA) +*/ +#define RAS2DRV_4MA DRAMCR3_M_RAS2DRV0 +#define RAS2DRV_8MA (DRAMCR3_M_RAS2DRV0 | DRAMCR3_M_RAS2DRV1) +#define RAS2DRV_12MA (DRAMCR3_M_RAS2DRV0 | DRAMCR3_M_RAS2DRV1 | DRAMCR3_M_RAS2DRV2 + +/* +** Driving Strength of RAS3# Output (mA) +*/ +#define RAS3DRV_4MA DRAMCR3_M_RAS3DRV0 +#define RAS3DRV_8MA (DRAMCR3_M_RAS3DRV0 | DRAMCR3_M_RAS3DRV1) +#define RAS3DRV_12MA (DRAMCR3_M_RAS3DRV0 | DRAMCR3_M_RAS3DRV1 | DRAMCR3_M_RAS3DRV2 + +/* +** +** DRAM Configuration Register 4 (DRAMCR4) - Index 0x20E +** +** Loc Size Name Function +** ----- ---- ---- --------------------------------- +** <0> 1 MADRV0 Driving Strength of MA Output 0 +** <1> 1 MADRV1 Driving Strength of MA Output 1 +** <2> 1 MADRV2 Driving Strength of MA Output 2 +** <3> 1 MADRV3 Driving Strength of MA Output 3 +** <4> 1 CASADRV0 Driving Strength of CASA Output 0 +** <5> 1 CASADRV1 Driving Strength of CASA Output 1 +** <6> 1 CASADRV2 Driving Strength of CASA Output 2 +** <7> 1 CASADRV3 Driving Strength of CASA Output 3 +** <8> 1 CASBDRV0 Driving Strength of CASB Output 0 +** <9> 1 CASBDRV1 Driving Strength of CASB Output 1 +** <10> 1 CASBDRV2 Driving Strength of CASB Output 2 +** <11> 1 CASBDRV3 Driving Strength of CASB Output 3 +** +*/ +#define DRAMCR_DRAMCR4_REG 0x20E +#define DRAMCR_DRAMCR4_INIT ( DRAMCR4_M_MADRV0 | DRAMCR4_M_MADRV1 | \ + DRAMCR4_M_MADRV2 | DRAMCR4_M_CASADRV0 | \ + DRAMCR4_M_CASADRV1 | DRAMCR4_M_CASADRV2 | \ + DRAMCR4_M_CASBDRV0 | DRAMCR4_M_CASBDRV1 | \ + DRAMCR4_M_CASBDRV2 ) +#define DRAMCR4_V_MADRV 0 +#define DRAMCR4_M_MADRV 0xF << DRAMCR4_V_MADRV +#define DRAMCR4_V_MADRV0 0 +#define DRAMCR4_M_MADRV0 1 << DRAMCR4_V_MADRV0 +#define DRAMCR4_V_MADRV1 1 +#define DRAMCR4_M_MADRV1 1 << DRAMCR4_V_MADRV1 +#define DRAMCR4_V_MADRV2 2 +#define DRAMCR4_M_MADRV2 1 << DRAMCR4_V_MADRV2 +#define DRAMCR4_V_MADRV3 3 +#define DRAMCR4_M_MADRV3 1 << DRAMCR4_V_MADRV3 +#define DRAMCR4_V_CASADRV 4 +#define DRAMCR4_M_CASADRV 0xF << DRAMCR4_V_CASADRV +#define DRAMCR4_V_CASADRV0 4 +#define DRAMCR4_M_CASADRV0 1 << DRAMCR4_V_CASADRV0 +#define DRAMCR4_V_CASADRV1 5 +#define DRAMCR4_M_CASADRV1 1 << DRAMCR4_V_CASADRV1 +#define DRAMCR4_V_CASADRV2 6 +#define DRAMCR4_M_CASADRV2 1 << DRAMCR4_V_CASADRV2 +#define DRAMCR4_V_CASADRV3 7 +#define DRAMCR4_M_CASADRV3 1 << DRAMCR4_V_CASADRV3 +#define DRAMCR4_V_CASBDRV 8 +#define DRAMCR4_M_CASBDRV 0xF << DRAMCR4_V_CASBDRV +#define DRAMCR4_V_CASBDRV0 8 +#define DRAMCR4_M_CASBDRV0 1 << DRAMCR4_V_CASBDRV0 +#define DRAMCR4_V_CASBDRV1 9 +#define DRAMCR4_M_CASBDRV1 1 << DRAMCR4_V_CASBDRV1 +#define DRAMCR4_V_CASBDRV2 10 +#define DRAMCR4_M_CASBDRV2 1 << DRAMCR4_V_CASBDRV2 +#define DRAMCR4_V_CASBDRV3 11 +#define DRAMCR4_M_CASBDRV3 1 << DRAMCR4_V_CASBDRV3 + +/* +** Driving Strength of MA Output (mA) +*/ +#define MADRV_4MA DRAMCR2_M_MADRV0 +#define MADRV_8MA (DRAMCR2_M_MADRV0 | DRAMCR2_M_MADRV1) +#define MADRV_12MA (DRAMCR2_M_MADRV0 | DRAMCR2_M_MADRV1 | DRAMCR2_M_MADRV2 + +/* +** Driving Strength of CASA Output (mA) +*/ +#define CASADRV_4MA DRAMCR2_M_CASADRV0 +#define CASADRV_8MA (DRAMCR2_M_CASADRV0 | DRAMCR2_M_CASADRV1) +#define CASADRV_12MA (DRAMCR2_M_CASADRV0 | DRAMCR2_M_CASADRV1 | DRAMCR2_M_CASADRV2 + +/* +** Driving Strength of CASB Output (mA) +*/ +#define CASBDRV_4MA DRAMCR2_M_CASBDRV0 +#define CASBDRV_8MA (DRAMCR2_M_CASBDRV0 | DRAMCR2_M_CASBDRV1) +#define CASBDRV_12MA (DRAMCR2_M_CASBDRV0 | DRAMCR2_M_CASBDRV1 | DRAMCR2_M_CASBDRV2 + +/* +** +** DRAM Configuration Register 5 (DRAMCR5) - Index 0x20F +** +** Loc Size Name Function +** ----- ---- ---- --------------------------------- +** <1> 1 FLASHENB Flash Enable +** <10> 1 ENC0ROMCS Enable ROMCS# for C0000H-C7FFFH Region +** <11> 1 ENC8ROMCS Enable ROMCS# for C8000H-CFFFFH Region +** <12> 1 END0ROMCS Enable ROMCS# for D0000H-D7FFFH Region +** <13> 1 END8ROMCS Enable ROMCS# for D8000H-DFFFFH Region +** <14> 1 ENE0ROMCS Enable ROMCS# for E0000H-E7FFFH Region +** <15> 1 ENE8ROMCS Enable ROMCS# for E8000H-EFFFFH Region +** +** <0><2:9> Reserved +*/ +#define DRAMCR_DRAMCR5_REG 0x20F +#define DRAMCR_DRAMCR5_INIT 0x0000 +#define DRAMCR5_V_FLASHENB 0 +#define DRAMCR5_M_FLASHENB 1 << DRAMCR5_V_FLASHENB +#define DRAMCR5_V_ENC0ROMCS 10 +#define DRAMCR5_M_ENC0ROMCS 1 << DRAMCR5_V_ENC0ROMCS +#define DRAMCR5_V_ENC8ROMCS 11 +#define DRAMCR5_M_ENC8ROMCS 1 << DRAMCR5_V_ENC8ROMCS +#define DRAMCR5_V_END0ROMCS 12 +#define DRAMCR5_M_END0ROMCS 1 << DRAMCR5_V_ENC0ROMCS +#define DRAMCR5_V_END8ROMCS 13 +#define DRAMCR5_M_END8ROMCS 1 << DRAMCR5_V_ENC8ROMCS +#define DRAMCR5_V_ENE0ROMCS 14 +#define DRAMCR5_M_ENE0ROMCS 1 << DRAMCR5_V_ENC0ROMCS +#define DRAMCR5_V_ENE8ROMCS 15 +#define DRAMCR5_M_ENE8ROMCS 1 << DRAMCR5_V_ENC8ROMCS + +/* +** Cache Controller Registers +** +*/ + +/* +** +** Cache Control Register 1 (CCR1) - Index 0x400 +** +** Loc Size Name Function +** ----- ---- ---- --------------------------------- +** <0> 1 L2CST0 Level 2 Cache Status 0 +** <1> 1 L2CST1 Level 2 Cache Status 1 +** <2> 1 L2CST2 Level 2 Cache Status 2 +** <3> 1 L2CST3 Level 2 Cache Status 3 +** <4> 1 CSIZE0 Level 2 Cache Data 0 +** <5> 1 CSIZE1 Level 2 Cache Data 1 +** <6> 1 CSIZE2 Level 2 Cache Data 2 +** <7> 1 CSIZE3 Level 2 Cache Data 3 +** <8> 1 L1WB Enable Level 1 Write Back Support +** <9> 1 WPL2KEN L2 Cache Write Protect +** +** <10:15> Reserved +*/ +#define CCR_CCR1_REG 0x400 +#define CCR1_V_L2CST 0 +#define CCR1_M_L2CST 0xF << CCR1_V_L2CST +#define CCR1_V_L2CST0 0 +#define CCR1_M_L2CST0 1 << CCR1_V_L2CST0 +#define CCR1_V_L2CST1 1 +#define CCR1_M_L2CST1 1 << CCR1_V_L2CST1 +#define CCR1_V_L2CST2 2 +#define CCR1_M_L2CST2 1 << CCR1_V_L2CST2 +#define CCR1_V_L2CST3 3 +#define CCR1_M_L2CST3 1 << CCR1_V_L2CST3 +#define CCR1_V_CSIZE 4 +#define CCR1_M_CSIZE 0xF << CCR1_V_CSIZE +#define CCR1_V_CSIZE0 4 +#define CCR1_M_CSIZE0 1 << CCR1_V_CSIZE0 +#define CCR1_V_CSIZE1 5 +#define CCR1_M_CSIZE1 1 << CCR1_V_CSIZE1 +#define CCR1_V_CSIZE2 6 +#define CCR1_M_CSIZE2 1 << CCR1_V_CSIZE2 +#define CCR1_V_CSIZE3 7 +#define CCR1_M_CSIZE3 1 << CCR1_V_CSIZE3 +#define CCR1_V_L1WB 8 +#define CCR1_M_L1WB 1 << CCR1_V_L1WB +#define CCR1_V_WPL2KEN 9 +#define CCR1_M_WPL2KEN 1 << CCR1_V_WPL2KEN + +/* +** Level 2 Cache Status +*/ +#define L2CST_STNDBY 0x0000 +#define L2CST_INIT CCR1_M_L2CST0 +#define L2CST_WRTHRU CCR1_M_L2CST1 +#define L2CST_WRBACK (CCR1_M_L2CST0 | CCR1_M_L2CST1) +#define L2CST_FLUSH CCR1_M_L2CST2 +#define L2CST_WRTHRUDR (CCR1_M_L2CST0 | CCR1_M_L2CST2) +#define L2CST_WRBACKDR (CCR1_M_L2CST1 | CCR1_M_L2CST2) + +/* +** Level 2 Cache Size +*/ +#define CSIZE_64KB_2BNK CCR1_M_CSIZE0 +#define CSIZE_128KB_1BNK CCR1_M_CSIZE1 +#define CSIZE_256KB_2BNK (CCR1_M_CSIZE0 | CCR1_M_CSIZE1) +#define CSIZE_512KB_1BNK CCR1_M_CSIZE2 +#define CSIZE_1MB_2BNK (CCR1_M_CSIZE0 | CCR1_M_CSIZE2) +#define CSIZE_256KB_1BNK (CCR1_M_CSIZE0 | CCR1_M_CSIZE1 | CCR1_M_CSIZE3) + +/* +** +** Cache Control Register 2 (CCR2) - Index 0x401 +** +** Loc Size Name Function +** ----- ---- ---- --------------------------------- +** <0> 1 TWIDTH Width of L2 Cache TAG Data +** <1> 1 DTYEN Configuration of L2 Cache TAG Field +** <2> 1 DRTWEN Configuration of L2 Cache TAG Write +** <7> 1 EHITEN External Comparator is Used +** +** <3:6><8:15> Reserved +*/ +#define CCR_CCR2_REG 0x401 +#define CCR2_V_TWIDTH 0 +#define CCR2_M_TWIDTH 1 << CCR2_V_TWIDTH +#define CCR2_V_DTYEN 1 +#define CCR2_M_DTYEN 1 << CCR2_V_DTYEN +#define CCR2_V_DRTWEN 2 +#define CCR2_M_DRTWEN 1 << CCR2_V_DRTWEN +#define CCR2_V_EHITEN 7 +#define CCR2_M_EHITEN 1 << CCR2_V_EHITEN + +/* +** +** Cache Control Register 3 (CCR3) - Index 0x402 +** +** Loc Size Name Function +** ----- ---- ---- --------------------------------- +** <0> 1 RDL0 CPU Cache Read Lead-off Cycles 0 +** <1> 1 RDL1 CPU Cache Read Lead-off Cycles 1 +** <2> 1 RDB2T CPU Cache Read Burst Cycles +** <3> 1 WRL0 CPU Cache Write Lead-off Cycles 0 +** <4> 1 WRL1 CPU Cache Write Lead-off Cycles 1 +** <5> 1 WRB2T CPU Cache Write Burst Cycles +** <6> 1 WRTEG0 Cache Write Enable Trailing Edge Timing 0 +** <7> 1 WRTEG1 Cache Write Enable Trailing Edge Timing 1 +** <8> 1 RDTEG0 Cache Write Enable Trailing Edge Timing 0 +** <9> 1 RDTEG1 Cache Write Enable Trailing Edge Timing 1 +** +** <10:15> Reserved +*/ +#define CCR_CCR3_REG 0x402 +#define CCR3_V_RDL 0 +#define CCR3_M_RDL 0x3 << CCR3_V_RDL +#define CCR3_V_RDL0 0 +#define CCR3_M_RDL0 1 << CCR3_V_RDL0 +#define CCR3_V_RDL1 2 +#define CCR3_M_RDL1 1 << CCR3_V_RDL1 +#define CCR3_V_RDB2T 3 +#define CCR3_M_RDB2T 1 << CCR3_V_RDB2T +#define CCR3_V_WRL 3 +#define CCR3_M_WRL 0x3 << CCR3_V_WRL +#define CCR3_V_WRL0 3 +#define CCR3_M_WRL0 1 << CCR3_V_WRL0 +#define CCR3_V_WRL1 4 +#define CCR3_M_WRL1 1 << CCR3_V_WRL1 +#define CCR3_V_WRB2T 5 +#define CCR3_M_WRB2T 1 << CCR3_V_WRB2T +#define CCR3_V_WRTEG 6 +#define CCR3_M_WRTEG 0x3 << CCR3_V_WRTEG +#define CCR3_V_WRTEG0 6 +#define CCR3_M_WRTEG0 1 << CCR3_V_WRTEG0 +#define CCR3_V_WRTEG1 7 +#define CCR3_M_WRTEG1 1 << CCR3_V_WRTEG1 +#define CCR3_V_RDTEG 8 +#define CCR3_M_RDTEG 0x3 << CCR3_V_RDTEG +#define CCR3_V_RDTEG0 8 +#define CCR3_M_RDTEG0 1 << CCR3_V_RDTEG0 +#define CCR3_V_RDTEG1 9 +#define CCR3_M_RDTEG1 1 << CCR3_V_RDTEG1 + +/* +** CPU Cache Read Lead-off Cycles +*/ +#define RDL_2T 0x000 +#define RDL_3T CCR3_M_RDL0 +#define RDL_4T CCR3_M_RDL1 + +/* +** CPU Cache Write Lead-off Cycles +*/ +#define WRL_2T 0x000 +#define WRL_3T CCR3_M_WRL0 +#define WRL_4T CCR3_M_WRL1 + +/* +** Cache Write Enable Trailing Edge Timing for Write Hit Cycles +*/ +#define WRTEG_SYNCH 0x000 +#define WRTEG_EARLY CCR3_M_WRTEG0 + +/* +** Cache Write Enable Trailing Edge Timing for Line Fill Cycles +*/ +#define RDTEG_SYNCH 0x000 +#define RDTEG_EARLY CCR3_M_RDTEG0 + +/* +** +** Cache Control Register 4 (CCR4) - Index 0x403 +** +** Loc Size Name Function +** ----- ---- ---- --------------------------------- +** <1> 1 TAGCK0 TAG RAM Timing Checking Point 0 +** <2> 1 TAGCK1 TAG RAM Timing Checking Point 1 +** <3> 1 DRTWETR0 Dirty Bit Write Timing Point 0 +** <4> 1 DRTWETR1 Dirty Bit Write Timing Point 1 +** +** <0><5:15> Reserved +*/ +#define CCR_CCR4_REG 0x403 +#define CCR4_V_TAGCK 0 +#define CCR4_M_TAGCK 0x3 << CCR4_V_TAGCK +#define CCR4_V_TAGCK0 0 +#define CCR4_M_TAGCK0 1 << CCR4_V_TAGCK0 +#define CCR4_V_TAGCK1 1 +#define CCR4_M_TAGCK1 1 << CCR4_V_TAGCK1 +#define CCR4_V_DRTWETR 0 +#define CCR4_M_DRTWETR 0x3 << CCR4_V_DRTWETR +#define CCR4_V_DRTWETR0 0 +#define CCR4_M_DRTWETR0 1 << CCR4_V_DRTWETR0 +#define CCR4_V_DRTWETR1 1 +#define CCR4_M_DRTWETR1 1 << CCR4_V_DRTWETR1 + +/* +** TAG RAM Timing Checking Point +*/ +#define TAGCK_ENDT1 0x000 +#define TAGCK_MIDT2_EARLY CCR4_M_TAGCK0 +#define TAGCK_MIDT2_NORM CCR4_M_TAGCK1 +#define TAGCK_ENDT2 (CCR4_M_TAGCK0 | CCR4_M_TAGCK1) + +/* +** Dirty Bit Write Enable Trailing Edge Timing Point +*/ +#define DRTWETR_EARLYEST CCR4_M_DRTWETR0 +#define DRTWETR_EARLYER CCR4_M_DRTWETR1 +#define DRTWETR_SYNCH (CCR4_M_DRTWETR0 | CCR4_M_DRTWETR1) + +/* +** +** Global Control Register 1 (GCR1) - Index 0x700 +** +** Loc Size Name Function +** ----- ---- ---- --------------------------------- +** <0> 1 CPUHITMWS CPU HITM# Sampling Wait State Selection +** +** <2:15> Reserved +*/ +#define CCR_GCR1_REG 0x700 +#define CCR_GCR1_INIT 0x0000 +#define GCR1_V_CPUHITMWS 0 +#define GCR1_M_CPUHITMWS 1 << GCR1_V_CPUHITMWS + +/**************************************************** +** SEQUOIA-2 ** +*****************************************************/ + +/* +** +** AT Miscellaneous Control Register 1 (ATMCR1) - Index 0x300 +** +** Loc Size Name Function +** ----- ---- ---- --------------------------------- +** <0> 1 SYSDIV0 SYSCLK Divisor Select 0 +** <1> 1 SYSDIV1 SYSCLK Divisor Select 1 +** <2> 1 SYSDIV2 SYSCLK Divisor Select 2 +** <4> 1 IDERDYDLY0 Turbo IDE Cycle Ready Delay Select 0 +** <5> 1 IDERDYDLY1 Turbo IDE Cycle Ready Delay Select 1 +** <6> 1 B2BD0 Back-to-Back I/O Delay Select 0 +** <7> 1 B2BD1 Back-to-Back I/O Delay Select 1 +** <9> 1 PARITYEN Global Parity Enable +** <10> 1 ATREFDIS AT Bus Refresh Disable +** <11> 1 HIDREFEN Hidden AT Refresh Enable +** +** <3><8><12:15> Reserved +*/ +#define SEQ2_ATMCR_REG 0x300 +#define SEQ2_ATMCR_INIT ( SYSDIV_4 | IDERDYDLY_2FS1XCLK | B2BD_3 | \ + ATMCR1_M_ATREFDIS | ATMCR1_M_HIDREFEN ) +#define ATMCR1_V_SYSDIV 0 +#define ATMCR1_M_SYSDIV 0x7 << ATMCR1_V_SYSDIV +#define ATMCR1_V_SYSDIV0 0 +#define ATMCR1_M_SYSDIV0 1 << ATMCR1_V_SYSDIV0 +#define ATMCR1_V_SYSDIV1 1 +#define ATMCR1_M_SYSDIV1 1 << ATMCR1_V_SYSDIV1 +#define ATMCR1_V_SYSDIV2 2 +#define ATMCR1_M_SYSDIV2 1 << ATMCR1_V_SYSDIV2 +#define ATMCR1_V_IDERDYDLY 4 +#define ATMCR1_M_IDERDYDLY 0x3 << ATMCR1_V_IDERDYDLY +#define ATMCR1_V_IDERDYDLY0 4 +#define ATMCR1_M_IDERDYDLY0 1 << ATMCR1_V_IDERDYDLY0 +#define ATMCR1_V_IDERDYDLY1 5 +#define ATMCR1_M_IDERDYDLY1 1 << ATMCR1_V_IDERDYDLY1 +#define ATMCR1_V_B2BD 6 +#define ATMCR1_M_B2BD 0x3 << ATMCR1_V_B2BD +#define ATMCR1_V_B2BD0 6 +#define ATMCR1_M_B2BD0 1 << ATMCR1_V_B2BD0 +#define ATMCR1_V_B2BD1 7 +#define ATMCR1_M_B2BD1 1 << ATMCR1_V_B2BD1 +#define ATMCR1_V_PARITYEN 9 +#define ATMCR1_M_PARITYEN 1 << ATMCR1_V_PARITYEN +#define ATMCR1_V_ATREFDIS 10 +#define ATMCR1_M_ATREFDIS 1 << ATMCR1_V_ATREFDIS +#define ATMCR1_V_HIDREFEN 11 +#define ATMCR1_M_HIDREFEN 1 << ATMCR1_V_HIDREFEN + +/* +** SYSCLK Divisor Select +*/ +#define SYSDIV_3 ATMCR1_M_SYSDIV0 +#define SYSDIV_4 ATMCR1_M_SYSDIV1 +#define SYSDIV_5 (ATMCR1_M_SYSDIV0 | ATMCR1_M_SYSDIV1) +#define SYSDIV_6 ATMCR1_M_SYSDIV2 + +/* +** Turbo IDE Cycle Ready Delay Select +*/ +#define IDERDYDLY_NONE 0x000 +#define IDERDYDLY_1FS1XCLK ATMCR1_M_IDERDYDLY0 +#define IDERDYDLY_2FS1XCLK ATMCR1_M_IDERDYDLY1 + +/* +** Back-to-Back Delay Select +*/ +#define B2BD_0 0x000 +#define B2BD_1 ATMCR1_M_B2BD0 +#define B2BD_2 ATMCR1_M_B2BD1 +#define B2BD_3 (ATMCR1_M_B2BD0 | ATMCR1_M_B2BD1) + +/* +** +** AT Miscellaneous Control Register 2 (ATMCR2) - Index 0x301 +** +** Loc Size Name Function +** ----- ---- ---- --------------------------------- +** <0> 1 IDECMDW0 Turbo IDE Command Width Select 0 +** <1> 1 IDECMDW1 Turbo IDE Command Width Select 1 +** <2> 1 IDECMDW2 Turbo IDE Command Width Select 2 +** <3> 1 IDEB2BDLY0 Turbo IDE Back-to-Back Cycle Delay Select 0 +** <4> 1 IDEB2BDLY1 Turbo IDE Back-to-Back Cycle Delay Select 1 +** <5> 1 IDEB2BDLY2 Turbo IDE Back-to-Back Cycle Delay Select 2 +** <6> 1 GIDENABLE Global IDE Enable +** <11> 1 EXTATADD Extended AT Address +** <12> 1 DLYLOCAL Delay Sampling Point for LOCAL# +** <14> 1 BSEREN BSER Enable +** <15> 1 DMACLKDIS DMA Modular Clock Disable +** +** <7:10><13> Reserved +*/ +#define SEQ2_ATMCR2_REG 0x301 +#define SEQ2_ATMCR2_INIT ( ATMCR2_M_IDECMDW | ATMCR2_M_IDEB2BDLY | \ + ATMCR2_M_IDEB2BDLY1 | ATMCR2_M_IDEB2BDLY2 | \ + ATMCR2_M_GIDENABLE | ATMCR2_M_EXTATADD | \ + ATMCR2_M_DLYLOCAL | ATMCR2_M_BSEREN ) +#define ATMCR2_V_IDECMDW 0 +#define ATMCR2_M_IDECMDW (0x7 << ATMCR2_V_IDECMDW) +#define ATMCR2_V_IDECMDW0 0 +#define ATMCR2_M_IDECMDW0 (1 << ATMCR2_V_IDECMDW0) +#define ATMCR2_V_IDECMDW1 1 +#define ATMCR2_M_IDECMDW1 (1 << ATMCR2_V_IDECMDW1) +#define ATMCR2_V_IDECMDW2 2 +#define ATMCR2_M_IDECMDW2 (1 << ATMCR2_V_IDECMDW2) +#define ATMCR2_V_IDEB2BDLY 3 +#define ATMCR2_M_IDEB2BDLY (0x7 << ATMCR2_V_IDEB2BDLY) +#define ATMCR2_V_IDEB2BDLY0 3 +#define ATMCR2_M_IDEB2BDLY0 (1 << ATMCR2_V_IDEB2BDLY0) +#define ATMCR2_V_IDEB2BDLY1 4 +#define ATMCR2_M_IDEB2BDLY1 (1 << ATMCR2_V_IDEB2BDLY1) +#define ATMCR2_V_IDEB2BDLY2 5 +#define ATMCR2_M_IDEB2BDLY2 (1 << ATMCR2_V_IDEB2BDLY2) +#define ATMCR2_V_GIDENABLE 6 +#define ATMCR2_M_GIDENABLE (1 << ATMCR2_V_GIDENABLE) +#define ATMCR2_V_EXTATADD 11 +#define ATMCR2_M_EXTATADD (1 << ATMCR2_V_EXTATADD) +#define ATMCR2_V_DLYLOCAL 12 +#define ATMCR2_M_DLYLOCAL (1 << ATMCR2_V_DLYLOCAL) +#define ATMCR2_V_BSEREN 14 +#define ATMCR2_M_BSEREN (1 << ATMCR2_V_BSEREN) +#define ATMCR2_V_DMACLKDIS 15 +#define ATMCR2_M_DMACLKDIS (1 << ATMCR2_V_DMACLKDIS) + +/* +** Turbo IDE Command Width Select +*/ +#define IDECMDW_2FS1XCLK 0x000 +#define IDECMDW_3FS1XCLK ATMCR2_M_IDECMDW0 +#define IDECMDW_4FS1XCLK ATMCR2_M_IDECMDW1 +#define IDECMDW_5FS1XCLK (ATMCR2_M_IDECMDW0 | ATMCR2_M_IDECMDW1) +#define IDECMDW_6FS1XCLK ATMCR2_M_IDECMDW2 +#define IDECMDW_7FS1XCLK (ATMCR2_M_IDECMDW0 | ATMCR2_M_IDECMDW2) +#define IDECMDW_8FS1XCLK (ATMCR2_M_IDECMDW1 | ATMCR2_M_IDECMDW2) +#define IDECMDW_9FS1XCLK (ATMCR2_M_IDECMDW0 | ATMCR2_M_IDECMDW1 | ATMCR2_M_IDECMDW2) + +/* +** Turbo IDE Back=to-Back Cycle Delay Select +*/ +#define IDEB2BDLY_2FS1XCLK 0x000 +#define IDEB2BDLY_3FS1XCLK ATMCR2_M_IDEB2BDLY0 +#define IDEB2BDLY_4FS1XCLK ATMCR2_M_IDEB2BDLY1 +#define IDEB2BDLY_5FS1XCLK (ATMCR2_M_IDEB2BDLY0 | ATMCR2_M_IDEB2BDLY1) +#define IDEB2BDLY_6FS1XCLK ATMCR2_M_IDEB2BDLY2 +#define IDEB2BDLY_7FS1XCLK (ATMCR2_M_IDEB2BDLY0 | ATMCR2_M_IDEB2BDLY2) +#define IDEB2BDLY_8FS1XCLK (ATMCR2_M_IDEB2BDLY1 | ATMCR2_M_IDEB2BDLY2) +#define IDEB2BDLY_9FS1XCLK (ATMCR2_M_IDEB2BDLY0 | ATMCR2_M_IDEB2BDLY1 | ATMCR2_M_IDEB2BDLY2) + +/* +** +** SEQUOIA-2 Pin Select Register (SEQ2PSR) - Index 0x302 +** +** Loc Size Name Function +** ----- ---- ---- --------------------------------- +** <0> 1 DPBUSEN DP Bus Enable +** <1> 1 GPIOPINEN General Purpose I/O [7:4] Pin Enable +** <4> 1 IDEPINEN IDE Pin Enable +** <5> 1 LOCALPINEN Additional LOCAL Pin Enable +** <8> 1 ATREFADDEN AT Refresh Address Enable +** <14> 1 IDECMDEN IDE Command Enable +** <15> 1 SQ2TYPESEL SEQUOIA-2 Type Select +** +** <2:3><6:7><9:13> Reserved +*/ +#define SEQ2_SEQ2PSR_REG 0x302 +#define SEQ2_SEQ2PSR_INIT ( SEQ2PSR_M_DPBUSEN | SEQ2PSR_M_LOCALPINEN ) +#define SEQ2PSR_V_DPBUSEN 0 +#define SEQ2PSR_M_DPBUSEN 1 << SEQ2PSR_V_DPBUSEN +#define SEQ2PSR_V_GPIOPINEN 1 +#define SEQ2PSR_M_GPIOPINEN 1 << SEQ2PSR_V_GPIOPINEN +#define SEQ2PSR_V_IDEPINEN 4 +#define SEQ2PSR_M_IDEPINEN 1 << SEQ2PSR_V_IDEPINEN +#define SEQ2PSR_V_LOCALPINEN 5 +#define SEQ2PSR_M_LOCALPINEN 1 << SEQ2PSR_V_LOCALPINEN +#define SEQ2PSR_V_ATREFADDEN 8 +#define SEQ2PSR_M_ATREFADDEN 1 << SEQ2PSR_V_ATREFADDEN +#define SEQ2PSR_V_IDECMDEN 14 +#define SEQ2PSR_M_IDECMDEN 1 << SEQ2PSR_V_IDECMDEN +#define SEQ2PSR_V_SQ2TYPESEL 15 +#define SEQ2PSR_M_SQ2TYPESEL 1 << SEQ2PSR_V_SQ2TYPESEL + +/* +** +** Modular Clock Control Register (MCLKCR) - Index 0x303 +** +** Loc Size Name Function +** ----- ---- ---- --------------------------------- +** <0> 1 ATMODCLKEN AT Modular Clock Enable +** <3> 1 SYNCTMREN Synchronous Timer Enable +** <4> 1 TMRCLKDIS Timer Clock Disable +** <5> 1 SYSCLKDIS ISA SYSCLK Disable +** +** <1:2><6:15> Reserved +*/ +#define SEQ2_MCLKCR_REG 0x303 +#define SEQ2_MCLKCR_INIT 0x0000 +#define MCLKCR_V_ATMODCLKEN 0 +#define MCLKCR_M_ATMODCLKEN 1 << MCLKCR_V_ATMODCLKEN +#define MCLKCR_V_SYNCTMREN 3 +#define MCLKCR_M_SYNCTMREN 1 << MCLKCR_V_SYNCTMREN +#define MCLKCR_V_TMRCLKDIS 4 +#define MCLKCR_M_TMRCLKDIS 1 << MCLKCR_V_TMRCLKDIS +#define MCLKCR_V_SYSCLKDIS 5 +#define MCLKCR_M_SYSCLKDIS 1 << MCLKCR_V_SYSCLKDIS + +/* +** +** Optional GPIO Control Register (OGPIOCR) - Index 0x304 +** +** Loc Size Name Function +** ----- ---- ---- --------------------------------- +** <0:7> 8 Reserved +** <8> 4 GPIODATA General Purpose I/O Data [4:7] +** <12> 4 GPIODIR General Purpose I/O Direction [4:7] +** +*/ +#define SEQ2_OGPIOCR_REG 0x304 +#define SEQ2_OGPIOCR_INIT OGPIOCR_M_GPIODIR +#define OOGPIOCR_V_GPIODATA 8 +#define OGPIOCR_M_GPIODATA 0xF << OGPIOCR_V_GPIODATA +#define OGPIOCR_V_GPIODATA4 8 +#define OGPIOCR_M_GPIODATA4 1 << OGPIOCR_V_GPIODATA4 +#define OGPIOCR_V_GPIODATA5 9 +#define OGPIOCR_M_GPIODATA5 1 << OGPIOCR_V_GPIODATA5 +#define OGPIOCR_V_GPIODATA6 10 +#define OGPIOCR_M_GPIODATA6 1 << OGPIOCR_V_GPIODATA6 +#define OGPIOCR_V_GPIODATA7 11 +#define OGPIOCR_M_GPIODATA7 1 << OGPIOCR_V_GPIODATA7 +#define OGPIOCR_V_GPIODIR 12 +#define OGPIOCR_M_GPIODIR 0xF << OGPIOCR_V_GPIODIR +#define OGPIOCR_V_GPIODIR4 12 +#define OGPIOCR_M_GPIODIR4 1 << OGPIOCR_V_GPIODIR4 +#define OGPIOCR_V_GPIODIR5 13 +#define OGPIOCR_M_GPIODIR5 1 << OGPIOCR_V_GPIODIR5 +#define OGPIOCR_V_GPIODIR6 14 +#define OGPIOCR_M_GPIODIR6 1 << OGPIOCR_V_GPIODIR6 +#define OGPIOCR_V_GPIODIR7 15 +#define OGPIOCR_M_GPIODIR7 1 << OGPIOCR_V_GPIODIR7 + +/* +** +** SEQUOIA-2 ID Register (SEQ2IDR) - Index 0x310 +** +** Loc Size Name Function +** ----- ---- ---- --------------------------------- +** <0> 4 S2ID SEQUOIA-2 Revision ID Number +** +** <1:15> Reserved +*/ +#define SEQ2_SEQ2IDR_REG 0x310 +#define SEQ2IDR_V_S2ID 0 +#define SEQ2IDR_M_S2ID 0xF << SEQ2IDR_V_S2ID + +/* +** +** Miscellaneous DMA Control Register 1 (MDMACR1) - Index 0x330 +** +** Loc Size Name Function +** ----- ---- ---- --------------------------------- +** <8> 1 ENCDDMA Encoded DMA Acknowledges +** +** <0:7><9:15> Reserved +*/ +#define SEQ2_MDMACR1_REG 0x330 +#define SEQ2_MDMACR1_INIT 0x0000 +#define MDMACR1_V_ENCDDMA 8 +#define MDMACR1_M_ENCDDMA 1 << MDMACR1_V_ENCDDMA + +/* +** +** Miscellaneous DMA Control Register 2 (MDMACR2) - Index 0x331 +** +** Loc Size Name Function +** ----- ---- ---- --------------------------------- +** <0> 1 SEL3DMA Select 3 DMA +** <4> 1 DMA0CHSEL0 DMA Channel 0 Select 0 +** <5> 1 DMA0CHSEL1 DMA Channel 0 Select 1 +** <6> 1 DMA0CHSEL2 DMA Channel 0 Select 2 +** <8> 1 DMA1CHSEL0 DMA Channel 1 Select 0 +** <9> 1 DMA1CHSEL1 DMA Channel 1 Select 1 +** <10> 1 DMA1CHSEL2 DMA Channel 1 Select 2 +** <12> 1 DMA2CHSEL0 DMA Channel 2 Select 0 +** <13> 1 DMA2CHSEL1 DMA Channel 2 Select 1 +** <14> 1 DMA2CHSEL2 DMA Channel 2 Select 2 +** +** <1:3><7><11><15> Reserved +*/ +#define SEQ2_MDMACR2_REG 0x331 +#define SEQ2_MDMACR2_INIT 0x0000 +#define MDMACR2_V_SEL3DMA 0 +#define MDMACR2_M_SEL3DMA 1 << MDMACR2_V_SEL3DMA +#define MDMACR2_V_DMA0CHSEL 4 +#define MDMACR2_M_DMA0CHSEL 0x7 << MDMACR2_V_DMA0CHSEL +#define MDMACR2_V_DMA0CHSEL0 4 +#define MDMACR2_M_DMA0CHSEL0 1 << MDMACR2_V_DMA0CHSEL0 +#define MDMACR2_V_DMA0CHSEL1 5 +#define MDMACR2_M_DMA0CHSEL1 1 << MDMACR2_V_DMA0CHSEL1 +#define MDMACR2_V_DMA0CHSEL2 6 +#define MDMACR2_M_DMA0CHSEL2 1 << MDMACR2_V_DMA0CHSEL2 +#define MDMACR2_V_DMA1CHSEL 7 +#define MDMACR2_M_DMA1CHSEL 0x7 << MDMACR2_V_DMA1CHSEL +#define MDMACR2_V_DMA1CHSEL0 7 +#define MDMACR2_M_DMA1CHSEL0 1 << MDMACR2_V_DMA1CHSEL0 +#define MDMACR2_V_DMA1CHSEL1 8 +#define MDMACR2_M_DMA1CHSEL1 1 << MDMACR2_V_DMA1CHSEL1 +#define MDMACR2_V_DMA1CHSEL2 9 +#define MDMACR2_M_DMA1CHSEL2 1 << MDMACR2_V_DMA1CHSEL2 +#define MDMACR2_V_DMA2CHSEL 12 +#define MDMACR2_M_DMA2CHSEL 0x7 << MDMACR2_V_DMA2CHSEL +#define MDMACR2_V_DMA2CHSEL0 12 +#define MDMACR2_M_DMA2CHSEL0 1 << MDMACR2_V_DMA2CHSEL0 +#define MDMACR2_V_DMA2CHSEL1 13 +#define MDMACR2_M_DMA2CHSEL1 1 << MDMACR2_V_DMA2CHSEL1 +#define MDMACR2_V_DMA2CHSEL2 14 +#define MDMACR2_M_DMA2CHSEL2 1 << MDMACR2_V_DMA2CHSEL2 + +/* +** DMA Channel 0 Select +*/ +#define DMA0CHSEL_0 0x000 +#define DMA0CHSEL_1 MDMACR2_M_DMA0CHSEL0 +#define DMA0CHSEL_2 MDMACR2_M_DMA0CHSEL1 +#define DMA0CHSEL_3 (MDMACR2_M_DMA0CHSEL0 | MDMACR2_M_DMA0CHSEL1) +#define DMA0CHSEL_5 (MDMACR2_M_DMA0CHSEL0 | MDMACR2_M_DMA0CHSEL2) +#define DMA0CHSEL_6 (MDMACR2_M_DMA0CHSEL1 | MDMACR2_M_DMA0CHSEL2) +#define DMA0CHSEL_7 (MDMACR2_M_DMA0CHSEL0 | MDMACR2_M_DMA0CHSEL1 | MDMACR2_M_DMA0CHSEL1) + +/* +** DMA Channel 1 Select +*/ +#define DMA1CHSEL_0 0x000 +#define DMA1CHSEL_1 MDMACR2_M_DMA1CHSEL0 +#define DMA1CHSEL_2 MDMACR2_M_DMA1CHSEL1 +#define DMA1CHSEL_3 (MDMACR2_M_DMA1CHSEL0 | MDMACR2_M_DMA1CHSEL1) +#define DMA1CHSEL_5 (MDMACR2_M_DMA1CHSEL0 | MDMACR2_M_DMA1CHSEL2) +#define DMA1CHSEL_6 (MDMACR2_M_DMA1CHSEL1 | MDMACR2_M_DMA1CHSEL2) +#define DMA1CHSEL_7 (MDMACR2_M_DMA1CHSEL0 | MDMACR2_M_DMA1CHSEL1 | MDMACR2_M_DMA1CHSEL1) + +/* +** DMA Channel 2 Select +*/ +#define DMA2CHSEL_0 0x000 +#define DMA2CHSEL_1 MDMACR2_M_DMA2CHSEL0 +#define DMA2CHSEL_2 MDMACR2_M_DMA2CHSEL1 +#define DMA2CHSEL_3 (MDMACR2_M_DMA2CHSEL0 | MDMACR2_M_DMA2CHSEL1) +#define DMA2CHSEL_5 (MDMACR2_M_DMA2CHSEL0 | MDMACR2_M_DMA2CHSEL2) +#define DMA2CHSEL_6 (MDMACR2_M_DMA2CHSEL1 | MDMACR2_M_DMA2CHSEL2) +#define DMA2CHSEL_7 (MDMACR2_M_DMA2CHSEL0 | MDMACR2_M_DMA2CHSEL1 | MDMACR2_M_DMA2CHSEL1) + +/* +** +** Burst Bus Interrupt Control Register (BBICR) - Index 0x340 +** +** Loc Size Name Function +** ----- ---- ---- --------------------------------- +** <0> 1 ENBINT Enable Burst Bus Interrupt +** <1> 1 BINTLOCKCLR Burst Interrupt Interlock Clear +** <2> 1 BINTLOCKDIS Burst Interrupt Interlock Disable +** +** <3:15> Reserved +*/ +#define SEQ2_BBICR_REG 0x340 +#define SEQ2_BBICR_INIT 0x0000 +#define BBICR_V_ENBINT 0 +#define BBICR_M_ENBINT 1 << BBICR_V_ENBINT +#define BBICR_V_BINTLOCKCLR 1 +#define BBICR_M_BINTLOCKCLR 1 << BBICR_V_BINTLOCKCLR +#define BBICR_V_BINTLOCKDIS 2 +#define BBICR_M_BINTLOCKDIS 1 << BBICR_V_BINTLOCKDIS + +/* +** +** Primary Activities IRQ Mask Register (PAIMR) - Index 0x350 +** +** Loc Size Name Function +** ----- ---- ---- --------------------------------- +** <1> 1 PAMSKIRQ1 IRQ1 Primary Activity Mask Enable +** <3> 1 PAMSKIRQ3 IRQ3 Primary Activity Mask Enable +** <4> 1 PAMSKIRQ4 IRQ4 Primary Activity Mask Enable +** <5> 1 PAMSKIRQ5 IRQ5 Primary Activity Mask Enable +** <6> 1 PAMSKIRQ6 IRQ6 Primary Activity Mask Enable +** <7> 1 PAMSKIRQ7 IRQ7 Primary Activity Mask Enable +** <8> 1 PAMSKIRQ8 IRQ8 Primary Activity Mask Enable +** <9> 1 PAMSKIRQ9 IRQ9 Primary Activity Mask Enable +** <10> 1 PAMSKIRQ10 IRQ10 Primary Activity Mask Enable +** <11> 1 PAMSKIRQ11 IRQ11 Primary Activity Mask Enable +** <12> 1 PAMSKIRQ12 IRQ12 Primary Activity Mask Enable +** <13> 1 PAMSKIRQ13 IRQ13 Primary Activity Mask Enable +** <14> 1 PAMSKIRQ14 IRQ14 Primary Activity Mask Enable +** <15> 1 PAMSKIRQ15 IRQ15 Primary Activity Mask Enable +** +** <0><2> Reserved +*/ +#define SEQ2_PAIMR_REG 0x350 +#define SEQ2_PAIMR_INIT ( PAIMR_M_PAMSKIRQ1 | PAIMR_M_PAMSKIRQ3 | \ + PAIMR_M_PAMSKIRQ4 | PAIMR_M_PAMSKIRQ5 | \ + PAIMR_M_PAMSKIRQ6 | PAIMR_M_PAMSKIRQ7 | \ + PAIMR_M_PAMSKIRQ8 | PAIMR_M_PAMSKIRQ9 | \ + PAIMR_M_PAMSKIRQ10 | PAIMR_M_PAMSKIRQ11 | \ + PAIMR_M_PAMSKIRQ12 | PAIMR_M_PAMSKIRQ13 | \ + PAIMR_M_PAMSKIRQ14 ) +#define PAIMR_V_PAMSKIRQ1 1 +#define PAIMR_M_PAMSKIRQ1 1 << PAIMR_V_PAMSKIRQ1 +#define PAIMR_V_PAMSKIRQ3 3 +#define PAIMR_M_PAMSKIRQ3 1 << PAIMR_V_PAMSKIRQ3 +#define PAIMR_V_PAMSKIRQ4 4 +#define PAIMR_M_PAMSKIRQ4 1 << PAIMR_V_PAMSKIRQ4 +#define PAIMR_V_PAMSKIRQ5 5 +#define PAIMR_M_PAMSKIRQ5 1 << PAIMR_V_PAMSKIRQ5 +#define PAIMR_V_PAMSKIRQ6 6 +#define PAIMR_M_PAMSKIRQ6 1 << PAIMR_V_PAMSKIRQ6 +#define PAIMR_V_PAMSKIRQ7 7 +#define PAIMR_M_PAMSKIRQ7 1 << PAIMR_V_PAMSKIRQ7 +#define PAIMR_V_PAMSKIRQ8 8 +#define PAIMR_M_PAMSKIRQ8 1 << PAIMR_V_PAMSKIRQ8 +#define PAIMR_V_PAMSKIRQ9 9 +#define PAIMR_M_PAMSKIRQ9 1 << PAIMR_V_PAMSKIRQ9 +#define PAIMR_V_PAMSKIRQ10 10 +#define PAIMR_M_PAMSKIRQ10 1 << PAIMR_V_PAMSKIRQ10 +#define PAIMR_V_PAMSKIRQ11 11 +#define PAIMR_M_PAMSKIRQ11 1 << PAIMR_V_PAMSKIRQ11 +#define PAIMR_V_PAMSKIRQ12 12 +#define PAIMR_M_PAMSKIRQ12 1 << PAIMR_V_PAMSKIRQ12 +#define PAIMR_V_PAMSKIRQ13 13 +#define PAIMR_M_PAMSKIRQ13 1 << PAIMR_V_PAMSKIRQ13 +#define PAIMR_V_PAMSKIRQ14 14 +#define PAIMR_M_PAMSKIRQ14 1 << PAIMR_V_PAMSKIRQ14 +#define PAIMR_V_PAMSKIRQ15 15 +#define PAIMR_M_PAMSKIRQ15 1 << PAIMR_V_PAMSKIRQ15 + +/* +** +** PMI Trigger Source IRQ Active Register (PTSIAR) - Index 0x351 +** +** Loc Size Name Function +** ----- ---- ---- --------------------------------- +** <0> 1 PMIDETBACTV PMI Trigger Source DeTurbo Switch Active +** <1> 1 PMIIRQ1ACTV PMI Trigger Source IRQ1 Active +** <3> 1 PMIIRQ3ACTV PMI Trigger Source IRQ3 Active +** <4> 1 PMIIRQ4ACTV PMI Trigger Source IRQ4 Active +** <5> 1 PMIIRQ5ACTV PMI Trigger Source IRQ5 Active +** <6> 1 PMIIRQ6ACTV PMI Trigger Source IRQ6 Active +** <7> 1 PMIIRQ7ACTV PMI Trigger Source IRQ7 Active +** <8> 1 PMIIRQ8ACTV PMI Trigger Source IRQ8 Active +** <9> 1 PMIIRQ9ACTV PMI Trigger Source IRQ9 Active +** <10> 1 PMIIRQ10ACTV PMI Trigger Source IRQ10 Active +** <11> 1 PMIIRQ11ACTV PMI Trigger Source IRQ11 Active +** <12> 1 PMIIRQ12ACTV PMI Trigger Source IRQ12 Active +** <13> 1 PMIIRQ13ACTV PMI Trigger Source IRQ13 Active +** <14> 1 PMIIRQ14ACTV PMI Trigger Source IRQ14 Active +** <15> 1 PMIIRQ15ACTV PMI Trigger Source IRQ15 Active +** +** <2> Reserved +*/ +#define SEQ2_PTSIAR_REG 0x351 +#define SEQ2_PTSIAR_INIT 0x0000 +#define PTSIAR_V_PMIDETBACTV 0 +#define PTSIAR_M_PMIDETBACTV 1 << PTSIAR_V_PMIDETBACTV +#define PTSIAR_V_PMIIRQ1ACTV 1 +#define PTSIAR_M_PMIIRQ1ACTV 1 << PTSIAR_V_PMIIRQ1ACTV +#define PTSIAR_V_PMIIRQ3ACTV 3 +#define PTSIAR_M_PMIIRQ3ACTV 1 << PTSIAR_V_PMIIRQ3ACTV +#define PTSIAR_V_PMIIRQ4ACTV 4 +#define PTSIAR_M_PMIIRQ4ACTV 1 << PTSIAR_V_PMIIRQ4ACTV +#define PTSIAR_V_PMIIRQ5ACTV 5 +#define PTSIAR_M_PMIIRQ5ACTV 1 << PTSIAR_V_PMIIRQ5ACTV +#define PTSIAR_V_PMIIRQ6ACTV 6 +#define PTSIAR_M_PMIIRQ6ACTV 1 << PTSIAR_V_PMIIRQ6ACTV +#define PTSIAR_V_PMIIRQ7ACTV 7 +#define PTSIAR_M_PMIIRQ7ACTV 1 << PTSIAR_V_PMIIRQ7ACTV +#define PTSIAR_V_PMIIRQ8ACTV 8 +#define PTSIAR_M_PMIIRQ8ACTV 1 << PTSIAR_V_PMIIRQ8ACTV +#define PTSIAR_V_PMIIRQ9ACTV 9 +#define PTSIAR_M_PMIIRQ9ACTV 1 << PTSIAR_V_PMIIRQ9ACTV +#define PTSIAR_V_PMIIRQ10ACTV 10 +#define PTSIAR_M_PMIIRQ10ACTV 1 << PTSIAR_V_PMIIRQ10ACTV +#define PTSIAR_V_PMIIRQ11ACTV 11 +#define PTSIAR_M_PMIIRQ11ACTV 1 << PTSIAR_V_PMIIRQ11ACTV +#define PTSIAR_V_PMIIRQ12ACTV 12 +#define PTSIAR_M_PMIIRQ12ACTV 1 << PTSIAR_V_PMIIRQ12ACTV +#define PTSIAR_V_PMIIRQ13ACTV 13 +#define PTSIAR_M_PMIIRQ13ACTV 1 << PTSIAR_V_PMIIRQ13ACTV +#define PTSIAR_V_PMIIRQ14ACTV 14 +#define PTSIAR_M_PMIIRQ14ACTV 1 << PTSIAR_V_PMIIRQ14ACTV +#define PTSIAR_V_PMIIRQ15ACTV 15 +#define PTSIAR_M_PMIIRQ15ACTV 1 << PTSIAR_V_PMIIRQ15ACTV + +/* +** +** PMI Trigger Source IRQ Mask Register (PTSIMR) - Index 0x352 +** +** Loc Size Name Function +** ----- ---- ---- --------------------------------- +** <0> 1 IMSKDETURBO DeTurbo Switch Triggering PMI Mask Enable +** <1> 1 IMSKIRQ1 IRQ1 Triggering PMI Mask Enable +** <3> 1 IMSKIRQ3 IRQ3 Triggering PMI Mask Enable +** <4> 1 IMSKIRQ4 IRQ4 Triggering PMI Mask Enable +** <5> 1 IMSKIRQ5 IRQ5 Triggering PMI Mask Enable +** <6> 1 IMSKIRQ6 IRQ6 Triggering PMI Mask Enable +** <7> 1 IMSKIRQ7 IRQ7 Triggering PMI Mask Enable +** <8> 1 IMSKIRQ8 IRQ8 Triggering PMI Mask Enable +** <9> 1 IMSKIRQ9 IRQ9 Triggering PMI Mask Enable +** <10> 1 IMSKIRQ10 IRQ10 Triggering PMI Mask Enable +** <11> 1 IMSKIRQ11 IRQ11 Triggering PMI Mask Enable +** <12> 1 IMSKIRQ12 IRQ12 Triggering PMI Mask Enable +** <13> 1 IMSKIRQ13 IRQ13 Triggering PMI Mask Enable +** <14> 1 IMSKIRQ14 IRQ14 Triggering PMI Mask Enable +** <15> 1 IMSKIRQ15 IRQ15 Triggering PMI Mask Enable +** +** <2> Reserved +*/ +#define SEQ2_PTSIMR_REG 0x352 +#define SEQ2_PTSIMR_INIT ( PTSIMR_M_IMSKDETURBO | PTSIMR_M_IMSKIRQ1 | \ + PTSIMR_M_IMSKIRQ3 | PTSIMR_M_IMSKIRQ4 | \ + PTSIMR_M_IMSKIRQ5 | PTSIMR_M_IMSKIRQ6 | \ + PTSIMR_M_IMSKIRQ7 | PTSIMR_M_IMSKIRQ8 | \ + PTSIMR_M_IMSKIRQ9 | PTSIMR_M_IMSKIRQ10 | \ + PTSIMR_M_IMSKIRQ11 | PTSIMR_M_IMSKIRQ12 | \ + PTSIMR_M_IMSKIRQ13 | PTSIMR_M_IMSKIRQ14 | \ + PTSIMR_M_IMSKIRQ15 ) +#define PTSIMR_V_IMSKDETURBO 0 +#define PTSIMR_M_IMSKDETURBO 1 << PTSIMR_V_IMSKDETURBO +#define PTSIMR_V_IMSKIRQ1 1 +#define PTSIMR_M_IMSKIRQ1 1 << PTSIMR_V_IMSKIRQ1 +#define PTSIMR_V_IMSKIRQ3 3 +#define PTSIMR_M_IMSKIRQ3 1 << PTSIMR_V_IMSKIRQ3 +#define PTSIMR_V_IMSKIRQ4 4 +#define PTSIMR_M_IMSKIRQ4 1 << PTSIMR_V_IMSKIRQ4 +#define PTSIMR_V_IMSKIRQ5 5 +#define PTSIMR_M_IMSKIRQ5 1 << PTSIMR_V_IMSKIRQ5 +#define PTSIMR_V_IMSKIRQ6 6 +#define PTSIMR_M_IMSKIRQ6 1 << PTSIMR_V_IMSKIRQ6 +#define PTSIMR_V_IMSKIRQ7 7 +#define PTSIMR_M_IMSKIRQ7 1 << PTSIMR_V_IMSKIRQ7 +#define PTSIMR_V_IMSKIRQ8 8 +#define PTSIMR_M_IMSKIRQ8 1 << PTSIMR_V_IMSKIRQ8 +#define PTSIMR_V_IMSKIRQ9 9 +#define PTSIMR_M_IMSKIRQ9 1 << PTSIMR_V_IMSKIRQ9 +#define PTSIMR_V_IMSKIRQ10 10 +#define PTSIMR_M_IMSKIRQ10 1 << PTSIMR_V_IMSKIRQ10 +#define PTSIMR_V_IMSKIRQ11 11 +#define PTSIMR_M_IMSKIRQ11 1 << PTSIMR_V_IMSKIRQ11 +#define PTSIMR_V_IMSKIRQ12 12 +#define PTSIMR_M_IMSKIRQ12 1 << PTSIMR_V_IMSKIRQ12 +#define PTSIMR_V_IMSKIRQ13 13 +#define PTSIMR_M_IMSKIRQ13 1 << PTSIMR_V_IMSKIRQ13 +#define PTSIMR_V_IMSKIRQ14 14 +#define PTSIMR_M_IMSKIRQ14 1 << PTSIMR_V_IMSKIRQ14 +#define PTSIMR_V_IMSKIRQ15 15 +#define PTSIMR_M_IMSKIRQ15 1 << PTSIMR_V_IMSKIRQ15 + +/* +** +** IRQ Secondary Activity Enable Register (ISAER) - Index 0x353 +** +** Loc Size Name Function +** ----- ---- ---- --------------------------------- +** <0> 1 SAMSKIRQ Secondary Activity Mask for IRQs +** +** <1:15> Reserved +*/ +#define SEQ2_ISAER_REG 0x353 +#define SEQ2_ISAER_INIT ISAER_M_SAMSKIRQ +#define ISAER_V_SAMSKIRQ 0 +#define ISAER_M_SAMSKIRQ 1 << ISAER_V_SAMSKIRQ + +/* +** Shadow Read Registers +** +*/ + +#define SR_M_DATAMSK 0xF + +/* +** 8254 Counter Registers +*/ +#define SRR_54CTR0_REG1 0x500 +#define SRR_54CTR0_REG2 0x501 +#define SRR_54CTR0_REG3 0x506 +#define SRR_54CTR1_REG1 0x502 +#define SRR_54CTR1_REG2 0x503 +#define SRR_54CTR1_REG3 0x507 +#define SRR_54CTR2_REG1 0x504 +#define SRR_54CTR2_REG2 0x505 +#define SRR_54CTR2_REG3 0x508 + +/* +** 8237 DMA Controller Registers +*/ +#define SRR_37CTRL0_REG1 0x510 +#define SRR_37CTRL0_REG2 0x511 +#define SRR_37CTRL0_REG3 0x512 +#define SRR_37CTRL1_REG4 0x513 +#define SRR_37CTRL1_REG5 0x514 +#define SRR_37CTRL1_REG6 0x515 +#define SRR_37CTRL2_REG7 0x516 +#define SRR_37CTRL2_REG8 0x517 + +/* +** 8259 Interrupt Controller Registers +*/ +#define SRR_59CTRL0_REG1 0x520 +#define SRR_59CTRL0_REG2 0x521 +#define SRR_59CTRL0_REG3 0x522 +#define SRR_59CTRL1_REG4 0x523 +#define SRR_59CTRL1_REG5 0x524 +#define SRR_59CTRL1_REG6 0x525 +#define SRR_59CTRL2_REG7 0x526 +#define SRR_59CTRL2_REG8 0x527 +#define SRR_59CTRL2_REG9 0x528 +#define SRR_59CTRL2_REG10 0x529 +#define SRR_59CTRL2_REG11 0x52A +#define SRR_59CTRL2_REG12 0x52B + +/* +** IBM-AT Standard Registers +** +*/ + +/* +** +** Register 1 (REG1) - Access Address 0x061 +** +** Loc Size Name Function +** ----- ---- ---- --------------------------------- +** <0> 1 TMR2EN Timer 2 Enable +** <1> 1 SPKREN Speaker Enable +** <2> 1 PARDIS Parity Disable +** <3> 1 IOCHKDIS I/O Channel Check Disable +** <4> 1 REFRTGL Refresh Toggle +** <5> 1 TMR2OUT Timer 2 Output +** <6> 1 IOCKERR I/O Channel Check Error +** <7> 1 PARERR Parity Error +** +*/ +#define ATSR_REG1_REG 0x061 +#define ATSR_REG1_INIT REG1_M_PARDIS +#define REG1_V_TMR2EN 0 +#define REG1_M_TMR2EN 1 << REG1_V_TMR2EN +#define REG1_V_SPKREN 1 +#define REG1_M_SPKREN 1 << REG1_V_SPKREN +#define REG1_V_PARDIS 2 +#define REG1_M_PARDIS 1 << REG1_V_PARDIS +#define REG1_V_IOCHKDIS 3 +#define REG1_M_IOCHKDIS 1 << REG1_V_IOCHKDIS +#define REG1_V_REFRTGL 4 +#define REG1_M_REFRTGL 1 << REG1_V_REFRTGL +#define REG1_V_TMR2OUT 5 +#define REG1_M_TMR2OUT 1 << REG1_V_TMR2OUT +#define REG1_V_IOCKERR 6 +#define REG1_M_IOCKERR 1 << REG1_V_IOCKERR +#define REG1_V_PARERR 7 +#define REG1_M_PARERR 1 << REG1_V_PARERR + +/* +** +** Register 2 (REG2) - Access Address 0x070 +** +** Loc Size Name Function +** ----- ---- ---- --------------------------------- +** <0> 6 RTCINDX Real Timer Clock Index +** <7> 1 NMIDIS NMI Mask Disable +** +*/ +#define ATSR_REG2_REG 0x070 +#define ATSR_REG2_INIT REG2_M_NMIDIS +#define REG2_V_RTCINDX 0 +#define REG2_M_RTCINDX 0x7F << REG2_V_RTCINDX +#define REG2_V_NMIDIS 7 +#define REG2_M_NMIDIS 1 << REG2_V_NMIDIS + +/* +** +** Register 3 (REG3) - Access Address 0x092 +** +** Loc Size Name Function +** ----- ---- ---- --------------------------------- +** <0> 1 FSTRST Alternate Fast CPU Reset +** <1> 1 FGATEA20 Fast GATEA20 +** <3> 1 SCLOCK1 Security Lock 1 +** +** <2><4:7> Reserved +*/ +#define ATSR_REG3_REG 0x092 +#define ATSR_REG3_INIT 0x0000 +#define REG3_V_FSTRST 0 +#define REG3_M_FSTRST 1 << REG3_V_FSTRST +#define REG3_V_FGATEA20 1 +#define REG3_M_FGATEA20 1 << REG3_V_FGATEA20 +#define REG3_V_SCLOCK1 3 +#define REG3_M_SCLOCK1 1 << REG3_V_SCLOCK1 + + + + + + +#ifndef __LANGUAGE_ASM__ +#ifndef _LOCORE + +void sequoiaInit(); +void sequoiaWrite __P((int reg,u_int16_t value)); +void sequoiaRead __P((int reg,u_int16_t * value_ptr)); + +/* x console functions */ +void consXTvOn __P((void)); +void consXTvOff __P((void)); + + +/* smart card reader functions */ +int scrGetDetect __P((void)); +void scrSetPower __P((int value)); +void scrSetClock __P((int value)); +void scrSetReset __P((int value)); +void scrSetDataHighZ __P((void)); +void scrSetData __P((int value)); +int scrGetData __P((void)); + + +/* just used to debug scr - remove when done - ejg */ +void scrToggleTestPin __P((void)); +void sequoiaOneAccess(void); + + +/* biled functions */ +void ledNetActive __P((void)); +void ledNetBlock __P((void)); +void ledNetUnblock __P((void)); +void ledPanic __P((void)); + + +/* function to get the hw rev */ +int hwGetRev __P((void)); + +/* debug led functions */ +#define LED_DEBUG_STATE_0 0 +#define LED_DEBUG_STATE_1 1 +#define LED_DEBUG_STATE_2 2 +#define LED_DEBUG_STATE_3 3 + +#define LED_DEBUG_YELLOW_OFF 4 +#define LED_DEBUG_YELLOW_ON 5 + +#define LED_DEBUG_GREEN_OFF 6 +#define LED_DEBUG_GREEN_ON 7 + + +void ledSetDebug __P((int command)); + + + + + +#endif /* _LOCORE */ +#endif /* __LANGUAGE_ASM__ */ + +#endif /* SEQUOIAH */ + + + + + + + +