Add support for the CMD PCI0646U2, an Ultra/33 version of the 0646.
Note: there's also a PCI0646U, for which I don't have docs for now.
This commit is contained in:
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8451f00774
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@ -1,4 +1,4 @@
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/* $NetBSD: pciide.c,v 1.81 2000/07/27 14:28:45 bouyer Exp $ */
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/* $NetBSD: pciide.c,v 1.82 2000/08/01 21:02:55 bouyer Exp $ */
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/*
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/*
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@ -2165,6 +2165,8 @@ cmd0643_9_chip_map(sc, pa)
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{
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{
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struct pciide_channel *cp;
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struct pciide_channel *cp;
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int channel;
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int channel;
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int rev = PCI_REVISION(
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pci_conf_read(sc->sc_pc, sc->sc_tag, PCI_CLASS_REG));
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/*
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/*
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* For a CMD PCI064x, the use of PCI_COMMAND_IO_ENABLE
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* For a CMD PCI064x, the use of PCI_COMMAND_IO_ENABLE
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@ -2193,7 +2195,13 @@ cmd0643_9_chip_map(sc, pa)
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case PCI_PRODUCT_CMDTECH_648:
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case PCI_PRODUCT_CMDTECH_648:
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sc->sc_wdcdev.cap |= WDC_CAPABILITY_UDMA;
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sc->sc_wdcdev.cap |= WDC_CAPABILITY_UDMA;
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sc->sc_wdcdev.UDMA_cap = 4;
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sc->sc_wdcdev.UDMA_cap = 4;
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sc->sc_wdcdev.irqack = cmd646_9_irqack;
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break;
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case PCI_PRODUCT_CMDTECH_646:
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case PCI_PRODUCT_CMDTECH_646:
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if (rev >= CMD0646U2_REV) {
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sc->sc_wdcdev.cap |= WDC_CAPABILITY_UDMA;
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sc->sc_wdcdev.UDMA_cap = 2;
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}
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sc->sc_wdcdev.irqack = cmd646_9_irqack;
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sc->sc_wdcdev.irqack = cmd646_9_irqack;
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break;
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break;
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default:
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default:
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@ -2219,6 +2227,7 @@ cmd0643_9_chip_map(sc, pa)
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continue;
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continue;
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cmd0643_9_setup_channel(&cp->wdc_channel);
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cmd0643_9_setup_channel(&cp->wdc_channel);
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}
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}
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/* note - this also make sure we clear the irq disable and reset bits */
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pciide_pci_write(sc->sc_pc, sc->sc_tag, CMD_DMA_MODE, CMD_DMA_MULTIPLE);
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pciide_pci_write(sc->sc_pc, sc->sc_tag, CMD_DMA_MODE, CMD_DMA_MULTIPLE);
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WDCDEBUG_PRINT(("cmd0643_9_chip_map: timings reg now 0x%x 0x%x\n",
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WDCDEBUG_PRINT(("cmd0643_9_chip_map: timings reg now 0x%x 0x%x\n",
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pci_conf_read(sc->sc_pc, sc->sc_tag, 0x54),
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pci_conf_read(sc->sc_pc, sc->sc_tag, 0x54),
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@ -2250,7 +2259,7 @@ cmd0643_9_setup_channel(chp)
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tim = cmd0643_9_data_tim_pio[drvp->PIO_mode];
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tim = cmd0643_9_data_tim_pio[drvp->PIO_mode];
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if (drvp->drive_flags & (DRIVE_DMA | DRIVE_UDMA)) {
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if (drvp->drive_flags & (DRIVE_DMA | DRIVE_UDMA)) {
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if (drvp->drive_flags & DRIVE_UDMA) {
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if (drvp->drive_flags & DRIVE_UDMA) {
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/* UltraDMA on a 0648 or 0649 */
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/* UltraDMA on a 646U2, 0648 or 0649 */
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udma_reg = pciide_pci_read(sc->sc_pc,
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udma_reg = pciide_pci_read(sc->sc_pc,
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sc->sc_tag, CMD_UDMATIM(chp->channel));
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sc->sc_tag, CMD_UDMATIM(chp->channel));
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if (drvp->UDMA_mode > 2 &&
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if (drvp->UDMA_mode > 2 &&
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@ -2260,13 +2269,13 @@ cmd0643_9_setup_channel(chp)
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drvp->UDMA_mode = 2;
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drvp->UDMA_mode = 2;
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if (drvp->UDMA_mode > 2)
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if (drvp->UDMA_mode > 2)
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udma_reg &= ~CMD_UDMATIM_UDMA33(drive);
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udma_reg &= ~CMD_UDMATIM_UDMA33(drive);
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else
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else if (sc->sc_wdcdev.UDMA_cap > 2)
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udma_reg |= CMD_UDMATIM_UDMA33(drive);
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udma_reg |= CMD_UDMATIM_UDMA33(drive);
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udma_reg |= CMD_UDMATIM_UDMA(drive);
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udma_reg |= CMD_UDMATIM_UDMA(drive);
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udma_reg &= ~(CMD_UDMATIM_TIM_MASK <<
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udma_reg &= ~(CMD_UDMATIM_TIM_MASK <<
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CMD_UDMATIM_TIM_OFF(drive));
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CMD_UDMATIM_TIM_OFF(drive));
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udma_reg |=
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udma_reg |=
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(cmd0648_9_tim_udma[drvp->UDMA_mode] <<
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(cmd0646_9_tim_udma[drvp->UDMA_mode] <<
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CMD_UDMATIM_TIM_OFF(drive));
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CMD_UDMATIM_TIM_OFF(drive));
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pciide_pci_write(sc->sc_pc, sc->sc_tag,
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pciide_pci_write(sc->sc_pc, sc->sc_tag,
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CMD_UDMATIM(chp->channel), udma_reg);
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CMD_UDMATIM(chp->channel), udma_reg);
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@ -2275,7 +2284,7 @@ cmd0643_9_setup_channel(chp)
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* use Multiword DMA.
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* use Multiword DMA.
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* Timings will be used for both PIO and DMA,
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* Timings will be used for both PIO and DMA,
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* so adjust DMA mode if needed
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* so adjust DMA mode if needed
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* if we have a 0648/9, turn off UDMA
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* if we have a 0646U2/8/9, turn off UDMA
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*/
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*/
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if (sc->sc_wdcdev.cap & WDC_CAPABILITY_UDMA) {
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if (sc->sc_wdcdev.cap & WDC_CAPABILITY_UDMA) {
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udma_reg = pciide_pci_read(sc->sc_pc,
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udma_reg = pciide_pci_read(sc->sc_pc,
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@ -1,4 +1,4 @@
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/* $NetBSD: pciide_cmd_reg.h,v 1.7 2000/06/26 10:07:52 bouyer Exp $ */
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/* $NetBSD: pciide_cmd_reg.h,v 1.8 2000/08/01 21:02:56 bouyer Exp $ */
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/*
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/*
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* Copyright (c) 1998 Manuel Bouyer.
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* Copyright (c) 1998 Manuel Bouyer.
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@ -37,6 +37,9 @@
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* Available from http://www.cmd.com/
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* Available from http://www.cmd.com/
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*/
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*/
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/* revision of the 0646U2 */
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#define CMD0646U2_REV 0x05
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/* Configuration (RO) */
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/* Configuration (RO) */
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#define CMD_CONF 0x50
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#define CMD_CONF 0x50
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#define CMD_CONF_REV_MASK 0x03 /* 0640/3/6 only */
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#define CMD_CONF_REV_MASK 0x03 /* 0640/3/6 only */
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@ -74,11 +77,16 @@
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/* DMA master read mode select */
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/* DMA master read mode select */
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#define CMD_DMA_MODE 0x71
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#define CMD_DMA_MODE 0x71
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#define CMD_DMA_MASK 0x03
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#define CMD_DMA 0x00
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#define CMD_DMA 0x00
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#define CMD_DMA_MULTIPLE 0x01
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#define CMD_DMA_MULTIPLE 0x01
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#define CMD_DMA_LINE 0x10
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#define CMD_DMA_LINE 0x03
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/* the followings bits are only for 0646U/646U2/648/649 */
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#define CMD_DMA_IRQ(chan) (0x4 << (chan))
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#define CMD_DMA_IRQ_DIS(chan) (0x10 << (chan))
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#define CMD_DMA_RST 0x40
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/* the followings are only for 0648/9 */
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/* the followings are only for 0646U/646U2/648/649 */
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/* busmaster control/status register */
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/* busmaster control/status register */
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#define CMD_BICSR 0x79
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#define CMD_BICSR 0x79
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#define CMD_BICSR_80(chan) (0x01 << (chan))
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#define CMD_BICSR_80(chan) (0x01 << (chan))
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#define CMD_UDMATIM_UDMA33(drive) (0x04 << (drive))
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#define CMD_UDMATIM_UDMA33(drive) (0x04 << (drive))
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#define CMD_UDMATIM_TIM_MASK 0x3
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#define CMD_UDMATIM_TIM_MASK 0x3
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#define CMD_UDMATIM_TIM_OFF(drive) (4 + ((drive) * 2))
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#define CMD_UDMATIM_TIM_OFF(drive) (4 + ((drive) * 2))
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static int8_t cmd0648_9_tim_udma[] = {0x03, 0x02, 0x01, 0x02, 0x01};
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static int8_t cmd0646_9_tim_udma[] = {0x03, 0x02, 0x01, 0x02, 0x01};
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/*
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/*
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* timings values for the 0643/6/8/9
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* timings values for the 0643/6/8/9
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