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skrll
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768fb9809e
@ -1,4 +1,4 @@
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/* $NetBSD: ahcisata_core.c,v 1.86 2020/12/25 08:55:40 skrll Exp $ */
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/* $NetBSD: ahcisata_core.c,v 1.87 2020/12/25 08:57:38 skrll Exp $ */
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/*
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* Copyright (c) 2006 Manuel Bouyer.
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@ -26,7 +26,7 @@
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*/
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#include <sys/cdefs.h>
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__KERNEL_RCSID(0, "$NetBSD: ahcisata_core.c,v 1.86 2020/12/25 08:55:40 skrll Exp $");
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__KERNEL_RCSID(0, "$NetBSD: ahcisata_core.c,v 1.87 2020/12/25 08:57:38 skrll Exp $");
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#include <sys/types.h>
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#include <sys/malloc.h>
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@ -176,7 +176,7 @@ static void
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ahci_setup_ports(struct ahci_softc *sc)
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{
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int i, port;
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for (i = 0, port = 0; i < AHCI_MAX_PORTS; i++) {
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if ((sc->sc_ahci_ports & (1U << i)) == 0)
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continue;
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@ -254,7 +254,7 @@ ahci_attach(struct ahci_softc *sc)
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sc->sc_init_data.cap = AHCI_READ(sc, AHCI_CAP);
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sc->sc_init_data.ports = AHCI_READ(sc, AHCI_PI);
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ahci_rev = AHCI_READ(sc, AHCI_VS);
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if (AHCI_VS_MJR(ahci_rev) > 1 ||
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(AHCI_VS_MJR(ahci_rev) == 1 && AHCI_VS_MNR(ahci_rev) >= 20)) {
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@ -314,7 +314,7 @@ ahci_attach(struct ahci_softc *sc)
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", %d port%s, %d slot%s, CAP %s\n",
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AHCI_VS_MJR(ahci_rev), AHCI_VS_MNR(ahci_rev),
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sc->sc_atac.atac_nchannels,
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(sc->sc_atac.atac_nchannels == 1 ? "" : "s"),
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(sc->sc_atac.atac_nchannels == 1 ? "" : "s"),
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sc->sc_ncmds, (sc->sc_ncmds == 1 ? "" : "s"), buf);
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sc->sc_atac.atac_cap = ATAC_CAP_DATA16 | ATAC_CAP_DMA | ATAC_CAP_UDMA
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@ -434,18 +434,18 @@ ahci_attach(struct ahci_softc *sc)
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achp->ahcic_bus_cmdh = sc->sc_cmd_hdrd->dm_segs[0].ds_addr +
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AHCI_CMDH_SIZE * port;
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achp->ahcic_rfis = (struct ahci_r_fis *)
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((char *)cmdhp +
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AHCI_CMDH_SIZE * sc->sc_atac.atac_nchannels +
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((char *)cmdhp +
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AHCI_CMDH_SIZE * sc->sc_atac.atac_nchannels +
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AHCI_RFIS_SIZE * port);
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achp->ahcic_bus_rfis = sc->sc_cmd_hdrd->dm_segs[0].ds_addr +
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AHCI_CMDH_SIZE * sc->sc_atac.atac_nchannels +
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AHCI_CMDH_SIZE * sc->sc_atac.atac_nchannels +
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AHCI_RFIS_SIZE * port;
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AHCIDEBUG_PRINT(("port %d cmdh %p (0x%" PRIx64 ") "
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"rfis %p (0x%" PRIx64 ")\n", i,
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achp->ahcic_cmdh, (uint64_t)achp->ahcic_bus_cmdh,
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achp->ahcic_rfis, (uint64_t)achp->ahcic_bus_rfis),
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DEBUG_PROBE);
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for (j = 0; j < sc->sc_ncmds; j++) {
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achp->ahcic_cmd_tbl[j] = (struct ahci_cmd_tbl *)
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((char *)cmdtblp + AHCI_CMDTBL_SIZE * j);
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@ -718,7 +718,7 @@ ahci_intr_port(void *v)
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if (__predict_false(recover)) {
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ata_channel_lock(chp);
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ata_channel_thaw_locked(chp);
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ata_thread_run(chp, 0, ATACH_TH_RECOVERY, tfd);
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ata_thread_run(chp, 0, ATACH_TH_RECOVERY, tfd);
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ata_channel_unlock(chp);
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}
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@ -1198,7 +1198,7 @@ ahci_cmd_poll(struct ata_channel *chp, struct ata_xfer *xfer)
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ata_channel_lock(chp);
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/*
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* Polled command.
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* Polled command.
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*/
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for (int i = 0; i < xfer->c_ata_c.timeout / 10; i++) {
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if (xfer->c_ata_c.flags & AT_DONE)
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@ -1208,7 +1208,7 @@ ahci_cmd_poll(struct ata_channel *chp, struct ata_xfer *xfer)
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ata_channel_lock(chp);
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ata_delay(chp, 10, "ahcipl", xfer->c_ata_c.flags);
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}
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AHCIDEBUG_PRINT(("%s port %d poll end GHC 0x%x IS 0x%x list 0x%x%x fis 0x%x%x CMD 0x%x CI 0x%x\n", AHCINAME(sc), chp->ch_channel,
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AHCIDEBUG_PRINT(("%s port %d poll end GHC 0x%x IS 0x%x list 0x%x%x fis 0x%x%x CMD 0x%x CI 0x%x\n", AHCINAME(sc), chp->ch_channel,
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AHCI_READ(sc, AHCI_GHC), AHCI_READ(sc, AHCI_IS),
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AHCI_READ(sc, AHCI_P_CLBU(chp->ch_channel)),
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AHCI_READ(sc, AHCI_P_CLB(chp->ch_channel)),
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@ -1444,7 +1444,7 @@ ahci_bio_poll(struct ata_channel *chp, struct ata_xfer *xfer)
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struct ahci_channel *achp = (struct ahci_channel *)chp;
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/*
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* Polled command.
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* Polled command.
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*/
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for (int i = 0; i < ATA_DELAY * 10; i++) {
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if (xfer->c_bio.flags & ATA_ITSDONE)
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@ -1452,7 +1452,7 @@ ahci_bio_poll(struct ata_channel *chp, struct ata_xfer *xfer)
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ahci_intr_port(achp);
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delay(100);
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}
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AHCIDEBUG_PRINT(("%s port %d poll end GHC 0x%x IS 0x%x list 0x%x%x fis 0x%x%x CMD 0x%x CI 0x%x\n", AHCINAME(sc), chp->ch_channel,
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AHCIDEBUG_PRINT(("%s port %d poll end GHC 0x%x IS 0x%x list 0x%x%x fis 0x%x%x CMD 0x%x CI 0x%x\n", AHCINAME(sc), chp->ch_channel,
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AHCI_READ(sc, AHCI_GHC), AHCI_READ(sc, AHCI_IS),
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AHCI_READ(sc, AHCI_P_CLBU(chp->ch_channel)),
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AHCI_READ(sc, AHCI_P_CLB(chp->ch_channel)),
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@ -1536,7 +1536,7 @@ ahci_bio_complete(struct ata_channel *chp, struct ata_xfer *xfer, int tfd)
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bus_dmamap_unload(sc->sc_dmat, achp->ahcic_datad[xfer->c_slot]);
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ata_bio->flags |= ATA_ITSDONE;
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if (AHCI_TFD_ERR(tfd) & WDCS_DWF) {
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if (AHCI_TFD_ERR(tfd) & WDCS_DWF) {
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ata_bio->error = ERR_DF;
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} else if (AHCI_TFD_ST(tfd) & WDCS_ERR) {
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ata_bio->error = ERROR;
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@ -1548,7 +1548,7 @@ ahci_bio_complete(struct ata_channel *chp, struct ata_xfer *xfer, int tfd)
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BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE);
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AHCIDEBUG_PRINT(("ahci_bio_complete bcount %ld",
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ata_bio->bcount), DEBUG_XFERS);
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/*
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/*
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* If it was a write, complete data buffer may have been transferred
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* before error detection; in this case don't use cmdh_prdbc
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* as it won't reflect what was written to media. Assume nothing
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@ -1741,7 +1741,7 @@ ahci_dma_setup(struct ata_channel *chp, int slot, void *data,
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return error;
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}
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bus_dmamap_sync(sc->sc_dmat, achp->ahcic_datad[slot], 0,
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achp->ahcic_datad[slot]->dm_mapsize,
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achp->ahcic_datad[slot]->dm_mapsize,
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(op == BUS_DMA_READ) ? BUS_DMASYNC_PREREAD : BUS_DMASYNC_PREWRITE);
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for (seg = 0; seg < achp->ahcic_datad[slot]->dm_nsegs; seg++) {
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cmd_tbl->cmdt_prd[seg].prd_dba = htole64(
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@ -1941,7 +1941,7 @@ ahci_atapi_poll(struct ata_channel *chp, struct ata_xfer *xfer)
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struct ahci_channel *achp = (struct ahci_channel *)chp;
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/*
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* Polled command.
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* Polled command.
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*/
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for (int i = 0; i < ATA_DELAY / 10; i++) {
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if (xfer->c_scsipi->xs_status & XS_STS_DONE)
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@ -1949,7 +1949,7 @@ ahci_atapi_poll(struct ata_channel *chp, struct ata_xfer *xfer)
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ahci_intr_port(achp);
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delay(10000);
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}
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AHCIDEBUG_PRINT(("%s port %d poll end GHC 0x%x IS 0x%x list 0x%x%x fis 0x%x%x CMD 0x%x CI 0x%x\n", AHCINAME(sc), chp->ch_channel,
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AHCIDEBUG_PRINT(("%s port %d poll end GHC 0x%x IS 0x%x list 0x%x%x fis 0x%x%x CMD 0x%x CI 0x%x\n", AHCINAME(sc), chp->ch_channel,
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AHCI_READ(sc, AHCI_GHC), AHCI_READ(sc, AHCI_IS),
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AHCI_READ(sc, AHCI_P_CLBU(chp->ch_channel)),
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AHCI_READ(sc, AHCI_P_CLB(chp->ch_channel)),
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@ -2003,7 +2003,7 @@ ahci_atapi_complete(struct ata_channel *chp, struct ata_xfer *xfer, int tfd)
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sc_xfer->resid -= le32toh(achp->ahcic_cmdh[xfer->c_slot].cmdh_prdbc);
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AHCIDEBUG_PRINT(("ahci_atapi_complete datalen %d resid %d\n",
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sc_xfer->datalen, sc_xfer->resid), DEBUG_XFERS);
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if (AHCI_TFD_ST(tfd) & WDCS_ERR &&
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if (AHCI_TFD_ST(tfd) & WDCS_ERR &&
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((sc_xfer->xs_control & XS_CTL_REQSENSE) == 0 ||
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sc_xfer->resid == sc_xfer->datalen)) {
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sc_xfer->error = XS_SHORTSENSE;
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@ -1,4 +1,4 @@
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/* $NetBSD: ahcisatavar.h,v 1.24 2020/01/18 11:26:11 simonb Exp $ */
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/* $NetBSD: ahcisatavar.h,v 1.25 2020/12/25 08:57:38 skrll Exp $ */
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/*
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* Copyright (c) 2006 Manuel Bouyer.
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@ -115,7 +115,7 @@ struct ahci_softc {
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(sc)->sc_ahcih, (reg))
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#define AHCI_WRITE(sc, reg, val) bus_space_write_4((sc)->sc_ahcit, \
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(sc)->sc_ahcih, (reg), (val))
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#define AHCI_CH2SC(chp) (struct ahci_softc *)((chp)->ch_atac)
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void ahci_attach(struct ahci_softc *);
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