Add MI mips3 wired map functions based on patch in port-mips/31915
from Garrett D'Amore of Tadpole Computer Inc. Please refer discussion filed in the PR for details.
This commit is contained in:
tsutsui
parent
2ae48df4fc
commit
74f4d162fb
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@ -1,4 +1,4 @@
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# $NetBSD: files.mips,v 1.51 2005/01/24 10:03:57 drochner Exp $
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# $NetBSD: files.mips,v 1.52 2005/11/05 09:46:07 tsutsui Exp $
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#
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defflag opt_cputype.h NOFPU
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@ -13,6 +13,7 @@ defflag opt_cputype.h NOFPU
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# ENABLE_MIPS_R3NKK
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defflag opt_mips_cache.h MIPS3_NO_PV_UNCACHED
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ENABLE_MIPS4_CACHE_R10K
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defflag opt_mips3_wired.h ENABLE_MIPS3_WIRED_MAP
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file arch/mips/mips/locore_mips1.S mips1
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file arch/mips/mips/locore_mips3.S mips3 | mips4 | mips32 | mips64
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@ -37,6 +38,7 @@ file arch/mips/mips/sys_machdep.c
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file arch/mips/mips/vm_machdep.c
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file arch/mips/mips/process_machdep.c
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file arch/mips/mips/cpu_exec.c
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file arch/mips/mips/wired_map.c (mips3|mips4|mips32|mips64) & enable_mips3_wired_map
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file arch/mips/mips/cache.c
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file arch/mips/mips/cache_r3k.c mips1
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@ -1,4 +1,4 @@
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/* $NetBSD: locore.h,v 1.70 2005/10/30 04:40:43 tsutsui Exp $ */
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/* $NetBSD: locore.h,v 1.71 2005/11/05 09:46:07 tsutsui Exp $ */
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/*
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* Copyright 1996 The Board of Trustees of The Leland Stanford
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@ -57,6 +57,7 @@ void mips3_TBIAP(int);
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void mips3_TBIS(vaddr_t);
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int mips3_TLBUpdate(u_int, u_int);
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void mips3_TLBRead(int, struct tlb *);
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void mips3_TLBWriteIndexedVPS(int, struct tlb *);
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void mips3_wbflush(void);
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void mips3_proc_trampoline(void);
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void mips3_cpu_switch_resume(void);
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@ -69,6 +70,7 @@ void mips5900_TBIAP(int);
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void mips5900_TBIS(vaddr_t);
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int mips5900_TLBUpdate(u_int, u_int);
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void mips5900_TLBRead(int, struct tlb *);
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void mips5900_TLBWriteIndexedVPS(int, struct tlb *);
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void mips5900_wbflush(void);
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void mips5900_proc_trampoline(void);
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void mips5900_cpu_switch_resume(void);
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@ -83,6 +85,7 @@ void mips32_TBIAP(int);
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void mips32_TBIS(vaddr_t);
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int mips32_TLBUpdate(u_int, u_int);
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void mips32_TLBRead(int, struct tlb *);
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void mips32_TLBWriteIndexedVPS(int, struct tlb *);
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void mips32_wbflush(void);
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void mips32_proc_trampoline(void);
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void mips32_cpu_switch_resume(void);
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@ -95,6 +98,7 @@ void mips64_TBIAP(int);
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void mips64_TBIS(vaddr_t);
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int mips64_TLBUpdate(u_int, u_int);
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void mips64_TLBRead(int, struct tlb *);
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void mips64_TLBWriteIndexedVPS(int, struct tlb *);
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void mips64_wbflush(void);
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void mips64_proc_trampoline(void);
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void mips64_cpu_switch_resume(void);
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@ -228,6 +232,7 @@ extern long *mips_locoresw[];
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#define MIPS_TBIAP() mips3_TBIAP(mips_num_tlb_entries)
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#define MIPS_TBIS mips3_TBIS
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#define MachTLBUpdate mips3_TLBUpdate
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#define MachTLBWriteIndexedVPS mips3_TLBWriteIndexedVPS
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#define proc_trampoline mips3_proc_trampoline
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#define wbflush() mips3_wbflush()
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#elif !defined(MIPS1) && !defined(MIPS3) && defined(MIPS32) && !defined(MIPS64)
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@ -235,6 +240,7 @@ extern long *mips_locoresw[];
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#define MIPS_TBIAP() mips32_TBIAP(mips_num_tlb_entries)
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#define MIPS_TBIS mips32_TBIS
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#define MachTLBUpdate mips32_TLBUpdate
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#define MachTLBWriteIndexedVPS mips32_TLBWriteIndexedVPS
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#define proc_trampoline mips32_proc_trampoline
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#define wbflush() mips32_wbflush()
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#elif !defined(MIPS1) && !defined(MIPS3) && !defined(MIPS32) && defined(MIPS64)
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@ -243,6 +249,7 @@ extern long *mips_locoresw[];
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#define MIPS_TBIAP() mips64_TBIAP(mips_num_tlb_entries)
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#define MIPS_TBIS mips64_TBIS
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#define MachTLBUpdate mips64_TLBUpdate
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#define MachTLBWriteIndexedVPS mips64_TLBWriteIndexedVPS
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#define proc_trampoline mips64_proc_trampoline
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#define wbflush() mips64_wbflush()
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#elif !defined(MIPS1) && defined(MIPS3) && !defined(MIPS32) && !defined(MIPS64) && defined(MIPS3_5900)
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@ -250,6 +257,7 @@ extern long *mips_locoresw[];
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#define MIPS_TBIAP() mips5900_TBIAP(mips_num_tlb_entries)
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#define MIPS_TBIS mips5900_TBIS
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#define MachTLBUpdate mips5900_TLBUpdate
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#define MachTLBWriteIndexedVPS mips5900_TLBWriteIndexedVPS
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#define proc_trampoline mips5900_proc_trampoline
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#define wbflush() mips5900_wbflush()
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#else
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@ -1,4 +1,4 @@
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/* $NetBSD: mips3_pte.h,v 1.18 2005/10/10 02:14:43 tsutsui Exp $ */
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/* $NetBSD: mips3_pte.h,v 1.19 2005/11/05 09:46:07 tsutsui Exp $ */
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/*
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* Copyright (c) 1992, 1993
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@ -181,6 +181,9 @@ struct tlb {
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#define MIPS3_PG_SIZE_MASK_TO_SIZE(pg_mask) \
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((((pg_mask) | 0x00001fff) + 1) / 2)
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#define MIPS3_PG_SIZE_TO_MASK(pg_size) \
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((((pg_size) * 2) - 1) & ~0x00001fff)
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/* NEC Vr41xx uses different pagemask values. */
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#define MIPS4100_PG_SIZE_1K 0x00000000
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#define MIPS4100_PG_SIZE_4K 0x00001800
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@ -190,3 +193,7 @@ struct tlb {
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#define MIPS4100_PG_SIZE_MASK_TO_SIZE(pg_mask) \
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((((pg_mask) | 0x000007ff) + 1) / 2)
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#define MIPS4100_PG_SIZE_TO_MASK(pg_size) \
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((((pg_size) * 2) - 1) & ~0x000007ff)
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@ -0,0 +1,103 @@
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/* $NetBSD: wired_map.h,v 1.1 2005/11/05 09:46:07 tsutsui Exp $ */
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/*-
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* Copyright (c) 2005 Tadpole Computer Inc.
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* All rights reserved.
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*
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* Written by Garrett D'Amore for Tadpole Computer Inc.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* 3. The name of Tadpole Computer Inc. may not be used to endorse
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* or promote products derived from this software without specific
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* prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY TADPOLE COMPUTER INC. ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
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* TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
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* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL TADPOLE COMPUTER INC.
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* BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*/
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#ifndef _MIPS_WIRED_MAP_H
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#define _MIPS_WIRED_MAP_H
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/*
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* Certain machines have peripheral busses which are only accessible
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* using the TLB.
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*
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* For example, certain Alchemy parts place PCI and PCMCIA busses at
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* physical address spaces which are beyond the normal 32-bit range.
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* In order to access these spaces TLB entries mapping 36-bit physical
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* addresses to 32-bit logical addresses must be used.
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*
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* Note that all wired mappings are must be 32 MB aligned. This is
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* because we use 32 MB mappings in the TLB. Changing this might get
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* us more effficent use of the address space, but it would greatly
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* complicate the code, and would also probably consume additional TLB
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* entries.
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*
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* Note that within a single 32 MB region, you can have multiple
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* decoders, but they must decode uniquely within the same 32MB of
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* physical address space.
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*
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* BEWARE: The start of KSEG2 (0xC0000000) is used by the NetBSD kernel
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* for context switching and is associated with wired entry 0. So you
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* cannot use that, as I discovered the hard way.
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*
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* Note also that at the moment this is not supported on the MIPS-I
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* ISA (but it shouldn't need it anyway.)
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*/
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#ifndef MIPS3_WIRED_SIZE
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#define MIPS3_WIRED_SIZE MIPS3_PG_SIZE_MASK_TO_SIZE(MIPS3_PG_SIZE_16M)
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#endif
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#define MIPS3_WIRED_OFFMASK (MIPS3_WIRED_SIZE - 1)
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#define MIPS3_WIRED_ENTRY_SIZE(pgsize) ((pgsize) * 2)
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#define MIPS3_WIRED_ENTRY_OFFMASK(pgsize) (MIPS3_WIRED_ENTRY_SIZE(pgsize) - 1)
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/*
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* This defines the maximum number of wired TLB entries that the wired
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* map will be allowed to consume. It can (and probably will!)
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* consume fewer, but it will not consume more. Note that NetBSD also
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* uses one wired entry for context switching (see TLB_WIRED_UPAGES),
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* and that is not included in this number.
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*/
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#ifndef MIPS3_NWIRED_ENTRY
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#define MIPS3_NWIRED_ENTRY 8 /* upper limit */
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#endif
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struct wired_map_entry {
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paddr_t pa0;
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paddr_t pa1;
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vaddr_t va;
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vsize_t pgmask;
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};
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extern struct wired_map_entry mips3_wired_map[];
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extern int mips3_nwired_page;
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/*
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* Wire down a region of the specified size.
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*/
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boolean_t mips3_wired_enter_region(vaddr_t, paddr_t, vsize_t);
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/*
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* Wire down a single page using specified page size.
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*/
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boolean_t mips3_wired_enter_page(vaddr_t, paddr_t, vsize_t);
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#endif /* _MIPS_WIRED_MAP_H */
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@ -1,4 +1,4 @@
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/* $NetBSD: mipsX_subr.S,v 1.17 2005/09/08 15:19:58 tsutsui Exp $ */
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/* $NetBSD: mipsX_subr.S,v 1.18 2005/11/05 09:46:07 tsutsui Exp $ */
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/*
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* Copyright 2002 Wasabi Systems, Inc.
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@ -118,6 +118,7 @@
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#include "opt_cputype.h"
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#include "opt_ddb.h"
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#include "opt_kgdb.h"
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#include "opt_mips3_wired.h"
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#include <sys/cdefs.h>
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@ -1593,6 +1594,68 @@ LEAF(MIPSX(SetPID))
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nop
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END(MIPSX(SetPID))
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#if defined(ENABLE_MIPS3_WIRED_MAP)
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/*--------------------------------------------------------------------------
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*
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* mipsN_TLBWriteIndexedVPS --
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*
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* Write the given entry into the TLB at the given index.
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* Pass full R4000 style TLB info including variable page size mask.
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*
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* mipsN_TLBWriteIndexed(unsigned int index, struct tlb *tlb)
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*
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* Results:
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* None.
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*
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* Side effects:
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* TLB entry set.
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*
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*--------------------------------------------------------------------------
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*/
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LEAF(MIPSX(TLBWriteIndexedVPS))
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mfc0 v1, MIPS_COP_0_STATUS # Save the status register.
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mtc0 zero, MIPS_COP_0_STATUS # Disable interrupts
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COP0_SYNC
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nop
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lw a2, 8(a1) # fetch tlb->tlb_lo0
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lw a3, 12(a1) # fetch tlb->tlb_lo1
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mfc0 v0, MIPS_COP_0_TLB_PG_MASK # Save current page mask.
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_MFC0 t0, MIPS_COP_0_TLB_HI # Save the current PID.
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_MTC0 a2, MIPS_COP_0_TLB_LO0 # Set up entry low0.
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COP0_SYNC
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_MTC0 a3, MIPS_COP_0_TLB_LO1 # Set up entry low1.
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COP0_SYNC
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nop
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lw a2, 0(a1) # fetch tlb->tlb_mask
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lw a3, 4(a1) # fetch tlb->tlb_hi
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nop
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mtc0 a0, MIPS_COP_0_TLB_INDEX # Set the index.
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COP0_SYNC
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mtc0 a2, MIPS_COP_0_TLB_PG_MASK # Set up entry pagemask.
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COP0_SYNC
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_MTC0 a3, MIPS_COP_0_TLB_HI # Set up entry high.
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COP0_SYNC
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nop
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nop
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tlbwi # Write the TLB
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COP0_SYNC
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nop
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nop
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nop # Delay for effect
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nop
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_MTC0 t0, MIPS_COP_0_TLB_HI # Restore the PID.
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COP0_SYNC
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mtc0 v0, MIPS_COP_0_TLB_PG_MASK # Restore page mask.
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COP0_SYNC
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nop
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nop
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j ra
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mtc0 v1, MIPS_COP_0_STATUS # Restore the status register
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END(MIPSX(TLBWriteIndexedVPS))
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#endif /* ENABLE_MIPS3_WIRED_MAP */
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/*--------------------------------------------------------------------------
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*
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* mipsN_TLBUpdate --
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@ -0,0 +1,201 @@
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/* $NetBSD: wired_map.c,v 1.1 2005/11/05 09:46:07 tsutsui Exp $ */
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/*-
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* Copyright (c) 2005 Tadpole Computer Inc.
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* All rights reserved.
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*
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* Written by Garrett D'Amore for Tadpole Computer Inc.
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*
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* Redistribution and use in source and binary forms, with or without
|
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* modification, are permitted provided that the following conditions
|
||||
* are met:
|
||||
* 1. Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in the
|
||||
* documentation and/or other materials provided with the distribution.
|
||||
* 3. The name of Tadpole Computer Inc. may not be used to endorse
|
||||
* or promote products derived from this software without specific
|
||||
* prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY TADPOLE COMPUTER INC. ``AS IS'' AND
|
||||
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
|
||||
* TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
|
||||
* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL TADPOLE COMPUTER INC.
|
||||
* BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
|
||||
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
|
||||
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
|
||||
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
|
||||
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
|
||||
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
||||
* POSSIBILITY OF SUCH DAMAGE.
|
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*/
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/*
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* Copyright (C) 2000 Shuichiro URATA. All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
|
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* modification, are permitted provided that the following conditions
|
||||
* are met:
|
||||
* 1. Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in the
|
||||
* documentation and/or other materials provided with the distribution.
|
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* 3. The name of the author may not be used to endorse or promote products
|
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* derived from this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
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* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
|
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* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
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* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
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* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
|
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* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
|
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
|
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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/*
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* This code is derived from similiar code in the ARC port of NetBSD, but
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* it now bears little resemblence to it owing to quite different needs
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* from the mapping logic.
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*/
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#include <sys/cdefs.h>
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__KERNEL_RCSID(0, "$NetBSD: wired_map.c,v 1.1 2005/11/05 09:46:07 tsutsui Exp $");
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#include <sys/param.h>
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#include <sys/systm.h>
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#include <uvm/uvm_extern.h>
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#include <machine/cpu.h>
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#include <machine/pte.h>
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#include <machine/vmparam.h>
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#include <machine/wired_map.h>
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#include <mips/locore.h>
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#include <mips/pte.h>
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||||
|
||||
struct wired_map_entry mips3_wired_map[MIPS3_NWIRED_ENTRY];
|
||||
int mips3_nwired_page;
|
||||
|
||||
/*
|
||||
* Lower layer API, to supply an explicit page size. It only wires a
|
||||
* single page at a time.
|
||||
*/
|
||||
boolean_t
|
||||
mips3_wired_enter_page(vaddr_t va, paddr_t pa, vsize_t pgsize)
|
||||
{
|
||||
struct tlb tlb;
|
||||
vaddr_t va0;
|
||||
int found, index;
|
||||
|
||||
/* make sure entries are aligned */
|
||||
KASSERT((va & (pgsize - 1)) == 0);
|
||||
KASSERT((pa & (pgsize - 1)) == 0);
|
||||
|
||||
/* TLB entries come in pairs: this is the first address of the pair */
|
||||
va0 = va & ~MIPS3_WIRED_ENTRY_OFFMASK(pgsize);
|
||||
|
||||
found = 0;
|
||||
for (index = 0; index < mips3_nwired_page; index++) {
|
||||
if (mips3_wired_map[index].va == va0) {
|
||||
if ((va & pgsize) == 0) {
|
||||
/* EntryLo0 */
|
||||
mips3_wired_map[index].pa0 = pa;
|
||||
} else {
|
||||
/* EntryLo1 */
|
||||
mips3_wired_map[index].pa1 = pa;
|
||||
}
|
||||
found = 1;
|
||||
break;
|
||||
}
|
||||
}
|
||||
|
||||
if (found == 0) {
|
||||
/* we have to allocate a new wired entry */
|
||||
if (mips3_nwired_page >= MIPS3_NWIRED_ENTRY) {
|
||||
#ifdef DIAGNOSTIC
|
||||
printf("mips3_wired_map: entries exhausted\n");
|
||||
#endif
|
||||
return FALSE;
|
||||
}
|
||||
|
||||
index = mips3_nwired_page;
|
||||
mips3_nwired_page++;
|
||||
if (va == va0) {
|
||||
/* EntryLo0 */
|
||||
mips3_wired_map[index].pa0 = pa;
|
||||
mips3_wired_map[index].pa1 = 0;
|
||||
} else {
|
||||
/* EntryLo1 */
|
||||
mips3_wired_map[index].pa0 = 0;
|
||||
mips3_wired_map[index].pa1 = pa;
|
||||
}
|
||||
mips3_wired_map[index].va = va0;
|
||||
mips3_wired_map[index].pgmask = MIPS3_PG_SIZE_TO_MASK(pgsize);
|
||||
|
||||
/* Allocate new wired entry */
|
||||
mips3_cp0_wired_write(MIPS3_TLB_WIRED_UPAGES +
|
||||
mips3_nwired_page + 1);
|
||||
}
|
||||
|
||||
/* map it */
|
||||
tlb.tlb_mask = mips3_wired_map[index].pgmask;
|
||||
tlb.tlb_hi = mips3_vad_to_vpn(va);
|
||||
if (mips3_wired_map[index].pa0 == 0)
|
||||
tlb.tlb_lo0 = MIPS3_PG_G;
|
||||
else
|
||||
tlb.tlb_lo0 =
|
||||
mips3_paddr_to_tlbpfn(mips3_wired_map[index].pa0) |
|
||||
MIPS3_PG_IOPAGE(
|
||||
PMAP_CCA_FOR_PA(mips3_wired_map[index].pa0));
|
||||
if (mips3_wired_map[index].pa1 == 0)
|
||||
tlb.tlb_lo1 = MIPS3_PG_G;
|
||||
else
|
||||
tlb.tlb_lo1 = mips3_paddr_to_tlbpfn(
|
||||
mips3_wired_map[index].pa1) |
|
||||
MIPS3_PG_IOPAGE(
|
||||
PMAP_CCA_FOR_PA(mips3_wired_map[index].pa1));
|
||||
MachTLBWriteIndexedVPS(MIPS3_TLB_WIRED_UPAGES + index, &tlb);
|
||||
return TRUE;
|
||||
}
|
||||
|
||||
|
||||
/*
|
||||
* Wire down a mapping from a virtual to physical address. The size
|
||||
* of the region must be a multiple of MIPS3_WIRED_SIZE, with
|
||||
* matching alignment.
|
||||
*
|
||||
* Typically the caller will just pass a physaddr that is the same as
|
||||
* the vaddr with bits 35-32 set nonzero.
|
||||
*/
|
||||
boolean_t
|
||||
mips3_wired_enter_region(vaddr_t va, paddr_t pa, vsize_t size)
|
||||
{
|
||||
vaddr_t vend;
|
||||
/*
|
||||
* This routine allows for for wired mappings to be set up,
|
||||
* and handles previously defined mappings and mapping
|
||||
* overlaps reasonably well. However, caution should be used
|
||||
* not to attempt to change the mapping for a page unless you
|
||||
* are certain that you are the only user of the virtual
|
||||
* address space, otherwise chaos may ensue.
|
||||
*/
|
||||
|
||||
/* offsets within the page have to be identical */
|
||||
KASSERT((va & MIPS3_WIRED_OFFMASK) == (pa & MIPS3_WIRED_OFFMASK));
|
||||
|
||||
vend = va + size;
|
||||
/* adjust for alignment */
|
||||
va &= ~MIPS3_WIRED_OFFMASK;
|
||||
pa &= ~MIPS3_WIRED_OFFMASK;
|
||||
|
||||
while (va < vend) {
|
||||
if (!mips3_wired_enter_page(va, pa, MIPS3_WIRED_SIZE))
|
||||
return FALSE;
|
||||
va += MIPS3_WIRED_SIZE;
|
||||
pa += MIPS3_WIRED_SIZE;
|
||||
}
|
||||
return TRUE;
|
||||
}
|
||||
Loading…
Reference in New Issue