make the dbri driver work again
while there enforce some alignment rules, adjust some timeouts, retry when probing the codec fails
This commit is contained in:
macallan
parent
2a18c897d3
commit
749b17a7c8
@ -1,7 +1,7 @@
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/* $NetBSD: cs4215var.h,v 1.2 2005/12/11 12:21:26 christos Exp $ */
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/* $NetBSD: cs4215var.h,v 1.3 2007/03/08 21:15:20 macallan Exp $ */
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/*
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* Copyright (c) 2001 Jared D. McNeill <jmcneill@invisible.yi.org>
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* Copyright (c) 2001 Jared D. McNeill <jmcneill@NetBSD.org>
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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@ -37,9 +37,15 @@
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#include <sys/types.h>
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struct cs4215_state {
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volatile u_int8_t data[4];
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volatile u_int8_t control[4];
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volatile u_int8_t onboard, offset;
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volatile u_int32_t status;
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volatile u_int32_t version;
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union {
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volatile uint32_t ldata;
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volatile uint8_t bdata[4];
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} d;
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union {
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volatile uint32_t lcontrol;
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volatile uint8_t bcontrol[4];
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} c;
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volatile uint8_t onboard, offset;
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volatile uint32_t status;
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volatile uint32_t version;
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};
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@ -1,4 +1,4 @@
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/* $NetBSD: dbri.c,v 1.8 2007/03/04 22:12:44 mrg Exp $ */
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/* $NetBSD: dbri.c,v 1.9 2007/03/08 21:15:20 macallan Exp $ */
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/*
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* Copyright (C) 1997 Rudolf Koenig (rfkoenig@immd4.informatik.uni-erlangen.de)
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@ -42,7 +42,7 @@
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*/
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#include <sys/cdefs.h>
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__KERNEL_RCSID(0, "$NetBSD: dbri.c,v 1.8 2007/03/04 22:12:44 mrg Exp $");
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__KERNEL_RCSID(0, "$NetBSD: dbri.c,v 1.9 2007/03/08 21:15:20 macallan Exp $");
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#include "audio.h"
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#if NAUDIO > 0
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@ -330,8 +330,10 @@ dbri_attach_sbus(struct device *parent, struct device *self, void *aux)
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/* map the registers into memory */
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sc->sc_dma = (struct dbri_dma *)sc->sc_membase; /* kernel virtual address of DMA buffer */
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sc->sc_dmabase = sc->sc_dmamap->dm_segs[0].ds_addr; /* physical address of DMA buffer */
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/* kernel virtual address of DMA buffer */
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sc->sc_dma = (struct dbri_dma *)sc->sc_membase;
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/* physical address of DMA buffer */
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sc->sc_dmabase = sc->sc_dmamap->dm_segs[0].ds_addr;
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sc->sc_bufsiz = size;
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sbus_establish(&sc->sc_sd, &sc->sc_dev);
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@ -365,13 +367,14 @@ dbri_set_power(struct dbri_softc *sc, int state)
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s = splhigh();
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*AUXIO4M_REG |= (AUXIO4M_MMX);
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splx(s);
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DELAY(1000);
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DPRINTF(("done\n")); /* more delay... */
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delay(10000);
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DPRINTF(("done (%02x})\n", *AUXIO4M_REG));
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} else {
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DPRINTF(("%s: powering down\n", sc->sc_dev.dv_xname));
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s = splhigh();
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*AUXIO4M_REG &= ~AUXIO4M_MMX;
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splx(s);
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DPRINTF(("done (%02x})\n", *AUXIO4M_REG));
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}
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sc->sc_powerstate = state;
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}
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@ -406,8 +409,10 @@ void
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dbri_config_interrupts(struct device *dev)
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{
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struct dbri_softc *sc = (struct dbri_softc *)dev;
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dbri_init(sc);
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mmcodec_init(sc);
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/* Attach ourselves to the high level audio interface */
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audio_attach_mi(&dbri_hw_if, sc, &sc->sc_dev);
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@ -491,6 +496,7 @@ dbri_init(struct dbri_softc *sc)
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/* Disable all SBus bursts */
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/* XXX 16 byte bursts cause errors, the rest works */
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reg = bus_space_read_4(iot, ioh, DBRI_REG0);
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/*reg &= ~(DBRI_BURST_4 | DBRI_BURST_8 | DBRI_BURST_16);*/
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reg |= (DBRI_BURST_4 | DBRI_BURST_8);
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bus_space_write_4(iot, ioh, DBRI_REG0, reg);
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@ -568,9 +574,10 @@ dbri_command_send(struct dbri_softc *sc, volatile u_int32_t *cmd)
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printf("%s: chip never completed command buffer\n",
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sc->sc_dev.dv_xname);
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} else {
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#ifdef DBRI_DEBUG
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printf("%s: command completed\n",sc->sc_dev.dv_xname);
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#endif
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DPRINTF(("%s: command completed\n",
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sc->sc_dev.dv_xname));
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while ((--maxloops) > 0 && (!sc->sc_waitseen))
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dbri_process_interrupt_buffer(sc);
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if (maxloops == 0) {
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@ -690,11 +697,12 @@ dbri_process_interrupt(struct dbri_softc *sc, int32_t i)
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dbri_command_send(sc, cmd);
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break;
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}
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case DBRI_INTR_CMDI:
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break;
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default:
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#if 0
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printf("%s: unknown interrupt code %d\n",
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sc->sc_dev.dv_xname, code);
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#endif
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DPRINTF(("%s: unknown interrupt code %d\n",
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sc->sc_dev.dv_xname, code));
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break;
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}
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@ -711,6 +719,7 @@ mmcodec_init(struct dbri_softc *sc)
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bus_space_handle_t ioh = sc->sc_ioh;
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bus_space_tag_t iot = sc->sc_iot;
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u_int32_t reg2;
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int bail;
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reg2 = bus_space_read_4(iot, ioh, DBRI_REG2);
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DPRINTF(("mmcodec_init: PIO reads %x\n", reg2));
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@ -746,10 +755,21 @@ mmcodec_init(struct dbri_softc *sc)
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sc->sc_mm.offset = sc->sc_mm.onboard ? 0 : 8;
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if (mmcodec_setcontrol(sc) == -1 || sc->sc_version == 0xff) {
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printf("%s: cs4215 probe failed at offset %d\n",
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sc->sc_dev.dv_xname, sc->sc_mm.offset);
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return (-1);
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/*
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* mmcodec_setcontrol() sometimes fails right after powerup
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* so we just try again until we either get a useful response or run
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* out of time
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*/
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bail = 0;
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while (mmcodec_setcontrol(sc) == -1 || sc->sc_version == 0xff) {
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bail++;
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if (bail > 100) {
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printf("%s: cs4215 probe failed at offset %d\n",
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sc->sc_dev.dv_xname, sc->sc_mm.offset);
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return (-1);
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}
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delay(10000);
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}
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printf("%s: cs4215 ver %d found at offset %d\n",
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@ -835,10 +855,10 @@ mmcodec_default(struct dbri_softc *sc)
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* speaker, line and headphone enable. set gain to half.
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* input is mic
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*/
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mm->data[0] = sc->sc_latt = 0x20 | CS4215_HE | CS4215_LE;
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mm->data[1] = sc->sc_ratt = 0x20 | CS4215_SE;
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mm->data[2] = CS4215_LG(0x08) | CS4215_IS | CS4215_PIO0 | CS4215_PIO1;
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mm->data[3] = CS4215_RG(0x08) | CS4215_MA(0x0f);
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mm->d.bdata[0] = sc->sc_latt = 0x20 | CS4215_HE | CS4215_LE;
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mm->d.bdata[1] = sc->sc_ratt = 0x20 | CS4215_SE;
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mm->d.bdata[2] = CS4215_LG(0x08) | CS4215_IS | CS4215_PIO0 | CS4215_PIO1;
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mm->d.bdata[3] = CS4215_RG(0x08) | CS4215_MA(0x0f);
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/*
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* control time slots 1-4
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@ -848,10 +868,10 @@ mmcodec_default(struct dbri_softc *sc)
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* 2: serial enable, CHI master, 128 bits per frame, clock 1
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* 3: tests disabled
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*/
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mm->control[0] = CS4215_RSRVD_1 | CS4215_MLB;
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mm->control[1] = CS4215_DFR_ULAW | CS4215_FREQ[0].csval;
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mm->control[2] = CS4215_XCLK | CS4215_BSEL_128 | CS4215_FREQ[0].xtal;
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mm->control[3] = 0;
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mm->c.bcontrol[0] = CS4215_RSRVD_1 | CS4215_MLB;
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mm->c.bcontrol[1] = CS4215_DFR_ULAW | CS4215_FREQ[0].csval;
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mm->c.bcontrol[2] = CS4215_XCLK | CS4215_BSEL_128 | CS4215_FREQ[0].xtal;
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mm->c.bcontrol[3] = 0;
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return;
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}
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@ -861,8 +881,8 @@ mmcodec_setgain(struct dbri_softc *sc, int mute)
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{
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if (mute) {
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/* disable all outputs, max. attenuation */
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sc->sc_mm.data[0] = sc->sc_latt | 63;
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sc->sc_mm.data[1] = sc->sc_ratt | 63;
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sc->sc_mm.d.bdata[0] = sc->sc_latt | 63;
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sc->sc_mm.d.bdata[1] = sc->sc_ratt | 63;
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} else {
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/*
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* We should be setting the proper output here.. for now,
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@ -874,13 +894,13 @@ mmcodec_setgain(struct dbri_softc *sc, int mute)
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* Speaker:
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* data[1] |= CS4215_SE;
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*/
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sc->sc_mm.data[0] = sc->sc_latt;
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sc->sc_mm.data[1] = sc->sc_ratt;
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sc->sc_mm.d.bdata[0] = sc->sc_latt;
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sc->sc_mm.d.bdata[1] = sc->sc_ratt;
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}
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if (sc->sc_powerstate == 0)
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return;
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pipe_transmit_fixed(sc, 20, *(u_int32_t *)__UNVOLATILE(sc->sc_mm.data));
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pipe_transmit_fixed(sc, 20, sc->sc_mm.d.ldata);
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/* give the chip some time to execure the command */
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delay(250);
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@ -904,7 +924,7 @@ mmcodec_setcontrol(struct dbri_softc *sc)
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* happens. This avoids clicking noises.
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*/
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mmcodec_setgain(sc, 1);
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//DELAY(125);
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delay(125);
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/* enable control mode */
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val = DBRI_PIO_ENABLE_ALL | DBRI_PIO1; /* was PIO1 */
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@ -914,7 +934,7 @@ mmcodec_setcontrol(struct dbri_softc *sc)
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bus_space_write_4(iot, ioh, DBRI_REG2, val);
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DELAY(34);
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delay(34);
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/*
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* in control mode, the cs4215 is the slave device, so the
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@ -935,8 +955,8 @@ mmcodec_setcontrol(struct dbri_softc *sc)
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pipe_ts_link(sc, 19, PIPEinput, 16, 8, sc->sc_mm.offset + 48);
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/* wait for the chip to echo back CLB as zero */
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sc->sc_mm.control[0] &= ~CS4215_CLB;
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pipe_transmit_fixed(sc, 17, *(int *)__UNVOLATILE(sc->sc_mm.control));
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sc->sc_mm.c.bcontrol[0] &= ~CS4215_CLB;
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pipe_transmit_fixed(sc, 17, sc->sc_mm.c.lcontrol);
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tmp = bus_space_read_4(iot, ioh, DBRI_REG0);
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tmp |= DBRI_CHI_ACTIVATE;
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@ -961,14 +981,14 @@ mmcodec_setcontrol(struct dbri_softc *sc)
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#endif
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/* copy the version information before it becomes unreadable again */
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sc->sc_version=sc->sc_mm.version;
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sc->sc_version = sc->sc_mm.version;
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/* terminate cs4215 control mode */
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sc->sc_mm.control[0] |= CS4215_CLB;
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pipe_transmit_fixed(sc, 17, *(int *)__UNVOLATILE(sc->sc_mm.control));
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sc->sc_mm.c.bcontrol[0] |= CS4215_CLB;
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pipe_transmit_fixed(sc, 17, sc->sc_mm.c.lcontrol);
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/* two frames of control info @ 8kHz frame rate = 250us delay */
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DELAY(250);
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delay(250);
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mmcodec_setgain(sc, 0);
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@ -1456,54 +1476,54 @@ dbri_set_params(void *hdl, int setmode, int usemode,
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return (EINVAL);
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/* set frequency */
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sc->sc_mm.control[1] &= ~0x38;
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sc->sc_mm.control[1] |= CS4215_FREQ[i].csval;
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sc->sc_mm.control[2] &= ~0x70;
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sc->sc_mm.control[2] |= CS4215_FREQ[i].xtal;
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sc->sc_mm.c.bcontrol[1] &= ~0x38;
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sc->sc_mm.c.bcontrol[1] |= CS4215_FREQ[i].csval;
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sc->sc_mm.c.bcontrol[2] &= ~0x70;
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sc->sc_mm.c.bcontrol[2] |= CS4215_FREQ[i].xtal;
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/*play->factor = 1;
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play->sw_code = NULL;*/
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switch (play->encoding) {
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case AUDIO_ENCODING_ULAW:
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sc->sc_mm.control[1] &= ~3;
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sc->sc_mm.control[1] |= CS4215_DFR_ULAW;
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sc->sc_mm.c.bcontrol[1] &= ~3;
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sc->sc_mm.c.bcontrol[1] |= CS4215_DFR_ULAW;
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break;
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case AUDIO_ENCODING_ALAW:
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sc->sc_mm.control[1] &= ~3;
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sc->sc_mm.control[1] |= CS4215_DFR_ALAW;
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sc->sc_mm.c.bcontrol[1] &= ~3;
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sc->sc_mm.c.bcontrol[1] |= CS4215_DFR_ALAW;
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break;
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case AUDIO_ENCODING_SLINEAR_LE:
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case AUDIO_ENCODING_ULINEAR_LE:
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if (play->precision == 16) {
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/* XXX this surely needs some changes elsewhere */
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/*play->sw_code = swap_bytes;*/
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sc->sc_mm.control[1] &= ~3;
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sc->sc_mm.control[1] |= CS4215_DFR_LINEAR16;
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sc->sc_mm.c.bcontrol[1] &= ~3;
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sc->sc_mm.c.bcontrol[1] |= CS4215_DFR_LINEAR16;
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}
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break;
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case AUDIO_ENCODING_ULINEAR:
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case AUDIO_ENCODING_SLINEAR:
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sc->sc_mm.control[1] &= ~3;
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sc->sc_mm.c.bcontrol[1] &= ~3;
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if (play->precision == 8) {
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sc->sc_mm.control[1] |= CS4215_DFR_LINEAR8;
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sc->sc_mm.c.bcontrol[1] |= CS4215_DFR_LINEAR8;
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} else {
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sc->sc_mm.control[1] |= CS4215_DFR_LINEAR16;
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sc->sc_mm.c.bcontrol[1] |= CS4215_DFR_LINEAR16;
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}
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break;
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case AUDIO_ENCODING_ULINEAR_BE:
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case AUDIO_ENCODING_SLINEAR_BE:
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sc->sc_mm.control[1] &= ~3;
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sc->sc_mm.control[1] |= CS4215_DFR_LINEAR16;
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sc->sc_mm.c.bcontrol[1] &= ~3;
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sc->sc_mm.c.bcontrol[1] |= CS4215_DFR_LINEAR16;
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break;
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}
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switch (play->channels) {
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case 1:
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sc->sc_mm.control[1] &= ~CS4215_DFR_STEREO;
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sc->sc_mm.c.bcontrol[1] &= ~CS4215_DFR_STEREO;
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break;
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case 2:
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sc->sc_mm.control[1] |= CS4215_DFR_STEREO;
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sc->sc_mm.c.bcontrol[1] |= CS4215_DFR_STEREO;
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break;
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}
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@ -1,4 +1,4 @@
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/* $NetBSD: dbrireg.h,v 1.4 2006/03/09 20:44:18 macallan Exp $ */
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/* $NetBSD: dbrireg.h,v 1.5 2007/03/08 21:15:21 macallan Exp $ */
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/*
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* Copyright (C) 1997 Rudolf Koenig (rfkoenig@immd4.informatik.uni-erlangen.de)
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@ -77,6 +77,7 @@
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/* interrupts */
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#define DBRI_INTR_BRDY 1 /* buffer ready for processing */
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#define DBRI_INTR_CMDI 6 /* command has been read */
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#define DBRI_INTR_XCMP 8 /* transmission of frame complete */
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#define DBRI_INTR_SBRI 9 /* BRI status change info */
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#define DBRI_INTR_FXDT 10 /* fixed data change */
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