First attempt to spin up the secondary processor on 180MP and 200MP.
XXX Need more work.
This commit is contained in:
tsubai
parent
f6f00e2615
commit
73db3f2b79
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@ -1,4 +1,4 @@
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/* $NetBSD: cpu.c,v 1.6 2000/02/08 12:49:06 tsubai Exp $ */
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/* $NetBSD: cpu.c,v 1.7 2000/07/05 16:02:38 tsubai Exp $ */
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/*-
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* Copyright (C) 1998, 1999 Internet Research Institute, Inc.
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@ -31,26 +31,55 @@
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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#include "opt_multiprocessor.h"
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#include <sys/param.h>
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#include <sys/systm.h>
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#include <sys/device.h>
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#include <uvm/uvm_extern.h>
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#include <dev/ofw/openfirm.h>
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#include <machine/autoconf.h>
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#include <machine/bat.h>
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#include <machine/pcb.h>
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#include <machine/pio.h>
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static int cpumatch __P((struct device *, struct cfdata *, void *));
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static void cpuattach __P((struct device *, struct device *, void *));
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int cpumatch(struct device *, struct cfdata *, void *);
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void cpuattach(struct device *, struct device *, void *);
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static void ohare_init __P((void));
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static void display_l2cr __P((void));
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void identifycpu(char *);
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static void ohare_init(void);
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static void display_l2cr(void);
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int cpu_spinup(void);
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void cpu_hatch(void);
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void cpu_spinup_trampoline(void);
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struct cfattach cpu_ca = {
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sizeof(struct device), cpumatch, cpuattach
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};
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int ncpus;
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extern struct cfdriver cpu_cd;
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extern int powersave;
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#define HAMMERHEAD 0xf8000000
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#define HH_ARBCONF (HAMMERHEAD + 0x90)
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#define HH_INTR (HAMMERHEAD + 0xc0)
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/* XXX for now */
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#undef cpu_number
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static inline int
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cpu_number()
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{
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int pir;
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asm ("mfspr %0,1023" : "=r"(pir));
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return pir;
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}
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int
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cpumatch(parent, cf, aux)
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struct device *parent;
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@ -58,11 +87,23 @@ cpumatch(parent, cf, aux)
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void *aux;
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{
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struct confargs *ca = aux;
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int *reg = ca->ca_reg;
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int hammerhead;
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if (strcmp(ca->ca_name, cpu_cd.cd_name))
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return 0;
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return 1;
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switch (reg[0]) {
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case 0: /* master CPU */
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return 1;
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case 1: /* secondary CPU */
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hammerhead = OF_finddevice("/hammerhead");
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if (hammerhead == -1)
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return 0;
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if (in32rb(HH_ARBCONF) & 0x02)
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return 1;
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}
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return 0;
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}
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#define MPC601 1
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@ -83,7 +124,29 @@ cpuattach(parent, self, aux)
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struct device *parent, *self;
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void *aux;
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{
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struct confargs *ca = aux;
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int *reg = ca->ca_reg;
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int hid0, pvr;
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char model[80];
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ncpus++;
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switch (reg[0]) {
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case 0:
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asm volatile ("mtspr 1023,%0" :: "r"(0)); /* PIR */
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identifycpu(model);
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printf(": %s, ID %d (primary)", model, cpu_number());
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break;
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/* #ifdef MULTIPROCESSOR */
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case 1:
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cpu_spinup();
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printf("\n");
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return;
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/* #endif */
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default:
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printf(": more than 2 cpus?\n");
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panic("cpuattach");
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}
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__asm __volatile ("mfpvr %0" : "=r"(pvr));
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switch (pvr >> 16) {
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@ -116,6 +179,47 @@ cpuattach(parent, self, aux)
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printf("\n");
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}
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struct cputab {
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int version;
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char *name;
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};
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static struct cputab models[] = {
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{ 1, "601" },
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{ 3, "603" },
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{ 4, "604" },
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{ 5, "602" },
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{ 6, "603e" },
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{ 7, "603ev" },
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{ 8, "750" },
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{ 9, "604ev" },
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{ 12, "7400" },
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{ 20, "620" },
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{ 0, NULL }
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};
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void
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identifycpu(cpu_model)
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char *cpu_model;
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{
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int pvr, vers, rev;
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struct cputab *cp = models;
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asm ("mfpvr %0" : "=r"(pvr));
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vers = pvr >> 16;
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rev = pvr & 0xffff;
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while (cp->name) {
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if (cp->version == vers)
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break;
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cp++;
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}
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if (cp->name)
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strcpy(cpu_model, cp->name);
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else
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sprintf(cpu_model, "Version %x", vers);
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sprintf(cpu_model + strlen(cpu_model), " (Revision %x)", rev);
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}
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#define CACHE_REG 0xf8000000
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void
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@ -210,3 +314,162 @@ display_l2cr()
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}
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printf("\n");
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}
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/* #ifdef MULTIPROCESSOR */
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struct cpu_hatch_data {
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int running;
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int pir;
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int hid0;
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int sdr1;
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int sr[16];
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int tbu, tbl;
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};
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volatile struct cpu_hatch_data *cpu_hatch_data;
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volatile int cpu_hatchstack;
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int
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cpu_spinup()
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{
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volatile struct cpu_hatch_data hatch_data, *h = &hatch_data;
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int i;
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struct pcb *pcb;
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struct pglist mlist;
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int error;
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/*
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* Allocate UPAGES contiguous pages for the idle PCB and stack
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* from the lowest 256MB (because bat0 always maps it va == pa).
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*/
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TAILQ_INIT(&mlist);
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error = uvm_pglistalloc(USPACE, 0x0, 0x10000000, 0, 0, &mlist, 1, 1);
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if (error) {
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printf(": unable to allocate idle stack");
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return -1;
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}
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pcb = (void *)VM_PAGE_TO_PHYS(TAILQ_FIRST(&mlist));
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bzero(pcb, USPACE);
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/*
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* Initialize the idle stack pointer, reserving space for an
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* (empty) trapframe (XXX is the trapframe really necessary?)
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*/
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pcb->pcb_sp = (paddr_t)pcb + USPACE - sizeof(struct trapframe);
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cpu_hatch_data = h;
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h->running = 0;
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h->pir = 1;
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cpu_hatchstack = pcb->pcb_sp;
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/* copy special registers */
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asm volatile ("mfspr %0,1008" : "=r"(h->hid0));
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asm volatile ("mfsdr1 %0" : "=r"(h->sdr1));
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for (i = 0; i < 16; i++)
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asm ("mfsrin %0,%1" : "=r"(h->sr[i]) : "r"(i << ADDR_SR_SHFT));
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asm volatile ("sync; isync");
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/* Start secondary cpu and stop timebase. */
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out32(0xf2800000, (int)cpu_spinup_trampoline);
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out32(HH_INTR, ~0);
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out32(HH_INTR, 0);
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/* sync timebase (XXX shouldn't be zero'ed) */
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asm volatile ("mttbl %0; mttbu %0; mttbl %0" :: "r"(0));
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/*
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* wait for secondary spin up (1.5ms @ 604/200MHz)
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* XXX we cannot use delay() here because timebase is not running.
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*/
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for (i = 0; i < 100000; i++)
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if (h->running)
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break;
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/* Start timebase. */
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out32(0xf2800000, 0x100);
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out32(HH_INTR, ~0);
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out32(HH_INTR, 0);
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delay(100000); /* wait for secondary printf */
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if (h->running == 0) {
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printf(": secondary cpu didn't start");
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return -1;
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}
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return 0;
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}
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void
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cpu_hatch()
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{
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volatile struct cpu_hatch_data *h = cpu_hatch_data;
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u_int msr;
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int i;
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char model[80];
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/* Initialize timebase. */
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asm ("mttbl %0; mttbu %0; mttbl %0" :: "r"(0));
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/* Set PIR (Processor Identification Register). i.e. whoami */
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asm volatile ("mtspr 1023,%0" :: "r"(h->pir));
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/* Initialize MMU. */
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asm ("mtibatu 0,%0" :: "r"(0));
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asm ("mtibatu 1,%0" :: "r"(0));
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asm ("mtibatu 2,%0" :: "r"(0));
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asm ("mtibatu 3,%0" :: "r"(0));
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asm ("mtdbatu 0,%0" :: "r"(0));
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asm ("mtdbatu 1,%0" :: "r"(0));
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asm ("mtdbatu 2,%0" :: "r"(0));
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asm ("mtdbatu 3,%0" :: "r"(0));
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asm ("mtspr 1008,%0" :: "r"(h->hid0));
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asm ("mtibatl 0,%0; mtibatu 0,%1;"
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"mtdbatl 0,%0; mtdbatu 0,%1;"
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:: "r"(battable[0].batl), "r"(battable[0].batu));
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/* XXX obio (for now) */
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asm ("mtibatl 1,%0; mtibatu 1,%1;"
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"mtdbatl 1,%0; mtdbatu 1,%1;"
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:: "r"(battable[0xf].batl), "r"(battable[0xf].batu));
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for (i = 0; i < 16; i++)
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asm ("mtsrin %0,%1" :: "r"(h->sr[i]), "r"(i << ADDR_SR_SHFT));
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asm ("mtsdr1 %0" :: "r"(h->sdr1));
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asm volatile ("isync");
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/* Enable I/D address translations. */
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asm volatile ("mfmsr %0" : "=r"(msr));
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msr |= PSL_IR|PSL_DR|PSL_ME|PSL_RI;
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asm volatile ("mtmsr %0" :: "r"(msr));
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asm volatile ("sync; isync");
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h->running = 1;
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identifycpu(model);
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printf(": %s, ID %d", model, cpu_number());
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/* XXX Enter power-saving mode and never return. */
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asm volatile ("
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1:
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sync
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mtmsr %0
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isync
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b 1b
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" :: "r"(PSL_POW));
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for (;;);
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}
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/* #endif MULTIPROCESSOR */
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#ifdef MULTIPROCESSOR
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void
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cpu_boot_secondary_processors()
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{
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/* currently noop */
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}
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#endif /* MULTIPROCESSOR */
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@ -1,4 +1,4 @@
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/* $NetBSD: locore.S,v 1.24 2000/05/31 05:09:17 thorpej Exp $ */
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/* $NetBSD: locore.S,v 1.25 2000/07/05 16:02:39 tsubai Exp $ */
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/*
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* Copyright (C) 1995, 1996 Wolfgang Solfrank.
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@ -1486,3 +1486,25 @@ _C_LABEL(setfault):
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stmw 12,12(3)
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xor 3,3,3
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blr
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/* #ifdef MULTIPROCESSOR */
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.globl _C_LABEL(cpu_spinup_trampoline)
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_C_LABEL(cpu_spinup_trampoline):
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li 0,0
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mtmsr 0
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isync
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lis 3,cpu_hatchstack@ha
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lwz 1,cpu_hatchstack@l(3)
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bl _C_LABEL(cpu_hatch)
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1:
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sync
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mfmsr 3
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oris 3,3,PSL_POW@h
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mtmsr 3
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isync
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b 1b
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/* #endif */
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@ -1,4 +1,4 @@
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/* $NetBSD: machdep.c,v 1.77 2000/07/02 04:40:39 cgd Exp $ */
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/* $NetBSD: machdep.c,v 1.78 2000/07/05 16:02:39 tsubai Exp $ */
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/*
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* Copyright (C) 1995, 1996 Wolfgang Solfrank.
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@ -392,60 +392,10 @@ restore_ofw_mapping()
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/*
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* This should probably be in autoconf! XXX
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*/
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int cpu;
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char cpu_model[80];
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char machine[] = MACHINE; /* from <machine/param.h> */
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char machine_arch[] = MACHINE_ARCH; /* from <machine/param.h> */
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void
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identifycpu()
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{
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int pvr;
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/*
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* Find cpu type (Do it by OpenFirmware?)
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*/
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asm ("mfpvr %0" : "=r"(pvr));
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cpu = pvr >> 16;
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switch (cpu) {
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case 1:
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sprintf(cpu_model, "601");
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break;
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case 3:
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sprintf(cpu_model, "603");
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break;
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case 4:
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sprintf(cpu_model, "604");
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break;
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case 5:
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sprintf(cpu_model, "602");
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break;
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case 6:
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sprintf(cpu_model, "603e");
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break;
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case 7:
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sprintf(cpu_model, "603ev");
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break;
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case 8:
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sprintf(cpu_model, "750");
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break;
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case 9:
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sprintf(cpu_model, "604ev");
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break;
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case 12:
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sprintf(cpu_model, "7400");
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break;
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case 20:
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sprintf(cpu_model, "620");
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break;
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default:
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sprintf(cpu_model, "Version %x", cpu);
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break;
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}
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sprintf(cpu_model + strlen(cpu_model), " (Revision %x)", pvr & 0xffff);
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printf("CPU: %s\n", cpu_model);
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}
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void
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install_extint(handler)
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void (*handler) __P((void));
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@ -486,7 +436,7 @@ cpu_startup()
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v = (caddr_t)proc0paddr + USPACE;
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printf("%s", version);
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identifycpu();
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identifycpu(cpu_model);
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format_bytes(pbuf, sizeof(pbuf), ctob(physmem));
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printf("total memory = %s\n", pbuf);
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@ -1,4 +1,4 @@
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/* $NetBSD: mainbus.c,v 1.7 2000/02/03 19:27:45 tsubai Exp $ */
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/* $NetBSD: mainbus.c,v 1.8 2000/07/05 16:02:39 tsubai Exp $ */
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/*
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* Copyright (c) 1996 Christopher G. Demetriou. All rights reserved.
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@ -69,12 +69,19 @@ mainbus_attach(parent, self, aux)
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{
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struct ofbus_attach_args oba;
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struct confargs ca;
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int node;
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int node, i;
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u_int32_t reg[4];
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char name[32];
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printf("\n");
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for (i = 0; i < 2; i++) {
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ca.ca_name = "cpu";
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ca.ca_reg = reg;
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reg[0] = i;
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config_found(self, &ca, NULL);
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}
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node = OF_peer(0);
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if (node) {
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oba.oba_busname = "ofw";
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@ -82,9 +89,6 @@ mainbus_attach(parent, self, aux)
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config_found(self, &oba, NULL);
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}
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ca.ca_name = "cpu";
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config_found(self, &ca, NULL);
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for (node = OF_child(OF_finddevice("/")); node; node = OF_peer(node)) {
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bzero(name, sizeof(name));
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if (OF_getprop(node, "name", name, sizeof(name)) == -1)
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