risc-v: add a SiFive FU[57]40/ L2 Cache controller driver
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skrll
parent
d1d52dee1a
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73ce3dc071
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@ -1,4 +1,4 @@
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# $NetBSD: GENERIC64,v 1.1 2023/05/07 12:41:48 skrll Exp $
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# $NetBSD: GENERIC64,v 1.2 2024/01/13 17:01:58 skrll Exp $
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#
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# GENERIC machine description file
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#
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@ -46,5 +46,8 @@ options DEBUG # expensive debugging checks/support
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#options COMPAT_NETBSD32
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#options EXEC_ELF32
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# Cache controller
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ccache* at fdt? # SiFive FU[57]40 L2 Cache
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# Pull in optional local configuration - always at end
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cinclude "arch/riscv/conf/GENERIC64.local"
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@ -1,4 +1,4 @@
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# $NetBSD: files.sifive,v 1.2 2022/12/03 09:40:56 skrll Exp $
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# $NetBSD: files.sifive,v 1.3 2024/01/13 17:01:58 skrll Exp $
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#
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# Configuration info for SiFive SoCs
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#
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@ -8,3 +8,8 @@
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device prci
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attach prci at fdt with fu540_prci
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file arch/riscv/sifive/fu540_prci.c fu540_prci
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# FU540 Level 2 Cache controller
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device ccache: fdt
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attach ccache at fdt with fu540_ccache
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file arch/riscv/sifive/fu540_ccache.c fu540_ccache
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/* $NetBSD: fu540_ccache.c,v 1.1 2024/01/13 17:01:58 skrll Exp $ */
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/*-
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* Copyright (c) 2023 The NetBSD Foundation, Inc.
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* All rights reserved.
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*
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* This code is derived from software contributed to The NetBSD Foundation
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* by Nick Hudson
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
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* ``AS IS'' AND ANY EXPRESS OR IMPLinIED WARRANTIES, INCLUDING, BUT NOT LIMITED
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* TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
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* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
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* BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*/
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#include <sys/cdefs.h>
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__KERNEL_RCSID(0, "$NetBSD: fu540_ccache.c,v 1.1 2024/01/13 17:01:58 skrll Exp $");
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#include <sys/param.h>
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#include <sys/bus.h>
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#include <dev/fdt/fdtvar.h>
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#include <machine/cpufunc.h>
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#define CCACHE_CONFIG 0x0000
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#define CCACHE_CONFIG_BANKS_MASK __BITS( 7, 0)
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#define CCACHE_CONFIG_WAYS_MASK __BITS(15, 8)
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#define CCACHE_CONFIG_LGSETS_MASK __BITS(23, 16)
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#define CCACHE_CONFIG_LGBLOCKBYTES_MASK __BITS(31, 24)
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#define CCACHE_WAYENABLE 0x0008
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#define CCACHE_ECCINJECTERROR 0x0040
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#define CCACHE_DIRECCFIX_LOW 0x0100
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#define CCACHE_DIRECCFIX_HIGH 0x0104
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#define CCACHE_DIRECCFIX_COUNT 0x0108
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#define CCACHE_DIRECCFAIL_LOW 0x0120
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#define CCACHE_DIRECCFAIL_HIGH 0x0124
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#define CCACHE_DIRECCFAIL_COUNT 0x0128
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#define CCACHE_DATECCFIX_LOW 0x0140
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#define CCACHE_DATECCFIX_HIGH 0x0144
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#define CCACHE_DATECCFIX_COUNT 0x0148
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#define CCACHE_DATECCFAIL_LOW 0x0160
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#define CCACHE_DATECCFAIL_HIGH 0x0164
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#define CCACHE_DATECCFAIL_COUNT 0x0168
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#define CCACHE_FLUSH64 0x0200
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#define CCACHE_FLUSH32 0x0250
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#define CCACHE_MAX_ECCINTR 4
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#define CCACHE_FLUSH64_LINE_LEN 64
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static const struct device_compatible_entry compat_data[] = {
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{ .compat = "sifive,fu540-c000-ccache" },
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{ .compat = "sifive,fu740-c000-ccache" },
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DEVICE_COMPAT_EOL
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};
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struct fu540_ccache_softc {
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device_t sc_dev;
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bus_space_tag_t sc_bst;
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bus_space_handle_t sc_bsh;
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uint32_t sc_line_size;
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uint32_t sc_size;
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uint32_t sc_sets;
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uint32_t sc_level;
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};
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static struct fu540_ccache_softc *fu540_ccache_sc;
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#define RD4(sc, reg) \
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bus_space_read_4((sc)->sc_bst, (sc)->sc_bsh, (reg))
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#define WR4(sc, reg, val) \
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bus_space_write_4((sc)->sc_bst, (sc)->sc_bsh, (reg), (val))
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#define WR8(sc, reg, val) \
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bus_space_write_8((sc)->sc_bst, (sc)->sc_bsh, (reg), (val))
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static void
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fu540_ccache_cache_wbinv_range(vaddr_t va, paddr_t pa, psize_t len)
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{
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struct fu540_ccache_softc * const sc = fu540_ccache_sc;
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KASSERT(powerof2(sc->sc_line_size));
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KASSERT(len != 0);
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const paddr_t spa = rounddown2(pa, sc->sc_line_size);
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const paddr_t epa = roundup2(pa + len, sc->sc_line_size);
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asm volatile ("fence iorw,iorw" ::: "memory");
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for (paddr_t fpa = spa; fpa < epa; fpa += sc->sc_line_size) {
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#ifdef _LP64
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WR8(sc, CCACHE_FLUSH64, fpa);
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#else
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WR4(sc, CCACHE_FLUSH32, fpa >> 4);
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#endif
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asm volatile ("fence iorw,iorw" ::: "memory");
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}
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}
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static int
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fu540_ccache_match(device_t parent, cfdata_t cf, void *aux)
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{
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struct fdt_attach_args * const faa = aux;
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return of_compatible_match(faa->faa_phandle, compat_data);
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}
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static void
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fu540_ccache_attach(device_t parent, device_t self, void *aux)
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{
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struct fu540_ccache_softc * const sc = device_private(self);
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const struct fdt_attach_args * const faa = aux;
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const int phandle = faa->faa_phandle;
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bus_addr_t addr;
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bus_size_t size;
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int error;
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error = fdtbus_get_reg(phandle, 0, &addr, &size);
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if (error) {
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aprint_error(": couldn't get registers\n");
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return;
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}
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sc->sc_dev = self;
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sc->sc_bst = faa->faa_bst;
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error = bus_space_map(sc->sc_bst, addr, size, 0, &sc->sc_bsh);
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if (error) {
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aprint_error(": couldn't map registers\n");
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return;
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}
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int ret;
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ret = of_getprop_uint32(phandle, "cache-block-size",
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&sc->sc_line_size);
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if (ret < 0) {
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aprint_error(": can't get cache-block-size\n");
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return;
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}
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ret = of_getprop_uint32(phandle, "cache-level",
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&sc->sc_level);
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if (ret < 0) {
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aprint_error(": can't get cache-level\n");
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return;
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}
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ret = of_getprop_uint32(phandle, "cache-sets",
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&sc->sc_sets);
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if (ret < 0) {
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aprint_error(": can't get cache-sets\n");
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return;
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}
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ret = of_getprop_uint32(phandle, "cache-size",
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&sc->sc_size);
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if (ret < 0) {
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aprint_error(": can't get cache-size\n");
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return;
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}
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if (!of_hasprop(phandle, "cache-unified")) {
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aprint_error(": can't get cache-unified\n");
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return;
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}
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uint32_t ways = sc->sc_size / (sc->sc_sets * sc->sc_line_size);
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aprint_naive("\n");
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aprint_normal(": L%u cache controller. %u KiB/%uB %u-way (%u set).\n",
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sc->sc_level, sc->sc_size / 1024, sc->sc_line_size, ways,
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sc->sc_sets);
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uint32_t l2config = RD4(sc, CCACHE_CONFIG);
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aprint_debug_dev(self, "l2config %#10" PRIx32 "\n",
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l2config);
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aprint_verbose_dev(self, "No. of banks %4" __PRIuBIT "\n",
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__SHIFTOUT(l2config, CCACHE_CONFIG_BANKS_MASK));
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aprint_verbose_dev(self, "No. of ways per bank %4" __PRIuBIT "\n",
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__SHIFTOUT(l2config, CCACHE_CONFIG_WAYS_MASK));
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aprint_verbose_dev(self, "Sets per bank %4lu\n",
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1UL << __SHIFTOUT(l2config, CCACHE_CONFIG_LGSETS_MASK));
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aprint_verbose_dev(self, "Bytes per cache block %4lu\n",
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1UL << __SHIFTOUT(l2config, CCACHE_CONFIG_LGBLOCKBYTES_MASK));
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uint32_t l2wayenable = RD4(sc, CCACHE_WAYENABLE);
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aprint_verbose_dev(self, "Largest way enabled %4" PRIu32 "\n",
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l2wayenable);
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fu540_ccache_sc = sc;
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cpu_sdcache_wbinv_range = fu540_ccache_cache_wbinv_range;
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cpu_sdcache_inv_range = fu540_ccache_cache_wbinv_range;
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cpu_sdcache_wb_range = fu540_ccache_cache_wbinv_range;
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}
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CFATTACH_DECL_NEW(fu540_ccache, sizeof(struct fu540_ccache_softc),
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fu540_ccache_match, fu540_ccache_attach, NULL, NULL);
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