Clean out some of the junk from this file, sepcifically definitions for
an Amiga DMA controller, and #if 0'ed WD33C93 definitions that are duplicated in sbicreg.h. uPD71071 definitions can stay for now, since they're not actually useless even though they're unused.
This commit is contained in:
bjh21
parent
c1f7db8026
commit
72e11b654e
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@ -1,4 +1,4 @@
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/* $NetBSD: ascreg.h,v 1.5 2006/03/08 23:46:22 lukem Exp $ */
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/* $NetBSD: ascreg.h,v 1.6 2006/08/20 19:26:52 bjh21 Exp $ */
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/*
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* Copyright (c) 1982, 1990 The Regents of the University of California.
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@ -69,73 +69,12 @@
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#ifndef _ASCREG_H_
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#define _ASCREG_H_
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/*
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* Hardware layout of the A3000 SDMAC. This also contains the
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* registers for the sbic chip, but in favor of separating DMA and
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* scsi, the scsi-driver doesn't make use of this dependency
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*/
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#define v_char volatile char
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#define v_int volatile int
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#define vu_char volatile u_char
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#define vu_short volatile u_short
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#define vu_int volatile u_int
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struct sdmac {
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short pad0;
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vu_short DAWR; /* DACK Width Register WO */
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vu_int WTC; /* Word Transfer Count Register RW */
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short pad1;
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vu_short CNTR; /* Control Register RW */
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vu_int ACR; /* Address Count Register RW */
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short pad2;
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vu_short ST_DMA; /* Start DMA Transfers RW-Strobe */
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short pad3;
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vu_short FLUSH; /* Flush FIFO RW-Strobe */
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short pad4;
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vu_short CINT; /* Clear Interrupts RW-Strobe */
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short pad5;
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vu_short ISTR; /* Interrupt Status Register RO */
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int pad6[7];
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short pad7;
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vu_short SP_DMA; /* Stop DMA Transfers RW-Strobe */
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char pad8;
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vu_char SASR; /* sbic asr */
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char pad9;
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vu_char SCMD; /* sbic data */
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};
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/*
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* value to go into DAWR
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*/
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#define DAWR_AHSC 3 /* according to A3000T service-manual */
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/*
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* bits defined for CNTR
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*/
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#define CNTR_TCEN (1<<5) /* Terminal Count Enable */
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#define CNTR_PREST (1<<4) /* Perp Reset (not implemented :-((( ) */
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#define CNTR_PDMD (1<<3) /* Perp Device Mode Select (1=SCSI,0=XT/AT) */
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#define CNTR_INTEN (1<<2) /* Interrupt Enable */
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#define CNTR_DDIR (1<<1) /* Device Direction. 1==rd host, wr perp */
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#define CNTR_IO_DX (1<<0) /* IORDY & CSX1 Polarity Select */
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/*
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* bits defined for ISTR
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*/
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#define ISTR_INTX (1<<8) /* XT/AT Interrupt pending */
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#define ISTR_INT_F (1<<7) /* Interrupt Follow */
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#define ISTR_INTS (1<<6) /* SCSI Peripheral Interrupt */
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#define ISTR_E_INT (1<<5) /* End-Of-Process Interrupt */
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#define ISTR_INT_P (1<<4) /* Interrupt Pending */
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#define ISTR_UE_INT (1<<3) /* Under-Run FIFO Error Interrupt */
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#define ISTR_OE_INT (1<<2) /* Over-Run FIFO Error Interrupt */
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#define ISTR_FF_FLG (1<<1) /* FIFO-Full Flag */
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#define ISTR_FE_FLG (1<<0) /* FIFO-Empty Flag */
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#define DMAGO_READ 0x01
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/* Addresses relative to podule base */
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#define ASC_INTSTATUS 0x2000
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@ -157,96 +96,12 @@ struct sdmac {
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#define IS_SBIC_IRQ 0x08
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#if 0
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/* SBIC Commands */
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#define SBIC_CMD_Reset 0x00 /* Reset the SBIC */
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#define SBIC_Abort 0x01 /* Abort command */
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#define SBIC_Sel_tx_wATN 0x08 /* Select and Transfer with ATN */
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#define SBIC_Sel_tx_woATN 0x09 /* Select and Transfer without ATN */
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/* SBIC status codes */
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#define SBIC_ResetOk 0x00
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#define SBIC_ResetAFOk 0x01
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/* SBIC registers bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 */
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#define SBIC_OWNID 0x00 /* RW FS1 FS0 0 EHP EAF ID2 ID1 ID0 */
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#define SBIC_CONTROL 0x01 /* RW DM2 DM1 DM0 HHP EDI IDI HA HSP */
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#define SBIC_TIMEREG 0x02 /* RW timeout period value = Tper*Ficlk/80d */
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#define SBIC_CDB1TSECT 0x03 /* RW CDB byte 1 & Total sectors per track */
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#define SBIC_CDB2THEAD 0x04 /* RW CDB byte 2 & Total number of heads */
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#define SBIC_CDB3TCYL1 0x05 /* RW CDB byte 3 & Total no. of cylinders MSB */
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#define SBIC_CDB4TCYL2 0x06 /* RW CDB byte 4 & Total no. of cylinders LSB */
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#define SBIC_CDB5LADR1 0x07 /* RW CDB byte 5 & Logical addr to translate */
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#define SBIC_CBD6LADR2 0x08 /* RW CDB byte 6 & Logical addr to translate */
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#define SBIC_CDB7LADR3 0x09 /* RW CDB byte 7 & Logical addr to translate */
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#define SBIC_CDB8LADR4 0x0A /* RW CDB byte 8 & Logical addr to translate */
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#define SBIC_CDB9SECT 0x0B /* RW CDB byte 9 & Translation sector result */
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#define SBIC_CDB10HEAD 0x0C /* RW CDB byte 10 & Translation head result */
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#define SBIC_CDB11CYL1 0x0D /* RW CDB byte 11 & Translation cyl result MSB*/
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#define SBIC_CDB12CYL2 0x0E /* RW CDB byte 12 & Translation cyl result LSB*/
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#define SBIC_TARGETLUN 0x0F /* RW TLV DOK 0 0 0 TL2 TL1 TL0 */
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#define SBIC_COMPHASE 0x10 /* RW Command Phase Register for multi-phase */
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#define SBIC_SYNCTX 0x11 /* RW 0 TP2 TP1 TP0 OF3 OF2 OF1 OF0 */
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#define SBIC_TXCOUNT1 0x12 /* RW Transfer count MSB */
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#define SBIC_TXCOUNT2 0x13 /* RW Transfer count */
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#define SBIC_TXCOUNT3 0x14 /* RW Transfer count LSB */
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#define SBIC_DESTID 0x15 /* RW SCC DPD 0 0 0 DI2 DI1 DI0 */
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#define SBIC_SOURCEID 0x16 /* RW ER ES DSP 0 SIV SI2 SI1 SI0 */
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#define SBIC_SCSISTAT 0x17 /* RO **Interrupt type*** **Int. qualifier** */
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#define SBIC_COMMAND 0x18 /* RW SBT *********Command code************* */
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#define SBIC_DATA 0x19 /* RW Access to data i/o FIFO for polled use */
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#define SBIC_ADDRREG 0x00
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#define SBIC_DATAREG 0x04
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#define SBIC_AUX_STATUS 0x00
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/*
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* My ID register, and/or CDB Size
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*/
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#define SBIC_ID_FS_8_10 0x00 /* Input clock is 8-10 MHz */
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/* 11 MHz is invalid */
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#define SBIC_ID_FS_12_15 0x40 /* Input clock is 12-15 MHz */
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#define SBIC_ID_FS_16_20 0x80 /* Input clock is 16-20 MHz */
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#define SBIC_ID_EHP 0x10 /* Enable host parity */
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#define SBIC_ID_EAF 0x08 /* Enable Advanced Features */
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#define SBIC_ID_MASK 0x07
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#define SBIC_ID_CBDSIZE_MASK 0x0f /* if unk SCSI cmd group */
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/*
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* Control register
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*/
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#define SBIC_CTL_DMA 0x80 /* Single byte dma */
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#define SBIC_CTL_DBA_DMA 0x40 /* direct buffer acces (bus master)*/
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#define SBIC_CTL_BURST_DMA 0x20 /* continuous mode (8237) */
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#define SBIC_CTL_NO_DMA 0x00 /* Programmed I/O */
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#define SBIC_CTL_HHP 0x10 /* Halt on host parity error */
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#define SBIC_CTL_EDI 0x08 /* Ending disconnect interrupt */
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#define SBIC_CTL_IDI 0x04 /* Intermediate disconnect interrupt*/
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#define SBIC_CTL_HA 0x02 /* Halt on ATN */
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#define SBIC_CTL_HSP 0x01 /* Halt on SCSI parity error */
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/*
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* Destination ID register
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*/
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#define SBIC_DID_DPD 0x40 /* Data Phase Direction */
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/*
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* Auxiliary Status Register
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*/
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#define SBIC_ASR_INT 0x80 /* Interrupt pending */
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#define SBIC_ASR_LCI 0x40 /* Last command ignored */
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#define SBIC_ASR_BSY 0x20 /* Busy, only cmd/data/asr readable */
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#define SBIC_ASR_CIP 0x10 /* Busy, cmd unavail also */
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#define SBIC_ASR_xxx 0x0c
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#define SBIC_ASR_PE 0x02 /* Parity error (even) */
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#define SBIC_ASR_DBR 0x01 /* Data Buffer Ready */
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/* DMAC constants */
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#define DMAC_Bits 0x01
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@ -278,33 +133,5 @@ temphi = dmac + 0x0218;/* RO T15 T14 T13 T12 T11 T10 T9 T8 */
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#define DMAC_REQREG 0x001C /* RW ---- ---- ---- ---- SRQ3 SRQ2 SRQ1 SRQ0 */
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#define DMAC_MASKREG 0x021C /* RW ---- ---- ---- ---- M3 M2 M1 M0 */
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#ifndef _LOCORE
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#define WriteSBIC(a, d) \
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WriteByte(sbic_base + SBIC_ADDRREG, a); \
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WriteByte(sbic_base + SBIC_DATAREG, d);
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/*
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#define ReadSBIC(a) \
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(WriteByte(sbic_base, a), ReadWord(sbic_base + 4) & 0xff)
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*/
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#define ReadSBIC(a) \
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ReadSBIC1(sbic_base, a)
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static inline int
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ReadSBIC1(sbic_base, a)
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u_int sbic_base;
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int a;
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{
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WriteByte(sbic_base + SBIC_ADDRREG, a);
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return(ReadByte(sbic_base + SBIC_DATAREG));
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}
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#define WriteDMAC(a, d) WriteByte(dmac_base + a, d)
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#define ReadDMAC(a) ReadByte(dmac_base + a)
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#endif
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#endif
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#endif /* _ASCREG_H_ */
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