Moved from ../dec/qbus/ubareg.h,v
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/* $NetBSD: ubareg.h,v 1.13 1999/05/27 16:04:27 ragge Exp $ */
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/*-
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* Copyright (c) 1982, 1986 The Regents of the University of California.
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* All rights reserved.
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* (c) UNIX System Laboratories, Inc.
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* All or some portions of this file are derived from material licensed
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* to the University of California by American Telephone and Telegraph
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* Co. or Unix System Laboratories, Inc. and are reproduced herein with
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* the permission of UNIX System Laboratories, Inc.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* 3. All advertising materials mentioning features or use of this software
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* must display the following acknowledgement:
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* This product includes software developed by the University of
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* California, Berkeley and its contributors.
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* 4. Neither the name of the University nor the names of its contributors
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* may be used to endorse or promote products derived from this software
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* without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*
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* @(#)ubareg.h 7.8 (Berkeley) 5/9/91
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*/
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/*
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* VAX UNIBUS adapter registers
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*/
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/*
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* "UNIBUS" adaptor types.
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* This code is used for both UNIBUSes and Q-buses
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* with different types of adaptors.
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* Definition of a type includes support code for that type.
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*/
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#if VAX780 || VAX8600
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#define DW780 1 /* has adaptor regs, sr: 780/785/8600 */
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#else
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#undef DW780
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#endif
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#if VAX750
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#define DW750 2 /* has adaptor regs, no sr: 750, 730 */
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#endif
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#if VAX730
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#define DW730 3 /* has adaptor regs, no sr: 750, 730 */
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#endif
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#if VAX630 || VAX650
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#define QBA 4 /* 22-bit Q-bus, no adaptor regs: uVAX II */
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#endif
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/*
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* Size of unibus memory address space in pages
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* (also number of map registers).
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* QBAPAGES should be 8192, but we don't need nearly that much
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* address space, and the return from the allocation routine
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* can accommodate at most 2047 (ubavar.h: UBA_MAXMR);
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* QBAPAGES must be at least UBAPAGES. Choose pragmatically.
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*
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* Is there ever any need to have QBAPAGES != UBAPAGES???
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* Wont work now anyway, QBAPAGES _must_ be .eq. UBAPAGES.
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*/
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#define UBAPAGES 496
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#define NUBMREG 496
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#define QBAPAGES 1024
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#define UBAIOADDR 0760000 /* start of I/O page */
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#define UBAIOPAGES 16
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#define UBAIOSIZE 8192 /* 8K I/O space */
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#ifndef _LOCORE
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#if 0
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/*
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* DW780/DW750 hardware registers
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*/
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struct uba_regs {
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int uba_cnfgr; /* configuration register */
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int uba_cr; /* control register */
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int uba_sr; /* status register */
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int uba_dcr; /* diagnostic control register */
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int uba_fmer; /* failed map entry register */
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int uba_fubar; /* failed UNIBUS address register */
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int pad1[2];
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int uba_brsvr[4];
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int uba_brrvr[4]; /* receive vector registers */
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int uba_dpr[16]; /* buffered data path register */
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int pad2[480];
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struct pte uba_map[UBAPAGES]; /* unibus map register */
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int pad3[UBAIOPAGES]; /* no maps for device address space */
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};
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#endif
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#endif
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#ifdef DW780
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/* uba_cnfgr */
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#define UBACNFGR_UBINIT 0x00040000 /* unibus init asserted */
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#define UBACNFGR_UBPDN 0x00020000 /* unibus power down */
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#define UBACNFGR_UBIC 0x00010000 /* unibus init complete */
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#define UBACNFGR_BITS \
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"\40\40PARFLT\37WSQFLT\36URDFLT\35ISQFLT\34MXTFLT\33XMTFLT\30ADPDN\27ADPUP\23UBINIT\22UBPDN\21UBIC"
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/* uba_cr */
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#define UBACR_MRD16 0x40000000 /* map reg disable bit 4 */
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#define UBACR_MRD8 0x20000000 /* map reg disable bit 3 */
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#define UBACR_MRD4 0x10000000 /* map reg disable bit 2 */
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#define UBACR_MRD2 0x08000000 /* map reg disable bit 1 */
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#define UBACR_MRD1 0x04000000 /* map reg disable bit 0 */
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#define UBACR_IFS 0x00000040 /* interrupt field switch */
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#define UBACR_BRIE 0x00000020 /* BR interrupt enable */
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#define UBACR_USEFIE 0x00000010 /* UNIBUS to SBI error field IE */
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#define UBACR_SUEFIE 0x00000008 /* SBI to UNIBUS error field IE */
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#define UBACR_CNFIE 0x00000004 /* configuration IE */
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#define UBACR_UPF 0x00000002 /* UNIBUS power fail */
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#define UBACR_ADINIT 0x00000001 /* adapter init */
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/* uba_sr */
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#define UBASR_BR7FULL 0x08000000 /* BR7 receive vector reg full */
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#define UBASR_BR6FULL 0x04000000 /* BR6 receive vector reg full */
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#define UBASR_BR5FULL 0x02000000 /* BR5 receive vector reg full */
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#define UBASR_BR4FULL 0x01000000 /* BR4 receive vector reg full */
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#define UBASR_RDTO 0x00000400 /* UNIBUS to SBI read data timeout */
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#define UBASR_RDS 0x00000200 /* read data substitute */
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#define UBASR_CRD 0x00000100 /* corrected read data */
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#define UBASR_CXTER 0x00000080 /* command transmit error */
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#define UBASR_CXTMO 0x00000040 /* command transmit timeout */
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#define UBASR_DPPE 0x00000020 /* data path parity error */
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#define UBASR_IVMR 0x00000010 /* invalid map register */
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#define UBASR_MRPF 0x00000008 /* map register parity failure */
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#define UBASR_LEB 0x00000004 /* lost error */
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#define UBASR_UBSTO 0x00000002 /* UNIBUS select timeout */
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#define UBASR_UBSSYNTO 0x00000001 /* UNIBUS slave sync timeout */
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#define UBASR_BITS \
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"\20\13RDTO\12RDS\11CRD\10CXTER\7CXTMO\6DPPE\5IVMR\4MRPF\3LEB\2UBSTO\1UBSSYNTO"
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/* uba_brrvr[] */
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#define UBABRRVR_AIRI 0x80000000 /* adapter interrupt request */
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#define UBABRRVR_DIV 0x0000ffff /* device interrupt vector field */
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#endif
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/* uba_dpr */
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#ifdef DW780
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#define UBADPR_BNE 0x80000000 /* buffer not empty - purge */
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#define UBADPR_BTE 0x40000000 /* buffer transfer error */
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#define UBADPR_DPF 0x20000000 /* DP function (RO) */
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#define UBADPR_BS 0x007f0000 /* buffer state field */
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#define UBADPR_BUBA 0x0000ffff /* buffered UNIBUS address */
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#endif
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#ifdef DW750
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#define UBADPR_ERROR 0x80000000 /* error occurred */
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#define UBADPR_NXM 0x40000000 /* nxm from memory */
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#define UBADPR_UCE 0x20000000 /* uncorrectable error */
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#define UBADPR_PURGE 0x00000001 /* purge bdp */
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#endif
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/* uba_mr[] */
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#define UBAMR_MRV 0x80000000 /* map register valid */
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#define UBAMR_BO 0x02000000 /* byte offset bit */
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#define UBAMR_DPDB 0x01e00000 /* data path designator field */
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#define UBAMR_SBIPFN 0x001fffff /* SBI page address field */
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#define UBAMR_DPSHIFT 21 /* shift to data path designator */
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/*
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* Number of unibus buffered data paths and possible uba's per cpu type.
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*/
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#define NBDP8600 15
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#define NBDP780 15
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#define NBDPBUA 5
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#define NBDP750 3
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#define NBDP730 0
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#define MAXNBDP 15
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/*
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* Symbolic BUS addresses for UBAs.
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*/
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#if VAX630 || VAX650
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#define QBAMAP 0x20088000
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#define QMEM 0x30000000
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#define QIOPAGE 0x20000000
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/*
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* Q-bus control registers
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*/
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#define QIPCR 0x1f40 /* from start of iopage */
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/* bits in QIPCR */
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#define Q_DBIRQ 0x0001 /* doorbell interrupt request */
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#define Q_LMEAE 0x0020 /* local mem external access enable */
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#define Q_DBIIE 0x0040 /* doorbell interrupt enable */
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#define Q_AUXHLT 0x0100 /* auxiliary processor halt */
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#define Q_DMAQPE 0x8000 /* Q22 bus address space parity error */
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#endif
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#if VAX730
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#define UMEM730 0xfc0000
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#endif
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#if VAX750
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#define UMEM750(i) (0xfc0000-(i)*0x40000)
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#endif
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#if VAX780
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#define UMEM780(i) (0x20100000+(i)*0x40000)
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#endif
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#if VAX8200 /* BEWARE, argument is node, not ubanum */
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#define UMEM8200(i) (0x20400000+(i)*0x40000)
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#endif
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#if VAX8600 || VAX780
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#define UMEMA8600(i) (0x20100000+(i)*0x40000)
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#define UMEMB8600(i) (0x22100000+(i)*0x40000)
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#endif
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/*
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* Macro to offset a UNIBUS device address, often expressed as
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* something like 0172520, by forcing it into the last 8K
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* of UNIBUS memory space.
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*/
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#define ubdevreg(addr) ((addr) & 017777)
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