Use bus_space(9) functions to access the controller registers.
Add probes to the attach routines before poking the chip to see where the registers are located.
This commit is contained in:
pk
parent
2d7f7ef7a6
commit
725c6438c1
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@ -1,4 +1,4 @@
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/* $NetBSD: fd.c,v 1.69 2000/01/11 12:59:45 pk Exp $ */
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/* $NetBSD: fd.c,v 1.70 2000/01/17 16:57:15 pk Exp $ */
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/*-
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* Copyright (c) 1993, 1994, 1995 Charles M. Hannum.
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@ -111,7 +111,7 @@ enum fdc_state {
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struct fdc_softc {
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struct device sc_dev; /* boilerplate */
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bus_space_tag_t sc_bustag;
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caddr_t sc_reg;
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struct fd_softc *sc_fd[4]; /* pointers to children */
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TAILQ_HEAD(drivehead, fd_softc) sc_drives;
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enum fdc_state sc_state;
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@ -123,6 +123,7 @@ struct fdc_softc {
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int sc_overruns; /* number of DMA overruns */
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int sc_cfg; /* current configuration */
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struct fdcio sc_io;
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#define sc_handle sc_io.fdcio_handle
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#define sc_reg_msr sc_io.fdcio_reg_msr
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#define sc_reg_fifo sc_io.fdcio_reg_fifo
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#define sc_reg_dor sc_io.fdcio_reg_dor
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@ -256,7 +257,15 @@ void fdfinish __P((struct fd_softc *fd, struct buf *bp));
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int fdformat __P((dev_t, struct ne7_fd_formb *, struct proc *));
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void fd_do_eject __P((struct fd_softc *));
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void fd_mountroot_hook __P((struct device *));
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static void fdconf __P((struct fdc_softc *));
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static int fdconf __P((struct fdc_softc *));
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static void establish_chip_type __P((
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struct fdc_softc *,
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bus_space_tag_t,
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bus_type_t,
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bus_addr_t,
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bus_size_t,
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bus_space_handle_t));
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#if PIL_FDSOFT == 4
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#define IE_FDSOFT IE_L4
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@ -334,6 +343,59 @@ fdcmatch_obio(parent, match, aux)
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NULL, NULL));
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}
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static void
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establish_chip_type(fdc, tag, type, addr, size, handle)
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struct fdc_softc *fdc;
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bus_space_tag_t tag;
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bus_type_t type;
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bus_addr_t addr;
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bus_size_t size;
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bus_space_handle_t handle;
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{
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u_int8_t v;
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/*
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* This hack from Chris Torek: apparently DOR really
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* addresses MSR/DRS on a 82072.
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* We used to rely on the VERSION command to tell the
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* difference (which did not work).
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*/
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/* First, check the size of the register bank */
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if (size < 8)
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/* It isn't a 82077 */
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return;
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/* Then probe the DOR register offset */
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if (bus_space_probe(tag, type, addr,
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1, /* probe size */
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FDREG77_DOR, /* offset */
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0, /* flags */
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NULL, NULL) == 0) {
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/* It isn't a 82077 */
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return;
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}
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v = bus_space_read_1(tag, handle, FDREG77_DOR);
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if (v == NE7_RQM) {
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/*
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* Value in DOR looks like it's really MSR
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*/
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bus_space_write_1(tag, handle, FDREG77_DOR, FDC_250KBPS);
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v = bus_space_read_1(tag, handle, FDREG77_DOR);
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if (v == NE7_RQM) {
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/*
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* The value in the DOR didn't stick;
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* it isn't a 82077
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*/
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return;
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}
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}
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fdc->sc_flags |= FDC_82077;
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}
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/*
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* Arguments passed between fdcattach and fdprobe.
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*/
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@ -361,14 +423,14 @@ fdprint(aux, fdc)
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return (QUIET);
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}
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static void
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static int
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fdconf(fdc)
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struct fdc_softc *fdc;
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{
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int vroom;
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if (out_fdc(fdc, NE7CMD_DUMPREG) || fdcresult(fdc) != 10)
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return;
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return (-1);
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/*
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* dumpreg[7] seems to be a motor-off timeout; set it to whatever
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@ -382,7 +444,27 @@ fdconf(fdc)
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out_fdc(fdc, vroom);
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out_fdc(fdc, fdc->sc_cfg);
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out_fdc(fdc, 0); /* PRETRK */
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/* No result phase */
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/* No result phase for the NE7CMD_CFG command */
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if ((fdc->sc_flags & FDC_82077) != 0) {
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/* Lock configuration across soft resets. */
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out_fdc(fdc, NE7CMD_LOCK | CFG_LOCK);
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if (fdcresult(fdc) != 1) {
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#ifdef DEBUG
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printf("fdconf: CFGLOCK failed");
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#endif
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return (-1);
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}
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}
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return (0);
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#if 0
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if (out_fdc(fdc, NE7CMD_VERSION) == 0 &&
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fdcresult(fdc) == 1 && fdc->sc_status[0] == 0x90) {
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if (fdc_debug)
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printf("[version cmd]");
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}
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#endif
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}
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/*
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@ -401,9 +483,8 @@ fdcattach_mainbus(parent, self, aux)
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fdc->sc_bustag = ma->ma_bustag;
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if (ma->ma_promvaddr != 0)
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fdc->sc_reg = (caddr_t)ma->ma_promvaddr;
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fdc->sc_handle = (bus_space_handle_t)ma->ma_promvaddr;
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else {
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bus_space_handle_t bh;
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if (bus_space_map2(
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ma->ma_bustag,
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ma->ma_iospace,
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@ -411,13 +492,19 @@ fdcattach_mainbus(parent, self, aux)
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ma->ma_size,
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BUS_SPACE_MAP_LINEAR,
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0,
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&bh) != 0) {
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&fdc->sc_handle) != 0) {
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printf("%s: cannot map registers\n", self->dv_xname);
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return;
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}
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fdc->sc_reg = (caddr_t)bh;
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}
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establish_chip_type(fdc,
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ma->ma_bustag,
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ma->ma_iospace,
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ma->ma_paddr,
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ma->ma_size,
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fdc->sc_handle);
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fdcattach(fdc, ma->ma_pri);
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}
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@ -433,23 +520,27 @@ fdcattach_obio(parent, self, aux)
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fdc->sc_bustag = sa->sa_bustag;
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if (sa->sa_npromvaddrs != 0)
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fdc->sc_reg = (caddr_t)sa->sa_promvaddrs[0];
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fdc->sc_handle = (bus_space_handle_t)sa->sa_promvaddrs[0];
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else {
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bus_space_handle_t bh;
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if (sbus_bus_map(sa->sa_bustag, sa->sa_slot,
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sa->sa_offset,
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sa->sa_size,
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BUS_SPACE_MAP_LINEAR,
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0,
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&bh) != 0) {
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&fdc->sc_handle) != 0) {
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printf("%s: cannot map control registers\n",
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self->dv_xname);
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return;
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}
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fdc->sc_reg = (caddr_t)bh;
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}
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establish_chip_type(fdc,
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sa->sa_bustag,
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sa->sa_slot,
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sa->sa_offset,
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sa->sa_size,
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fdc->sc_handle);
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if (sa->sa_nintr != 0)
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fdcattach(fdc, sa->sa_pri);
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}
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@ -467,6 +558,30 @@ fdcattach(fdc, pri)
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fdc->sc_flags |= FDC_EIS;
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TAILQ_INIT(&fdc->sc_drives);
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if ((fdc->sc_flags & FDC_82077) != 0) {
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fdc->sc_reg_msr = FDREG77_MSR;
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fdc->sc_reg_fifo = FDREG77_FIFO;
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fdc->sc_reg_dor = FDREG77_DOR;
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code = '7';
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} else {
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fdc->sc_reg_msr = FDREG72_MSR;
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fdc->sc_reg_fifo = FDREG72_FIFO;
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fdc->sc_reg_dor = 0;
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code = '2';
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}
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printf(" softpri %d: chip 8207%c\n", PIL_FDSOFT, code);
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/*
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* Configure controller; enable FIFO, Implied seek, no POLL mode?.
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* Note: CFG_EFIFO is active-low, initial threshold value: 8
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*/
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fdc->sc_cfg = CFG_EIS|/*CFG_EFIFO|*/CFG_POLL|(8 & CFG_THRHLD_MASK);
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if (fdconf(fdc) != 0) {
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printf("%s: no drives attached\n", fdc->sc_dev.dv_xname);
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return;
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}
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#ifdef FDC_C_HANDLER
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(void)bus_intr_establish(fdc->sc_bustag, pri, 0,
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fdchwintr, fdc);
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@ -480,57 +595,8 @@ fdcattach(fdc, pri)
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BUS_INTR_ESTABLISH_SOFTINTR,
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fdcswintr, fdc);
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/* Assume a 82077 */
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fdc->sc_reg_msr = &((struct fdreg_77 *)fdc->sc_reg)->fd_msr;
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fdc->sc_reg_fifo = &((struct fdreg_77 *)fdc->sc_reg)->fd_fifo;
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fdc->sc_reg_dor = &((struct fdreg_77 *)fdc->sc_reg)->fd_dor;
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code = '7';
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if (*fdc->sc_reg_dor == NE7_RQM) {
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/*
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* This hack from Chris Torek: apparently DOR really
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* addresses MSR/DRS on a 82072.
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* We used to rely on the VERSION command to tell the
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* difference (which did not work).
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*/
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*fdc->sc_reg_dor = FDC_250KBPS;
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if (*fdc->sc_reg_dor == NE7_RQM)
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code = '2';
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}
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if (code == '7') {
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fdc->sc_flags |= FDC_82077;
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} else {
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fdc->sc_reg_msr = &((struct fdreg_72 *)fdc->sc_reg)->fd_msr;
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fdc->sc_reg_fifo = &((struct fdreg_72 *)fdc->sc_reg)->fd_fifo;
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fdc->sc_reg_dor = 0;
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}
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#ifdef FD_DEBUG
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if (out_fdc(fdc, NE7CMD_VERSION) == 0 &&
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fdcresult(fdc) == 1 && fdc->sc_status[0] == 0x90) {
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if (fdc_debug)
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printf("[version cmd]");
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}
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#endif
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/*
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* Configure controller; enable FIFO, Implied seek, no POLL mode?.
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* Note: CFG_EFIFO is active-low, initial threshold value: 8
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*/
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fdc->sc_cfg = CFG_EIS|/*CFG_EFIFO|*/CFG_POLL|(8 & CFG_THRHLD_MASK);
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fdconf(fdc);
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if (fdc->sc_flags & FDC_82077) {
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/* Lock configuration across soft resets. */
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out_fdc(fdc, NE7CMD_LOCK | CFG_LOCK);
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if (fdcresult(fdc) != 1)
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printf(" CFGLOCK: unexpected response");
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}
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evcnt_attach(&fdc->sc_dev, "intr", &fdc->sc_intrcnt);
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printf(" softpri %d: chip 8207%c\n", PIL_FDSOFT, code);
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/* physical limit: four drives per controller. */
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for (fa.fa_drive = 0; fa.fa_drive < 4; fa.fa_drive++) {
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fa.fa_deftype = NULL; /* unknown */
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@ -546,6 +612,8 @@ fdmatch(parent, match, aux)
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void *aux;
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{
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struct fdc_softc *fdc = (void *)parent;
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bus_space_tag_t t = fdc->sc_bustag;
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bus_space_handle_t h = fdc->sc_handle;
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struct fdc_attach_args *fa = aux;
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int drive = fa->fa_drive;
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int n, ok;
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@ -556,7 +624,8 @@ fdmatch(parent, match, aux)
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if (fdc->sc_flags & FDC_82077) {
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/* select drive and turn on motor */
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*fdc->sc_reg_dor = drive | FDO_FRST | FDO_MOEN(drive);
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bus_space_write_1(t, h, fdc->sc_reg_dor,
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drive | FDO_FRST | FDO_MOEN(drive));
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/* wait for motor to spin up */
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delay(250000);
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} else {
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@ -565,10 +634,14 @@ fdmatch(parent, match, aux)
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fdc->sc_nstat = 0;
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out_fdc(fdc, NE7CMD_RECAL);
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out_fdc(fdc, drive);
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/* wait for recalibrate */
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/* Wait for recalibration to complete */
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for (n = 0; n < 10000; n++) {
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u_int8_t v;
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delay(1000);
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if ((*fdc->sc_reg_msr & (NE7_RQM|NE7_DIO|NE7_CB)) == NE7_RQM) {
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v = bus_space_read_1(t, h, fdc->sc_reg_msr);
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if ((v & (NE7_RQM|NE7_DIO|NE7_CB)) == NE7_RQM) {
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/* wait a bit longer till device *really* is ready */
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delay(100000);
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if (out_fdc(fdc, NE7CMD_SENSEI))
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@ -598,7 +671,7 @@ fdmatch(parent, match, aux)
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/* turn off motor */
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if (fdc->sc_flags & FDC_82077) {
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/* deselect drive and turn motor off */
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*fdc->sc_reg_dor = FDO_FRST | FDO_DS;
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bus_space_write_1(t, h, fdc->sc_reg_dor, FDO_FRST | FDO_DS);
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} else {
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auxregbisc(0, AUXIO4C_FDS);
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}
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@ -797,16 +870,21 @@ void
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fdc_reset(fdc)
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struct fdc_softc *fdc;
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{
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bus_space_tag_t t = fdc->sc_bustag;
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bus_space_handle_t h = fdc->sc_handle;
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if (fdc->sc_flags & FDC_82077) {
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*fdc->sc_reg_dor = FDO_FDMAEN | FDO_MOEN(0);
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bus_space_write_1(t, h, fdc->sc_reg_dor,
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FDO_FDMAEN | FDO_MOEN(0));
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}
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*fdc->sc_reg_drs = DRS_RESET;
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bus_space_write_1(t, h, fdc->sc_reg_drs, DRS_RESET);
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delay(10);
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*fdc->sc_reg_drs = 0;
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bus_space_write_1(t, h, fdc->sc_reg_drs, 0);
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if (fdc->sc_flags & FDC_82077) {
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*fdc->sc_reg_dor = FDO_FRST | FDO_FDMAEN | FDO_DS;
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bus_space_write_1(t, h, fdc->sc_reg_dor,
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FDO_FRST | FDO_FDMAEN | FDO_DS);
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}
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#ifdef FD_DEBUG
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if (fdc_debug)
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@ -830,7 +908,8 @@ fd_set_motor(fdc)
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for (n = 0; n < 4; n++)
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if ((fd = fdc->sc_fd[n]) && (fd->sc_flags & FD_MOTOR))
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status |= FDO_MOEN(n);
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*fdc->sc_reg_dor = status;
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bus_space_write_1(fdc->sc_bustag, fdc->sc_handle,
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fdc->sc_reg_dor, status);
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} else {
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int on = 0;
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@ -877,20 +956,23 @@ int
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fdcresult(fdc)
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struct fdc_softc *fdc;
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{
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u_char i;
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bus_space_tag_t t = fdc->sc_bustag;
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bus_space_handle_t h = fdc->sc_handle;
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int j = 100000,
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n = 0;
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for (; j; j--) {
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i = *fdc->sc_reg_msr & (NE7_DIO | NE7_RQM | NE7_CB);
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if (i == NE7_RQM)
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u_int8_t v = bus_space_read_1(t, h, fdc->sc_reg_msr);
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v &= (NE7_DIO | NE7_RQM | NE7_CB);
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if (v == NE7_RQM)
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return (fdc->sc_nstat = n);
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if (i == (NE7_DIO | NE7_RQM | NE7_CB)) {
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if (v == (NE7_DIO | NE7_RQM | NE7_CB)) {
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if (n >= sizeof(fdc->sc_status)) {
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log(LOG_ERR, "fdcresult: overrun\n");
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return (-1);
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}
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fdc->sc_status[n++] = *fdc->sc_reg_fifo;
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fdc->sc_status[n++] =
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bus_space_read_1(t, h, fdc->sc_reg_fifo);
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} else
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delay(10);
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}
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@ -901,16 +983,22 @@ fdcresult(fdc)
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int
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out_fdc(fdc, x)
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struct fdc_softc *fdc;
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u_char x;
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u_int8_t x;
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{
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int i = 100000;
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bus_space_tag_t t = fdc->sc_bustag;
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bus_space_handle_t h = fdc->sc_handle;
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int i;
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|
||||
while (((*fdc->sc_reg_msr & (NE7_DIO|NE7_RQM)) != NE7_RQM) && i-- > 0)
|
||||
for (i = 100000; i-- > 0;) {
|
||||
u_int8_t v = bus_space_read_1(t, h, fdc->sc_reg_msr);
|
||||
if ((v & (NE7_DIO|NE7_RQM)) == NE7_RQM)
|
||||
break;
|
||||
delay(1);
|
||||
}
|
||||
if (i <= 0)
|
||||
return (-1);
|
||||
|
||||
*fdc->sc_reg_fifo = x;
|
||||
bus_space_write_1(t, h, fdc->sc_reg_fifo, x);
|
||||
return (0);
|
||||
}
|
||||
|
||||
|
|
@ -1124,6 +1212,8 @@ fdchwintr(arg)
|
|||
void *arg;
|
||||
{
|
||||
struct fdc_softc *fdc = arg;
|
||||
bus_space_tag_t t = fdc->sc_bustag;
|
||||
bus_space_handle_t h = fdc->sc_handle;
|
||||
|
||||
switch (fdc->sc_istate) {
|
||||
case ISTATE_IDLE:
|
||||
|
|
@ -1148,9 +1238,9 @@ fdchwintr(arg)
|
|||
}
|
||||
|
||||
for (;;) {
|
||||
register int msr;
|
||||
u_int8_t msr;
|
||||
|
||||
msr = *fdc->sc_reg_msr;
|
||||
msr = bus_space_read_1(t, h, fdc->sc_reg_msr);
|
||||
|
||||
if ((msr & NE7_RQM) == 0)
|
||||
break;
|
||||
|
|
@ -1164,9 +1254,12 @@ fdchwintr(arg)
|
|||
}
|
||||
|
||||
if (msr & NE7_DIO) {
|
||||
*fdc->sc_data++ = *fdc->sc_reg_fifo;
|
||||
*fdc->sc_data++ =
|
||||
bus_space_read_1(t, h, fdc->sc_reg_fifo);
|
||||
} else {
|
||||
*fdc->sc_reg_fifo = *fdc->sc_data++;
|
||||
bus_space_write_1(t, h, fdc->sc_reg_fifo,
|
||||
*fdc->sc_data);
|
||||
fdc->sc_data++;
|
||||
}
|
||||
if (--fdc->sc_tc == 0) {
|
||||
fdc->sc_istate = ISTATE_DONE;
|
||||
|
|
@ -1344,7 +1437,8 @@ loop:
|
|||
fdc->sc_data = bp->b_data + fd->sc_skip;
|
||||
fdc->sc_tc = fd->sc_nbytes;
|
||||
|
||||
*fdc->sc_reg_drs = type->rate;
|
||||
bus_space_write_1(fdc->sc_bustag, fdc->sc_handle,
|
||||
fdc->sc_reg_drs, type->rate);
|
||||
#ifdef FD_DEBUG
|
||||
if (fdc_debug > 1)
|
||||
printf("fdcintr: %s drive %d track %d head %d sec %d nblks %d\n",
|
||||
|
|
@ -1646,14 +1740,23 @@ fdioctl(dev, cmd, addr, flag, p)
|
|||
int flag;
|
||||
struct proc *p;
|
||||
{
|
||||
struct fd_softc *fd = fd_cd.cd_devs[FDUNIT(dev)];
|
||||
struct fd_softc *fd;
|
||||
struct fdc_softc *fdc;
|
||||
struct fdformat_parms *form_parms;
|
||||
struct fdformat_cmd *form_cmd;
|
||||
struct ne7_fd_formb fd_formb;
|
||||
int il[FD_MAX_NSEC + 1];
|
||||
int unit;
|
||||
int i, j;
|
||||
int error;
|
||||
|
||||
unit = FDUNIT(dev);
|
||||
if (unit >= fd_cd.cd_ndevs)
|
||||
return (ENXIO);
|
||||
|
||||
fd = fd_cd.cd_devs[FDUNIT(dev)];
|
||||
fdc = (struct fdc_softc *)fd->sc_dv.dv_parent;
|
||||
|
||||
switch (cmd) {
|
||||
case DIOCGDINFO:
|
||||
*(struct disklabel *)addr = *(fd->sc_dk.dk_label);
|
||||
|
|
@ -1825,38 +1928,26 @@ fdioctl(dev, cmd, addr, flag, p)
|
|||
|
||||
#ifdef DEBUG
|
||||
case _IO('f', 100):
|
||||
{
|
||||
int i;
|
||||
struct fdc_softc *fdc = (struct fdc_softc *)
|
||||
fd->sc_dv.dv_parent;
|
||||
|
||||
out_fdc(fdc, NE7CMD_DUMPREG);
|
||||
fdcresult(fdc);
|
||||
printf("dumpreg(%d regs): <", fdc->sc_nstat);
|
||||
printf("fdc: dumpreg(%d regs): <", fdc->sc_nstat);
|
||||
for (i = 0; i < fdc->sc_nstat; i++)
|
||||
printf(" 0x%x", fdc->sc_status[i]);
|
||||
printf(">\n");
|
||||
}
|
||||
return (0);
|
||||
|
||||
return (0);
|
||||
case _IOW('f', 101, int):
|
||||
((struct fdc_softc *)fd->sc_dv.dv_parent)->sc_cfg &=
|
||||
~CFG_THRHLD_MASK;
|
||||
((struct fdc_softc *)fd->sc_dv.dv_parent)->sc_cfg |=
|
||||
(*(int *)addr & CFG_THRHLD_MASK);
|
||||
fdconf((struct fdc_softc *) fd->sc_dv.dv_parent);
|
||||
fdc->sc_cfg &= ~CFG_THRHLD_MASK;
|
||||
fdc->sc_cfg |= (*(int *)addr & CFG_THRHLD_MASK);
|
||||
fdconf(fdc);
|
||||
return (0);
|
||||
|
||||
case _IO('f', 102):
|
||||
{
|
||||
int i;
|
||||
struct fdc_softc *fdc = (struct fdc_softc *)
|
||||
fd->sc_dv.dv_parent;
|
||||
out_fdc(fdc, NE7CMD_SENSEI);
|
||||
fdcresult(fdc);
|
||||
printf("sensei(%d regs): <", fdc->sc_nstat);
|
||||
printf("fdc: sensei(%d regs): <", fdc->sc_nstat);
|
||||
for (i=0; i< fdc->sc_nstat; i++)
|
||||
printf(" 0x%x", fdc->sc_status[i]);
|
||||
}
|
||||
printf(">\n");
|
||||
return (0);
|
||||
#endif
|
||||
|
|
@ -2008,10 +2099,13 @@ fd_do_eject(fd)
|
|||
return;
|
||||
}
|
||||
if (CPU_ISSUN4M && (fdc->sc_flags & FDC_82077)) {
|
||||
int dor = FDO_FRST | FDO_FDMAEN | FDO_MOEN(0);
|
||||
*fdc->sc_reg_dor = dor | FDO_EJ;
|
||||
bus_space_tag_t t = fdc->sc_bustag;
|
||||
bus_space_handle_t h = fdc->sc_handle;
|
||||
u_int8_t dor = FDO_FRST | FDO_FDMAEN | FDO_MOEN(0);
|
||||
|
||||
bus_space_write_1(t, h, fdc->sc_reg_dor, dor | FDO_EJ);
|
||||
delay(10);
|
||||
*fdc->sc_reg_dor = FDO_FRST | FDO_DS;
|
||||
bus_space_write_1(t, h, fdc->sc_reg_dor, FDO_FRST | FDO_DS);
|
||||
return;
|
||||
}
|
||||
}
|
||||
|
|
|
|||
|
|
@ -1,4 +1,4 @@
|
|||
/* $NetBSD: fdreg.h,v 1.6 1997/05/02 13:03:44 pk Exp $ */
|
||||
/* $NetBSD: fdreg.h,v 1.7 2000/01/17 16:57:15 pk Exp $ */
|
||||
|
||||
/*-
|
||||
* Copyright (c) 1991 The Regents of the University of California.
|
||||
|
|
@ -42,33 +42,26 @@
|
|||
/* uses NEC765 controller */
|
||||
#include <dev/ic/nec765reg.h>
|
||||
|
||||
#ifndef _LOCORE
|
||||
struct fdreg_77 {
|
||||
u_int8_t fd_statusA;
|
||||
u_int8_t fd_statusB;
|
||||
u_int8_t fd_dor; /* Digital Output Register (R/W) */
|
||||
u_int8_t fd_tdr; /* Tape Control Register (R/W) */
|
||||
u_int8_t fd_msr; /* Main Status Register (R) */
|
||||
#define fd_drs fd_msr /* Data Rate Select Register (W) */
|
||||
u_int8_t fd_fifo; /* Data (FIFO) register (R/W) */
|
||||
u_int8_t fd_reserved;
|
||||
u_int8_t fd_dir; /* Digital Input Register (R) */
|
||||
#define fd_ccr fd_dir /* Configuration Control (W) */
|
||||
};
|
||||
/*
|
||||
* Register offsets for the 82077 controller.
|
||||
*/
|
||||
#define FDREG77_STATUSA 0
|
||||
#define FDREG77_STATUSB 1
|
||||
#define FDREG77_DOR 2 /* Digital Output Register (R/W) */
|
||||
#define FDREG77_TDR 3 /* Tape Control Register (R/W) */
|
||||
#define FDREG77_MSR 4 /* Main Status Register (R) */
|
||||
#define FDREG77_DRS 4 /* Data Rate Select Register (W) */
|
||||
#define FDREG77_FIFO 5 /* Data (FIFO) register (R/W) */
|
||||
#define FDREG77_DIR 7 /* Digital Input Register (R) */
|
||||
#define FDREG77_CCR 7 /* Configuration Control (W) */
|
||||
|
||||
struct fdreg_72 {
|
||||
u_int8_t fd_msr; /* Main Status Register (R) */
|
||||
#if already_a_define
|
||||
#define fd_drs fd_msr /* Data Rate Select Register (W) */
|
||||
#endif
|
||||
u_int8_t fd_fifo; /* Data (FIFO) register (R/W) */
|
||||
};
|
||||
/*
|
||||
* Register offsets for the 82077 controller.
|
||||
*/
|
||||
#define FDREG72_MSR 0 /* Main Status Register (R) */
|
||||
#define FDREG72_DRS 0 /* Data Rate Select Register (W) */
|
||||
#define FDREG72_FIFO 1 /* Data (FIFO) register (R/W) */
|
||||
|
||||
union fdreg {
|
||||
struct fdreg_72 fun72;
|
||||
struct fdreg_77 fun77;
|
||||
};
|
||||
#endif
|
||||
|
||||
/* Data Select Register bits */
|
||||
#define DRS_RESET 0x80
|
||||
|
|
|
|||
|
|
@ -1,4 +1,4 @@
|
|||
/* $NetBSD: fdvar.h,v 1.8 1998/09/05 15:42:42 pk Exp $ */
|
||||
/* $NetBSD: fdvar.h,v 1.9 2000/01/17 16:57:15 pk Exp $ */
|
||||
|
||||
/*-
|
||||
* Copyright (c) 1998 The NetBSD Foundation, Inc.
|
||||
|
|
@ -43,13 +43,14 @@
|
|||
|
||||
#ifndef _LOCORE
|
||||
struct fdcio {
|
||||
bus_space_handle_t fdcio_handle;
|
||||
/*
|
||||
* 82072 (sun4c) and 82077 (sun4m) controllers have different
|
||||
* register layout; so we cache some here.
|
||||
* register layout; so we cache offsets to the registers here.
|
||||
*/
|
||||
volatile u_int8_t *fdcio_reg_msr;
|
||||
volatile u_int8_t *fdcio_reg_fifo;
|
||||
volatile u_int8_t *fdcio_reg_dor; /* 82077 only */
|
||||
u_int fdcio_reg_msr;
|
||||
u_int fdcio_reg_fifo;
|
||||
u_int fdcio_reg_dor; /* 82077 only */
|
||||
|
||||
/*
|
||||
* Interrupt state.
|
||||
|
|
|
|||
Loading…
Reference in New Issue