add support for the Intel 82557/82558 fast ethernet chip
This commit is contained in:
drochner
parent
737886c364
commit
6f71e420f3
@ -1,4 +1,4 @@
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## $NetBSD: Makefile.inc,v 1.2 1998/02/16 11:21:59 drochner Exp $
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## $NetBSD: Makefile.inc,v 1.3 1998/12/12 15:47:05 drochner Exp $
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SRCS += netif_small.c
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.if (${USE_NETIF} == "3c509")
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@ -16,3 +16,6 @@ SRCS += pcnet_pci.c am7990.c
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.if (${USE_NETIF} == "pcnet_isapnp")
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SRCS += pcnet_isapnp.c am7990.c
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.endif
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.if (${USE_NETIF} == "i82557")
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SRCS += i82557.c
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.endif
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497
sys/arch/i386/stand/lib/netif/i82557.c
Normal file
497
sys/arch/i386/stand/lib/netif/i82557.c
Normal file
@ -0,0 +1,497 @@
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/* $NetBSD: i82557.c,v 1.1 1998/12/12 15:47:05 drochner Exp $ */
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/*
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* Copyright (c) 1998
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* Matthias Drochner. All rights reserved.
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* Copyright (c) 1995, David Greenman
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice unmodified, this list of conditions, and the following
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* disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*/
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#include <sys/types.h>
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#include <machine/pio.h>
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typedef int bus_dmamap_t; /* XXX */
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#include <dev/pci/if_fxpreg.h>
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#include <lib/libsa/stand.h>
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#include <libi386.h>
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#include <pcivar.h>
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#if defined(_STANDALONE) && !defined(SUPPORT_NO_NETBSD)
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#include <lib/libkern/libkern.h>
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#include <bootinfo.h>
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#endif
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#include "etherdrv.h"
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#define RECVBUF_SIZE 1600 /* struct fxp_rfa + packet */
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#ifdef _STANDALONE
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static pcihdl_t mytag;
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static char recvbuf[RECVBUF_SIZE];
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#define RECVBUF_PHYS vtophys(recvbuf)
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#define RECVBUF_VIRT ((void *)recvbuf)
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static union _sndbuf {
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struct fxp_cb_config cbp;
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struct fxp_cb_ias cb_ias;
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struct fxp_cb_tx txp;
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} sndbuf;
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#define SNDBUF_PHYS vtophys(&sndbuf)
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#define SNDBUF_VIRT ((void *)&sndbuf)
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#else /* !standalone, userspace testing environment */
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#define PCI_MODE1_ENABLE 0x80000000UL
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static pcihdl_t mytag = PCI_MODE1_ENABLE | (PCIDEVNO << 11);
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extern caddr_t mapmem __P((int, int));
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void *dmamem; /* virtual */
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#define RECVBUF_PHYS DMABASE
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#define RECVBUF_VIRT dmamem
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#define SNDBUF_PHYS (DMABASE + RECVBUF_SIZE)
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#define SNDBUF_VIRT ((void *)(((char *)dmamem) + RECVBUF_SIZE))
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#endif /* _STANDALONE */
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static void fxp_read_eeprom __P((u_int16_t *, int, int));
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static inline void fxp_scb_wait __P((void));
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#ifdef DEBUG
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static void fxp_checkintr __P((char *));
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#else
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#define fxp_checkintr(x)
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#endif
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static void fxp_startreceiver __P((void));
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/*
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* Template for default configuration parameters.
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* See struct fxp_cb_config for the bit definitions.
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*/
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static u_int8_t fxp_cb_config_template[] = {
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0x0, 0x0, /* cb_status */
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0x80, 0x2, /* cb_command */
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0xff, 0xff, 0xff, 0xff, /* link_addr */
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0x16, /* 0 */
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0x8, /* 1 */
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0x0, /* 2 */
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0x0, /* 3 */
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0x0, /* 4 */
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0x80, /* 5 */
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0xb2, /* 6 */
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0x3, /* 7 */
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0x1, /* 8 */
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0x0, /* 9 */
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0x26, /* 10 */
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0x0, /* 11 */
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0x60, /* 12 */
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0x0, /* 13 */
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0xf2, /* 14 */
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0x48, /* 15 */
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0x0, /* 16 */
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0x40, /* 17 */
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0xf3, /* 18 */
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0x0, /* 19 */
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0x3f, /* 20 */
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0x5 /* 21 */
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};
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static int tx_threshold = 64; /* x8, max 192 */
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#define CSR_READ_1(reg) inb(iobase + (reg))
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#define CSR_READ_2(reg) inw(iobase + (reg))
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#define CSR_WRITE_1(reg, val) outb(iobase + (reg), val)
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#define CSR_WRITE_2(reg, val) outw(iobase + (reg), val)
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#define CSR_WRITE_4(reg, val) outl(iobase + (reg), val)
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#define DELAY(n) delay(n)
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static int iobase;
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#if defined(_STANDALONE) && !defined(SUPPORT_NO_NETBSD)
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static struct btinfo_netif bi_netif;
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#endif
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/*
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* Wait for the previous command to be accepted (but not necessarily
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* completed).
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*/
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static inline void
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fxp_scb_wait()
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{
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int i = 10000;
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while (CSR_READ_1(FXP_CSR_SCB_COMMAND) && --i)
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DELAY(1);
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if (i == 0)
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printf("fxp: WARNING: SCB timed out!\n");
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}
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#ifdef DEBUG
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static void
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fxp_checkintr(msg)
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char *msg;
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{
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u_int8_t statack;
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int i = 10000;
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do {
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statack = CSR_READ_1(FXP_CSR_SCB_STATACK);
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} while ((statack == 0) && (--i > 0));
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if (statack != 0) {
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CSR_WRITE_1(FXP_CSR_SCB_STATACK, statack);
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printf("%s: ack'd irq %x, i=%d\n", msg, statack, i);
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}
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}
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#endif
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int
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EtherInit(myadr)
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char *myadr;
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{
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#ifndef _STANDALONE
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u_int32_t id;
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#endif
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volatile struct fxp_cb_config *cbp;
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volatile struct fxp_cb_ias *cb_ias;
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int i;
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if (pcicheck()) {
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printf("pcicheck failed\n");
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return (0);
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}
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#ifdef _STANDALONE
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if (pcifinddev(0x8086, 0x1229, &mytag)) {
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printf("no fxp\n");
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return (0);
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}
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#else
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pcicfgread(&mytag, 0, &id);
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if (id != 0x12298086) {
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printf("no fxp\n");
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return (0);
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}
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#endif
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pcicfgread(&mytag, FXP_PCI_IOBA, &iobase);
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iobase &= ~3;
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#ifndef _STANDALONE
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dmamem = mapmem(DMABASE, DMASIZE);
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if (!dmamem)
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return (0);
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#endif
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fxp_read_eeprom((void *)myadr, 0, 3);
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/*
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* Initialize base of CBL and RFA memory. Loading with zero
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* sets it up for regular linear addressing.
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*/
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CSR_WRITE_4(FXP_CSR_SCB_GENERAL, 0);
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CSR_WRITE_1(FXP_CSR_SCB_COMMAND, FXP_SCB_COMMAND_CU_BASE);
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fxp_scb_wait();
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CSR_WRITE_1(FXP_CSR_SCB_COMMAND, FXP_SCB_COMMAND_RU_BASE);
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cbp = SNDBUF_VIRT;
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/*
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* This bcopy is kind of disgusting, but there are a bunch of must be
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* zero and must be one bits in this structure and this is the easiest
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* way to initialize them all to proper values.
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*/
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bcopy(fxp_cb_config_template, (void *)&cbp->cb_status,
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sizeof(fxp_cb_config_template));
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#define prm 0
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#define phy_10Mbps_only 0
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#define all_mcasts 0
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cbp->cb_status = 0;
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cbp->cb_command = FXP_CB_COMMAND_CONFIG | FXP_CB_COMMAND_EL;
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cbp->link_addr = -1; /* (no) next command */
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cbp->byte_count = 22; /* (22) bytes to config */
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cbp->rx_fifo_limit = 8; /* rx fifo threshold (32 bytes) */
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cbp->tx_fifo_limit = 0; /* tx fifo threshold (0 bytes) */
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cbp->adaptive_ifs = 0; /* (no) adaptive interframe spacing */
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cbp->rx_dma_bytecount = 0; /* (no) rx DMA max */
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cbp->tx_dma_bytecount = 0; /* (no) tx DMA max */
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cbp->dma_bce = 0; /* (disable) dma max counters */
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cbp->late_scb = 0; /* (don't) defer SCB update */
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cbp->tno_int = 0; /* (disable) tx not okay interrupt */
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cbp->ci_int = 0; /* interrupt on CU not active */
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cbp->save_bf = prm; /* save bad frames */
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cbp->disc_short_rx = !prm; /* discard short packets */
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cbp->underrun_retry = 1; /* retry mode (1) on DMA underrun */
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cbp->mediatype = !phy_10Mbps_only; /* interface mode */
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cbp->nsai = 1; /* (don't) disable source addr insert */
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cbp->preamble_length = 2; /* (7 byte) preamble */
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cbp->loopback = 0; /* (don't) loopback */
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cbp->linear_priority = 0; /* (normal CSMA/CD operation) */
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cbp->linear_pri_mode = 0; /* (wait after xmit only) */
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cbp->interfrm_spacing = 6; /* (96 bits of) interframe spacing */
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cbp->promiscuous = prm; /* promiscuous mode */
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cbp->bcast_disable = 0; /* (don't) disable broadcasts */
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cbp->crscdt = 0; /* (CRS only) */
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cbp->stripping = !prm; /* truncate rx packet to byte count */
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cbp->padding = 1; /* (do) pad short tx packets */
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cbp->rcv_crc_xfer = 0; /* (don't) xfer CRC to host */
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cbp->force_fdx = 0; /* (don't) force full duplex */
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cbp->fdx_pin_en = 1; /* (enable) FDX# pin */
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cbp->multi_ia = 0; /* (don't) accept multiple IAs */
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cbp->mc_all = all_mcasts;/* accept all multicasts */
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#undef prm
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#undef phy_10Mbps_only
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#undef all_mcasts
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/*
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* Start the config command/DMA.
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*/
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fxp_scb_wait();
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CSR_WRITE_4(FXP_CSR_SCB_GENERAL, SNDBUF_PHYS + 12); /* XXX */
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CSR_WRITE_1(FXP_CSR_SCB_COMMAND, FXP_SCB_COMMAND_CU_START);
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/* ...and wait for it to complete. */
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i = 10000;
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while (!(cbp->cb_status & FXP_CB_STATUS_C) && (--i > 0))
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DELAY(1);
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if (i == 0)
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printf("config timeout");
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fxp_checkintr("config");
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cb_ias = SNDBUF_VIRT;
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/*
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* Now initialize the station address. Temporarily use the TxCB
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* memory area like we did above for the config CB.
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*/
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cb_ias->cb_status = 0;
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cb_ias->cb_command = FXP_CB_COMMAND_IAS | FXP_CB_COMMAND_EL;
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cb_ias->link_addr = -1;
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bcopy(myadr, (void *)cb_ias->macaddr, 6);
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/*
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* Start the IAS (Individual Address Setup) command/DMA.
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*/
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fxp_scb_wait();
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/* address is still there */
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CSR_WRITE_1(FXP_CSR_SCB_COMMAND, FXP_SCB_COMMAND_CU_START);
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/* ...and wait for it to complete. */
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i = 10000;
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while (!(cb_ias->cb_status & FXP_CB_STATUS_C) && (--i > 0))
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DELAY(1);
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if (i == 0)
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printf("ias timeout");
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fxp_checkintr("ias");
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fxp_startreceiver();
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#if defined(_STANDALONE) && !defined(SUPPORT_NO_NETBSD)
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strncpy(bi_netif.ifname, "fxp", sizeof(bi_netif.ifname));
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bi_netif.bus = BI_BUS_PCI;
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bi_netif.addr.tag = mytag;
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BI_ADD(&bi_netif, BTINFO_NETIF, sizeof(bi_netif));
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#endif
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return (1);
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}
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void
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EtherStop()
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{
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/*
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* Issue software reset
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*/
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CSR_WRITE_4(FXP_CSR_PORT, FXP_PORT_SELECTIVE_RESET);
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DELAY(10);
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}
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int EtherSend(pkt, len)
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char *pkt;
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int len;
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{
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volatile struct fxp_cb_tx *txp;
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int i;
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txp = SNDBUF_VIRT;
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txp->tbd[0].tb_size = len;
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#ifdef _STANDALONE
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txp->tbd[0].tb_addr = vtophys(pkt);
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#else
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txp->tbd[0].tb_addr = SNDBUF_PHYS + 400;
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#endif
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txp->tbd_number = 1;
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txp->cb_status = 0;
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txp->cb_command =
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FXP_CB_COMMAND_XMIT | FXP_CB_COMMAND_SF | FXP_CB_COMMAND_EL;
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txp->tx_threshold = tx_threshold;
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txp->link_addr = -1;
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txp->tbd_array_addr =
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(u_int32_t)&((struct fxp_cb_tx *)SNDBUF_PHYS)->tbd;
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txp->byte_count = 0;
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#ifndef _STANDALONE
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bcopy(pkt, SNDBUF_VIRT + 400, len);
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#endif
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fxp_scb_wait();
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CSR_WRITE_4(FXP_CSR_SCB_GENERAL, SNDBUF_PHYS + 12); /* XXX */
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CSR_WRITE_1(FXP_CSR_SCB_COMMAND, FXP_SCB_COMMAND_CU_START);
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/* ...and wait for it to complete. */
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i = 10000;
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while (!(txp->cb_status & FXP_CB_STATUS_C) && (--i > 0))
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DELAY(1);
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if (i == 0)
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printf("send timeout");
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fxp_checkintr("send");
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return (len);
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}
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static void
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fxp_startreceiver()
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{
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volatile struct fxp_rfa *rfa;
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u_int32_t v;
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rfa = RECVBUF_VIRT;
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rfa->size = RECVBUF_SIZE - sizeof(struct fxp_rfa);
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rfa->rfa_status = 0;
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rfa->rfa_control = FXP_RFA_CONTROL_S;
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rfa->actual_size = 0;
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v = RECVBUF_PHYS; /* close the "ring" */
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memcpy((void *)&rfa->link_addr, &v, sizeof(v));
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v = -1;
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memcpy((void *)&rfa->rbd_addr, &v, sizeof(v));
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fxp_scb_wait();
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CSR_WRITE_4(FXP_CSR_SCB_GENERAL, RECVBUF_PHYS);
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CSR_WRITE_1(FXP_CSR_SCB_COMMAND, FXP_SCB_COMMAND_RU_START);
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}
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int
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EtherReceive(pkt, maxlen)
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char *pkt;
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int maxlen;
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{
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u_int8_t ruscus;
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volatile struct fxp_rfa *rfa;
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int len = 0;
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ruscus = CSR_READ_1(FXP_CSR_SCB_RUSCUS);
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if (((ruscus >> 2) & 0x0f) == FXP_SCB_RUS_READY)
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return (0);
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if (((ruscus >> 2) & 0x0f) != FXP_SCB_RUS_SUSPENDED) {
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printf("rcv: ruscus=%x\n", ruscus);
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return (0);
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}
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rfa = RECVBUF_VIRT;
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if (rfa->rfa_status & FXP_RFA_STATUS_C) {
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len = rfa->actual_size & 0x7ff;
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if (len <= maxlen) {
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bcopy((caddr_t)(rfa + 1), pkt, maxlen);
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#if 0
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printf("rfa status=%x, len=%x, i=%d\n",
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rfa->rfa_status, len, i);
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#endif
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} else
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len = 0;
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}
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fxp_scb_wait();
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CSR_WRITE_1(FXP_CSR_SCB_COMMAND, FXP_SCB_COMMAND_RU_RESUME);
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return (len);
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}
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||||
|
||||
/*
|
||||
* Read from the serial EEPROM. Basically, you manually shift in
|
||||
* the read opcode (one bit at a time) and then shift in the address,
|
||||
* and then you shift out the data (all of this one bit at a time).
|
||||
* The word size is 16 bits, so you have to provide the address for
|
||||
* every 16 bits of data.
|
||||
*/
|
||||
static void
|
||||
fxp_read_eeprom(data, offset, words)
|
||||
u_int16_t *data;
|
||||
int offset;
|
||||
int words;
|
||||
{
|
||||
u_int16_t reg;
|
||||
int i, x;
|
||||
|
||||
for (i = 0; i < words; i++) {
|
||||
CSR_WRITE_2(FXP_CSR_EEPROMCONTROL, FXP_EEPROM_EECS);
|
||||
/*
|
||||
* Shift in read opcode.
|
||||
*/
|
||||
for (x = 3; x > 0; x--) {
|
||||
if (FXP_EEPROM_OPC_READ & (1 << (x - 1))) {
|
||||
reg = FXP_EEPROM_EECS | FXP_EEPROM_EEDI;
|
||||
} else {
|
||||
reg = FXP_EEPROM_EECS;
|
||||
}
|
||||
CSR_WRITE_2(FXP_CSR_EEPROMCONTROL, reg);
|
||||
CSR_WRITE_2(FXP_CSR_EEPROMCONTROL,
|
||||
reg | FXP_EEPROM_EESK);
|
||||
DELAY(1);
|
||||
CSR_WRITE_2(FXP_CSR_EEPROMCONTROL, reg);
|
||||
DELAY(1);
|
||||
}
|
||||
/*
|
||||
* Shift in address.
|
||||
*/
|
||||
for (x = 6; x > 0; x--) {
|
||||
if ((i + offset) & (1 << (x - 1))) {
|
||||
reg = FXP_EEPROM_EECS | FXP_EEPROM_EEDI;
|
||||
} else {
|
||||
reg = FXP_EEPROM_EECS;
|
||||
}
|
||||
CSR_WRITE_2(FXP_CSR_EEPROMCONTROL, reg);
|
||||
CSR_WRITE_2(FXP_CSR_EEPROMCONTROL,
|
||||
reg | FXP_EEPROM_EESK);
|
||||
DELAY(1);
|
||||
CSR_WRITE_2(FXP_CSR_EEPROMCONTROL, reg);
|
||||
DELAY(1);
|
||||
}
|
||||
reg = FXP_EEPROM_EECS;
|
||||
data[i] = 0;
|
||||
/*
|
||||
* Shift out data.
|
||||
*/
|
||||
for (x = 16; x > 0; x--) {
|
||||
CSR_WRITE_2(FXP_CSR_EEPROMCONTROL,
|
||||
reg | FXP_EEPROM_EESK);
|
||||
DELAY(1);
|
||||
if (CSR_READ_2(FXP_CSR_EEPROMCONTROL) &
|
||||
FXP_EEPROM_EEDO)
|
||||
data[i] |= (1 << (x - 1));
|
||||
CSR_WRITE_2(FXP_CSR_EEPROMCONTROL, reg);
|
||||
DELAY(1);
|
||||
}
|
||||
CSR_WRITE_2(FXP_CSR_EEPROMCONTROL, 0);
|
||||
DELAY(1);
|
||||
}
|
||||
}
|
||||
|
||||
Loading…
Reference in New Issue
Block a user