Simplify the blitting code slightly, and fix fenceposts.
This commit is contained in:
mycroft
parent
4ae80dbd09
commit
6db8861212
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@ -1,4 +1,4 @@
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/* $NetBSD: tga.c,v 1.42 2002/07/04 14:37:11 junyoung Exp $ */
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/* $NetBSD: tga.c,v 1.43 2002/09/16 16:33:13 mycroft Exp $ */
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/*
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* Copyright (c) 1995, 1996 Carnegie-Mellon University.
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@ -28,7 +28,7 @@
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*/
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#include <sys/cdefs.h>
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__KERNEL_RCSID(0, "$NetBSD: tga.c,v 1.42 2002/07/04 14:37:11 junyoung Exp $");
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__KERNEL_RCSID(0, "$NetBSD: tga.c,v 1.43 2002/09/16 16:33:13 mycroft Exp $");
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#include <sys/param.h>
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#include <sys/systm.h>
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@ -1072,32 +1072,6 @@ tga_rop_vtov(dst, dx, dy, w, h, rop, src, sx, sy)
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return -1;
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}
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wb = w * (dst->ri_depth / 8);
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if (sy >= dy) {
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ystart = 0;
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yend = h;
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ydir = 1;
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} else {
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ystart = h;
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yend = 0;
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ydir = -1;
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}
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if (sx >= dx) { /* moving to the left */
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xstart = 0;
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xend = w * (dst->ri_depth / 8) - 4;
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xdir = 1;
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} else { /* moving to the right */
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xstart = wb - ( wb >= 4*64 ? 4*64 : wb >= 64 ? 64 : 4 );
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xend = 0;
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xdir = -1;
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}
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#define XINC4 4
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#define XINC64 64
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#define XINC256 (64*4)
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yinc = ydir * dst->ri_stride;
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ystart *= dst->ri_stride;
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yend *= dst->ri_stride;
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srcb = sy * src->ri_stride + sx * (src->ri_depth/8);
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dstb = dy * dst->ri_stride + dx * (dst->ri_depth/8);
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tga_srcb = offset + (sy + src->ri_yorigin) * src->ri_stride +
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@ -1105,6 +1079,28 @@ tga_rop_vtov(dst, dx, dy, w, h, rop, src, sx, sy)
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tga_dstb = offset + (dy + dst->ri_yorigin) * dst->ri_stride +
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(dx + dst->ri_xorigin) * (dst->ri_depth/8);
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if (sy >= dy) {
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ystart = 0;
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yend = (h - 1) * dst->ri_stride;
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ydir = 1;
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} else {
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ystart = (h - 1) * dst->ri_stride;
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yend = 0;
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ydir = -1;
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}
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yinc = ydir * dst->ri_stride;
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wb = w * (dst->ri_depth / 8);
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if (sx >= dx) { /* moving to the left */
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xstart = 0;
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xend = wb;
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xdir = 1;
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} else { /* moving to the right */
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xstart = wb;
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xend = 0;
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xdir = -1;
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}
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TGAWALREG(dc, TGA_REG_GMOR, 3, 0x0007); /* Copy mode */
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TGAWALREG(dc, TGA_REG_GOPR, 3, map_rop[rop]); /* Set up the op */
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@ -1118,11 +1114,9 @@ tga_rop_vtov(dst, dx, dy, w, h, rop, src, sx, sy)
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if (xdir == 1) { /* move to the left */
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for (y = ystart; (ydir * y) <= (ydir * yend); y += yinc) {
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/* 4*64 byte chunks */
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for (xleft = wb, x = xstart;
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x <= xend && xleft >= 4*64;
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x += XINC256, xleft -= XINC256) {
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for (xleft = wb, x = xstart; xleft >= 4*64;
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x += 4*64, xleft -= 4*64) {
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/* XXX XXX Eight writes to different addresses should fill
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* XXX XXX up the write buffers on 21064 and 21164 chips,
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@ -1141,35 +1135,33 @@ tga_rop_vtov(dst, dx, dy, w, h, rop, src, sx, sy)
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}
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/* 64 byte chunks */
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for ( ; x <= xend && xleft >= 64;
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x += XINC64, xleft -= XINC64) {
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for (; xleft >= 64; x += 64, xleft -= 64) {
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TGAWALREG(dc, TGA_REG_GCSR, 0, tga_srcb + y + x + 0 * 64);
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TGAWALREG(dc, TGA_REG_GCDR, 0, tga_dstb + y + x + 0 * 64);
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}
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lastx = x; lastleft = xleft; /* remember for CPU loop */
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lastx = x; lastleft = xleft; /* remember for CPU loop */
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}
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TGAWALREG(dc, TGA_REG_GOPR, 0, 0x0003); /* op -> dst = src */
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TGAWALREG(dc, TGA_REG_GMOR, 0, 0x0000); /* Simple mode */
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if (lastleft) {
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for (y = ystart; (ydir * y) <= (ydir * yend); y += yinc) {
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/* 4 byte granularity */
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for (x = lastx, xleft = lastleft;
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x <= xend && xleft >= 4;
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x += XINC4, xleft -= XINC4) {
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*(uint32_t *)(dst->ri_bits + dstb + y + x) =
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*(uint32_t *)(dst->ri_bits + srcb + y + x);
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for (x = lastx, xleft = lastleft; xleft >= 4;
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x += 4, xleft -= 4) {
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*(uint32_t *)(dst->ri_bits + dstb + y + x + 0 * 4) =
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*(uint32_t *)(dst->ri_bits + srcb + y + x + 0 * 4);
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}
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}
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}
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}
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else { /* above move to the left, below move to the right */
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for (y = ystart; (ydir * y) <= (ydir * yend); y += yinc) {
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/* 4*64 byte chunks */
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for (xleft = wb, x = xstart;
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x >= xend && xleft >= 4*64;
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x -= XINC256, xleft -= XINC256) {
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for (xleft = wb, x = xstart; xleft >= 4*64;
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x -= 4*64, xleft -= 4*64) {
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/* XXX XXX Eight writes to different addresses should fill
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* XXX XXX up the write buffers on 21064 and 21164 chips,
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@ -1177,37 +1169,35 @@ tga_rop_vtov(dst, dx, dy, w, h, rop, src, sx, sy)
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* XXX XXX require further unrolling of this loop, or the
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* XXX XXX insertion of memory barriers.
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*/
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TGAWALREG(dc, TGA_REG_GCSR, 0, tga_srcb + y + x + 3 * 64);
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TGAWALREG(dc, TGA_REG_GCDR, 0, tga_dstb + y + x + 3 * 64);
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TGAWALREG(dc, TGA_REG_GCSR, 1, tga_srcb + y + x + 2 * 64);
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TGAWALREG(dc, TGA_REG_GCDR, 1, tga_dstb + y + x + 2 * 64);
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TGAWALREG(dc, TGA_REG_GCSR, 2, tga_srcb + y + x + 1 * 64);
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TGAWALREG(dc, TGA_REG_GCDR, 2, tga_dstb + y + x + 1 * 64);
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TGAWALREG(dc, TGA_REG_GCSR, 3, tga_srcb + y + x + 0 * 64);
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TGAWALREG(dc, TGA_REG_GCDR, 3, tga_dstb + y + x + 0 * 64);
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TGAWALREG(dc, TGA_REG_GCSR, 0, tga_srcb + y + x - 1 * 64);
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TGAWALREG(dc, TGA_REG_GCDR, 0, tga_dstb + y + x - 1 * 64);
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TGAWALREG(dc, TGA_REG_GCSR, 1, tga_srcb + y + x - 2 * 64);
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TGAWALREG(dc, TGA_REG_GCDR, 1, tga_dstb + y + x - 2 * 64);
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TGAWALREG(dc, TGA_REG_GCSR, 2, tga_srcb + y + x - 3 * 64);
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TGAWALREG(dc, TGA_REG_GCDR, 2, tga_dstb + y + x - 3 * 64);
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TGAWALREG(dc, TGA_REG_GCSR, 3, tga_srcb + y + x - 4 * 64);
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TGAWALREG(dc, TGA_REG_GCDR, 3, tga_dstb + y + x - 4 * 64);
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}
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if (xleft) x += XINC256 - XINC64;
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/* 64 byte chunks */
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for ( ; x >= xend && xleft >= 64;
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x -= XINC64, xleft -= XINC64) {
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TGAWALREG(dc, TGA_REG_GCSR, 0, tga_srcb + y + x + 0 * 64);
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TGAWALREG(dc, TGA_REG_GCDR, 0, tga_dstb + y + x + 0 * 64);
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for (; xleft >= 64; x -= 64, xleft -= 64) {
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TGAWALREG(dc, TGA_REG_GCSR, 0, tga_srcb + y + x - 1 * 64);
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TGAWALREG(dc, TGA_REG_GCDR, 0, tga_dstb + y + x - 1 * 64);
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}
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if (xleft) x += XINC64 - XINC4;
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lastx = x; lastleft = xleft; /* remember for CPU loop */
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}
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TGAWALREG(dc, TGA_REG_GOPR, 0, 0x0003); /* op -> dst = src */
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TGAWALREG(dc, TGA_REG_GMOR, 0, 0x0000); /* Simple mode */
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if (lastleft) {
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for (y = ystart; (ydir * y) <= (ydir * yend); y += yinc) {
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/* 4 byte granularity */
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for (x = lastx, xleft = lastleft;
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x >= xend && xleft >= 4;
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x -= XINC4, xleft -= XINC4) {
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*(uint32_t *)(dst->ri_bits + dstb + y + x) =
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*(uint32_t *)(dst->ri_bits + srcb + y + x);
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for (x = lastx, xleft = lastleft; xleft >= 4;
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x -= 4, xleft -= 4) {
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*(uint32_t *)(dst->ri_bits + dstb + y + x - 1 * 4) =
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*(uint32_t *)(dst->ri_bits + srcb + y + x - 1 * 4);
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}
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}
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}
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}
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