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By default, don't frob the ICU masks here. The software masking should 

be sufficient.
This commit is contained in:
mycroft 1995-05-03 14:31:35 +00:00
parent aff3578b36
commit 6db4e1b58a
1 changed files with 18 additions and 10 deletions
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28
sys/arch/i386/isa/vector.s
View File

@ -1,4 +1,4 @@
/* $NetBSD: vector.s,v 1.27 1995/05/01 08:25:42 mycroft Exp $ */ /* $NetBSD: vector.s,v 1.28 1995/05/03 14:31:35 mycroft Exp $ */
/* /*
* Copyright (c) 1993, 1994, 1995 Charles M. Hannum. All rights reserved. * Copyright (c) 1993, 1994, 1995 Charles M. Hannum. All rights reserved.
@ -33,9 +33,9 @@
#include <dev/isa/isareg.h> #include <dev/isa/isareg.h>
/* /*
* These macros are fairly self explanatory. If SPECIAL_MASK_MODE is defined, * These macros are fairly self explanatory. If ICU_SPECIAL_MASK_MODE is
* we try to take advantage of the ICU's `special mask mode' by only EOIing * defined, we try to take advantage of the ICU's `special mask mode' by only
* the interrupts on return. This avoids the requirement of masking and * EOIing the interrupts on return. This avoids the requirement of masking and
* unmasking. We can't do this without special mask mode, because the ICU * unmasking. We can't do this without special mask mode, because the ICU
* would also hold interrupts that it thinks are of lower priority. * would also hold interrupts that it thinks are of lower priority.
* *
@ -46,18 +46,18 @@
#define IRQ_BIT(irq_num) (1 << ((irq_num) % 8)) #define IRQ_BIT(irq_num) (1 << ((irq_num) % 8))
#define IRQ_BYTE(irq_num) ((irq_num) / 8) #define IRQ_BYTE(irq_num) ((irq_num) / 8)
#ifdef SPECIAL_MASK_MODE #ifdef ICU_SPECIAL_MASK_MODE
#define ENABLE_ICU1(irq_num) #define ENABLE_ICU1(irq_num)
#define ENABLE_ICU1_AND_2(irqnum) \ #define ENABLE_ICU1_AND_2(irqnum) \
movb $(0x60|2),%al /* specific EOI for IRQ2 */ ;\ movb $(0x60|IRQ_SLAVE),%al /* specific EOI for IRQ2 */ ;\
outb %al,$IO_ICU1 outb %al,$IO_ICU1
#define MASK(irq_num, icu) #define MASK(irq_num, icu)
#define UNMASK(irq_num, icu) \ #define UNMASK(irq_num, icu) \
movb $(0x60|(irq_num%8)),%al /* specific EOI */ ;\ movb $(0x60|(irq_num%8)),%al /* specific EOI */ ;\
outb %al,$icu outb %al,$icu
#else /* SPECIAL_MASK_MODE */ #else /* ICU_SPECIAL_MASK_MODE */
#ifndef AUTO_EOI_1 #ifndef AUTO_EOI_1
#define ENABLE_ICU1(irq_num) \ #define ENABLE_ICU1(irq_num) \
@ -71,19 +71,20 @@
#define ENABLE_ICU1_AND_2(irq_num) \ #define ENABLE_ICU1_AND_2(irq_num) \
movb $(0x60|(irq_num%8)),%al /* specific EOI */ ;\ movb $(0x60|(irq_num%8)),%al /* specific EOI */ ;\
outb %al,$IO_ICU2 /* do the second ICU first */ ;\ outb %al,$IO_ICU2 /* do the second ICU first */ ;\
movb $(0x60|2),%al /* specific EOI for IRQ2 */ ;\ movb $(0x60|IRQ_SLAVE),%al /* specific EOI for IRQ2 */ ;\
outb %al,$IO_ICU1 outb %al,$IO_ICU1
#else #else
#define ENABLE_ICU1_AND_2(irq_num) #define ENABLE_ICU1_AND_2(irq_num)
#endif #endif
#ifdef ICU_HARDWARE_MASK
#define MASK(irq_num, icu) \ #define MASK(irq_num, icu) \
movb _imen + IRQ_BYTE(irq_num),%al ;\ movb _imen + IRQ_BYTE(irq_num),%al ;\
orb $IRQ_BIT(irq_num),%al ;\ orb $IRQ_BIT(irq_num),%al ;\
movb %al,_imen + IRQ_BYTE(irq_num) ;\ movb %al,_imen + IRQ_BYTE(irq_num) ;\
FASTER_NOP ;\ FASTER_NOP ;\
outb %al,$(icu+1) outb %al,$(icu+1)
#define UNMASK(irq_num, icu) \ #define UNMASK(irq_num, icu) \
cli ;\ cli ;\
movb _imen + IRQ_BYTE(irq_num),%al ;\ movb _imen + IRQ_BYTE(irq_num),%al ;\
@ -93,7 +94,14 @@
outb %al,$(icu+1) ;\ outb %al,$(icu+1) ;\
sti sti
#endif /* SPECIAL_MASK_MODE */ #else /* ICU_HARDWARE_MASK */
#define MASK(irq_num, icu)
#define UNMASK(irq_num, icu)
#endif /* ICU_HARDWARE_MASK */
#endif /* ICU_SPECIAL_MASK_MODE */
/* /*
* Macros for interrupt entry, call to handler, and exit. * Macros for interrupt entry, call to handler, and exit.