bnx(4) SERDES NICs will definitely work better with the PHY initialization
code... rather than without. (forgot to commit it two weeks ago -- should be part of the BCM 5709S patch)
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jym
parent
60e66c6f48
commit
6da35ef6e8
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@ -1,4 +1,4 @@
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/* $NetBSD: if_bnx.c,v 1.40 2011/01/06 02:02:43 jym Exp $ */
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/* $NetBSD: if_bnx.c,v 1.41 2011/01/06 03:37:55 jym Exp $ */
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/* $OpenBSD: if_bnx.c,v 1.85 2009/11/09 14:32:41 dlg Exp $ */
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/*-
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@ -35,7 +35,7 @@
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#if 0
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__FBSDID("$FreeBSD: src/sys/dev/bce/if_bce.c,v 1.3 2006/04/13 14:12:26 ru Exp $");
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#endif
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__KERNEL_RCSID(0, "$NetBSD: if_bnx.c,v 1.40 2011/01/06 02:02:43 jym Exp $");
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__KERNEL_RCSID(0, "$NetBSD: if_bnx.c,v 1.41 2011/01/06 03:37:55 jym Exp $");
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/*
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* The following controllers are supported by this driver:
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@ -346,6 +346,7 @@ int bnx_nvram_write(struct bnx_softc *, u_int32_t, u_int8_t *, int);
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/* */
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/****************************************************************************/
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void bnx_get_media(struct bnx_softc *);
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void bnx_init_media(struct bnx_softc *);
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int bnx_dma_alloc(struct bnx_softc *);
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void bnx_dma_free(struct bnx_softc *);
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void bnx_release_resources(struct bnx_softc *);
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@ -459,6 +460,7 @@ bnx_attach(device_t parent, device_t self, void *aux)
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{
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const struct bnx_product *bp;
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struct bnx_softc *sc = device_private(self);
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prop_dictionary_t dict;
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struct pci_attach_args *pa = aux;
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pci_chipset_tag_t pc = pa->pa_pc;
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pci_intr_handle_t ih;
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@ -708,9 +710,17 @@ bnx_attach(device_t parent, device_t self, void *aux)
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sc->bnx_mii.mii_writereg = bnx_miibus_write_reg;
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sc->bnx_mii.mii_statchg = bnx_miibus_statchg;
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/* Handle any special PHY initialization for SerDes PHYs. */
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bnx_init_media(sc);
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sc->bnx_ec.ec_mii = &sc->bnx_mii;
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ifmedia_init(&sc->bnx_mii.mii_media, 0, ether_mediachange,
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ether_mediastatus);
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/* set phyflags before mii_attach() */
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dict = device_properties(self);
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prop_dictionary_set_uint32(dict, "phyflags", sc->bnx_phy_flags);
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if (sc->bnx_phy_flags & BNX_PHY_SERDES_FLAG)
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mii_flags |= MIIF_HAVEFIBER;
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mii_attach(self, &sc->bnx_mii, 0xffffffff,
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@ -920,6 +930,16 @@ bnx_miibus_read_reg(device_t dev, int phy, int reg)
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return(0);
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}
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/*
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* The BCM5709S PHY is an IEEE Clause 45 PHY
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* with special mappings to work with IEEE
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* Clause 22 register accesses.
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*/
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if ((sc->bnx_phy_flags & BNX_PHY_IEEE_CLAUSE_45_FLAG) != 0) {
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if (reg >= MII_BMCR && reg <= MII_ANLPRNP)
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reg += 0x10;
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}
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if (sc->bnx_phy_flags & BNX_PHY_INT_MODE_AUTO_POLLING_FLAG) {
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val = REG_RD(sc, BNX_EMAC_MDIO_MODE);
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val &= ~BNX_EMAC_MDIO_MODE_AUTO_POLL;
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@ -999,6 +1019,16 @@ bnx_miibus_write_reg(device_t dev, int phy, int reg, int val)
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"val = 0x%04X\n", __func__,
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phy, (u_int16_t) reg & 0xffff, (u_int16_t) val & 0xffff);
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/*
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* The BCM5709S PHY is an IEEE Clause 45 PHY
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* with special mappings to work with IEEE
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* Clause 22 register accesses.
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*/
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if ((sc->bnx_phy_flags & BNX_PHY_IEEE_CLAUSE_45_FLAG) != 0) {
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if (reg >= MII_BMCR && reg <= MII_ANLPRNP)
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reg += 0x10;
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}
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if (sc->bnx_phy_flags & BNX_PHY_INT_MODE_AUTO_POLLING_FLAG) {
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val1 = REG_RD(sc, BNX_EMAC_MDIO_MODE);
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val1 &= ~BNX_EMAC_MDIO_MODE_AUTO_POLL;
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@ -2005,6 +2035,14 @@ bnx_get_media(struct bnx_softc *sc)
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u_int32_t val;
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sc->bnx_flags |= BNX_NO_WOL_FLAG;
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if (BNX_CHIP_NUM(sc) == BNX_CHIP_NUM_5709)
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sc->bnx_phy_flags |= BNX_PHY_IEEE_CLAUSE_45_FLAG;
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/*
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* The BCM5708S, BCM5709S, and BCM5716S controllers use a
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* separate PHY for SerDes.
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*/
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if (BNX_CHIP_NUM(sc) != BNX_CHIP_NUM_5706) {
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sc->bnx_phy_addr = 2;
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val = REG_RD_IND(sc, sc->bnx_shmem_base +
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@ -2024,6 +2062,36 @@ bnx_get_media_exit:
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"Using PHY address %d.\n", sc->bnx_phy_addr);
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}
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/****************************************************************************/
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/* Performs PHY initialization required before MII drivers access the */
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/* device. */
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/* */
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/* Returns: */
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/* Nothing. */
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/****************************************************************************/
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void
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bnx_init_media(struct bnx_softc *sc)
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{
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if (sc->bnx_phy_flags & BNX_PHY_IEEE_CLAUSE_45_FLAG) {
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/*
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* Configure the BCM5709S / BCM5716S PHYs to use traditional
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* IEEE Clause 22 method. Otherwise we have no way to attach
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* the PHY to the mii(4) layer. PHY specific configuration
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* is done by the mii(4) layer.
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*/
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/* Select auto-negotiation MMD of the PHY. */
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bnx_miibus_write_reg(sc->bnx_dev, sc->bnx_phy_addr,
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BRGPHY_BLOCK_ADDR, BRGPHY_BLOCK_ADDR_ADDR_EXT);
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bnx_miibus_write_reg(sc->bnx_dev, sc->bnx_phy_addr,
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BRGPHY_ADDR_EXT, BRGPHY_ADDR_EXT_AN_MMD);
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bnx_miibus_write_reg(sc->bnx_dev, sc->bnx_phy_addr,
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BRGPHY_BLOCK_ADDR, BRGPHY_BLOCK_ADDR_COMBO_IEEE0);
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}
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}
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/****************************************************************************/
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/* Free any DMA memory owned by the driver. */
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/* */
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