Reorganize buserr/addrerr stuff, to allow omitting unused code in single-cpu
kernels, at the same time getting rid of up to 3 conditional branches and a bit over one cacheline fetch (for the 68060; the saving is a bit smaller for 040 and yet smaller for the 020/30). While we're here, also get rid of an redundant lea (using SP-relative addressing) and of two redundant pushes. While we're here, also fix a panic which would tear us down on 68060 machines if a branch prediction error ever occured.
This commit is contained in:
is
parent
f2b935d7c6
commit
6d6e724440
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@ -1,4 +1,4 @@
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/* $NetBSD: locore.s,v 1.81 1997/05/22 22:48:47 veego Exp $ */
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/* $NetBSD: locore.s,v 1.82 1997/06/04 22:12:45 is Exp $ */
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/*
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* Copyright (c) 1988 University of Utah.
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@ -102,30 +102,34 @@ _doadump:
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#include <m68k/m68k/trap_subr.s>
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.globl _trap, _nofault, _longjmp
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_buserr:
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tstl _nofault | device probe?
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jeq _addrerr | no, handle as usual
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movl _nofault,sp@- | yes,
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jbsr _longjmp | longjmp(nofault)
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_addrerr:
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#if defined(M68040) || defined(M68060)
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.globl _addrerr4060
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_addrerr4060:
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clrl sp@- | stack adjust count
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moveml #0xFFFF,sp@- | save user registers
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movl usp,a0 | save the user SP
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movl a0,sp@(FR_SP) | in the savearea
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lea sp@(FR_HW),a1 | grab base of HW berr frame
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cmpl #MMU_68040,_mmutype
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jne Lbe030
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movl a1@(8),sp@- | V = exception address
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clrl sp@- | dummy code
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moveq #0,d0
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movw a1@(6),d0 | get vector offset
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andw #0x0fff,d0
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cmpw #12,d0 | is it address error
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jeq Lisaerr
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#ifdef M68060
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btst #7,_machineid+3 | is it 68060?
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jeq Lbe040
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movel a1@(12),d0 | FSLW
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movl #T_ADDRERR,sp@- | mark address error
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jra _ASM_LABEL(faultstkadj) | and deal with it
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#endif
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#if defined(M68060)
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.globl _buserr60
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_buserr60:
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tstl _nofault | device probe?
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jeq Lnonofault60 | no, handle as usual
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movl _nofault,sp@- | yes,
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jbsr _longjmp | longjmp(nofault)
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/* NOTREACHED */
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Lnonofault60:
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clrl sp@- | stack adjust count
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moveml #0xFFFF,sp@- | save user registers
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movl usp,a0 | save the user SP
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movl a0,sp@(FR_SP) | in the savearea
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movel sp@(FR_HW+12),d0 | FSLW
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btst #2,d0 | branch prediction error?
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jeq Lnobpe
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movc cacr,d2
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@ -134,59 +138,85 @@ _addrerr:
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movl d0,d1
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andl #0x7ffd,d1
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addql #1,L60bpe
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jeq _ASM_LABEL(faultstkadjnotrap)
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jeq _ASM_LABEL(faultstkadjnotrap2)
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Lnobpe:
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movl d0,sp@ | code is FSLW now.
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| we need to adjust for misaligned addresses
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movl a1@(8),d1 | grab VA
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movl sp@(FR_HW+8),d1 | grab VA
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btst #27,d0 | check for mis-aligned access
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jeq Lberr3 | no, skip
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addl #28,d1 | yes, get into next page
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| operand case: 3,
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| instruction case: 4+12+12
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| XXX instr. case not done yet
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andl #PG_FRAME,d1 | and truncate
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Lberr3:
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movl d1,sp@(4)
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movl d1,sp@-
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movl d0,sp@- | code is FSLW now.
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andw #0x1f80,d0
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jeq Lisberr
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jra Lismerr
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Lbe040:
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movl #T_MMUFLT,sp@- | show that we are an MMU fault
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jra _ASM_LABEL(faultstkadj) | and deal with it
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#endif
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movl a1@(20),d1 | get fault address
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#if defined(M68040)
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.globl _buserr40
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_buserr40:
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tstl _nofault | device probe?
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jeq Lnonofault40 | no, handle as usual
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movl _nofault,sp@- | yes,
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jbsr _longjmp | longjmp(nofault)
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Lnonofault40:
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clrl sp@- | stack adjust count
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moveml #0xFFFF,sp@- | save user registers
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movl usp,a0 | save the user SP
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movl a0,sp@(FR_SP) | in the savearea
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movl sp@(FR_HW+20),d1 | get fault address
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moveq #0,d0
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movw a1@(12),d0 | get SSW
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movw sp@(FR_HW+12),d0 | get SSW
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btst #11,d0 | check for mis-aligned
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jeq Lbe1stpg | no skip
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addl #3,d1 | get into next page
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andl #PG_FRAME,d1 | and truncate
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Lbe1stpg:
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movl d1,sp@(4) | pass fault address.
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movl d0,sp@ | pass SSW as code
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movl d1,sp@- | pass fault address.
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movl d0,sp@- | pass SSW as code
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btst #10,d0 | test ATC
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jeq Lisberr | it is a bus error
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jra Lismerr
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Lbe030:
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movl #T_MMUFLT,sp@- | show that we are an MMU fault
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jra _ASM_LABEL(faultstkadj) | and deal with it
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#endif
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_buserr:
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tstl _nofault | device probe?
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jeq _addrerr | no, handle as usual
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movl _nofault,sp@- | yes,
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jbsr _longjmp | longjmp(nofault)
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_addrerr:
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#if !(defined(M68020) || defined(M68030))
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jra _badtrap
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#else
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clrl sp@- | stack adjust count
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moveml #0xFFFF,sp@- | save user registers
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movl usp,a0 | save the user SP
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movl a0,sp@(FR_SP) | in the savearea
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moveq #0,d0
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movw a1@(10),d0 | grab SSW for fault processing
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movw sp@(FR_HW+10),d0 | grab SSW for fault processing
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btst #12,d0 | RB set?
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jeq LbeX0 | no, test RC
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bset #14,d0 | yes, must set FB
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movw d0,a1@(10) | for hardware too
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movw d0,sp@(FR_HW+10) | for hardware too
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LbeX0:
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btst #13,d0 | RC set?
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jeq LbeX1 | no, skip
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bset #15,d0 | yes, must set FC
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movw d0,a1@(10) | for hardware too
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movw d0,sp@(FR_HW+10) | for hardware too
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LbeX1:
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btst #8,d0 | data fault?
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jeq Lbe0 | no, check for hard cases
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movl a1@(16),d1 | fault address is as given in frame
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movl sp@(FR_HW+16),d1 | fault address is as given in frame
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jra Lbe10 | thats it
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Lbe0:
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btst #4,a1@(6) | long (type B) stack frame?
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btst #4,sp@(FR_HW+6) | long (type B) stack frame?
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jne Lbe4 | yes, go handle
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movl a1@(2),d1 | no, can use save PC
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movl sp@(FR_HW+2),d1 | no, can use save PC
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btst #14,d0 | FB set?
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jeq Lbe3 | no, try FC
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addql #4,d1 | yes, adjust address
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@ -197,14 +227,14 @@ Lbe3:
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addql #2,d1 | yes, adjust address
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jra Lbe10 | done
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Lbe4:
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movl a1@(36),d1 | long format, use stage B address
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movl sp@(FR_HW+36),d1 | long format, use stage B address
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btst #15,d0 | FC set?
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jeq Lbe10 | no, all done
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subql #2,d1 | yes, adjust address
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Lbe10:
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movl d1,sp@- | push fault VA
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movl d0,sp@- | and padded SSW
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movw a1@(6),d0 | get frame format/vector offset
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movw sp@(FR_HW+8+6),d0 | get frame format/vector offset
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andw #0x0FFF,d0 | clear out frame format
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cmpw #12,d0 | address error vector?
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jeq Lisaerr | yes, go to it
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@ -214,7 +244,7 @@ Lbe10:
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jne Lbe10a
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movql #1,d0 | user program access FC
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| (we dont seperate data/program)
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btst #5,a1@ | supervisor mode?
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btst #5,sp@(FR_HW+8) | supervisor mode?
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jeq Lbe10a | if no, done
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movql #5,d0 | else supervisor program access
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Lbe10a:
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@ -241,7 +271,8 @@ Lisaerr:
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jra _ASM_LABEL(faultstkadj) | and deal with it
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Lisberr1:
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clrw sp@ | re-clear pad word
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Lisberr:
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#endif
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Lisberr: | also used by M68040/60
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movl #T_BUSERR,sp@- | mark bus error
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jra _ASM_LABEL(faultstkadj) | and deal with it
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@ -1,4 +1,4 @@
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/* $NetBSD: machdep.c,v 1.89 1997/04/09 19:32:09 thorpej Exp $ */
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/* $NetBSD: machdep.c,v 1.90 1997/06/04 22:12:46 is Exp $ */
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/*
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* Copyright (c) 1988 University of Utah.
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@ -1245,11 +1245,16 @@ void
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initcpu()
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{
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/* XXX should init '40 vecs here, too */
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#if defined(M68060) || defined(DRACO)
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#if defined(M68060) || defined(M68040) || defined(DRACO)
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extern caddr_t vectab[256];
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#endif
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#if defined(M68060) || defined(M68040)
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extern u_int8_t addrerr4060;
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#endif
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#ifdef M68060
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extern u_int8_t buserr60;
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#if defined(M060SP)
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/*extern u_int8_t I_CALL_TOP[];*/
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extern u_int8_t intemu60, fpiemu60, fpdemu60, fpeaemu60;
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@ -1260,6 +1265,10 @@ initcpu()
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extern u_int8_t fpfault;
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#endif
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#ifdef M68040
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extern u_int8_t buserr40;
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#endif
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#ifdef DRACO
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extern u_int8_t DraCoIntr, DraCoLev1intr, DraCoLev2intr;
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u_char dracorev;
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@ -1269,6 +1278,10 @@ initcpu()
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if (machineid & AMIGA_68060) {
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asm volatile ("movl %0,d0; .word 0x4e7b,0x0808" : :
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"d"(m68060_pcr_init):"d0" );
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/* bus/addrerr vectors */
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vectab[2] = &buserr60;
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vectab[3] = &addrerr4060;
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#if defined(M060SP)
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/* integer support */
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@ -1301,6 +1314,16 @@ initcpu()
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/*
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* Vector initialization for special motherboards
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*/
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#ifdef M68040
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#ifdef M68060
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else
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#endif
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if (machineid & AMIGA_68040) {
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/* addrerr vector */
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vectab[2] = &buserr40;
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vectab[3] = &addrerr4060;
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}
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#endif
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#ifdef DRACO
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dracorev = is_draco();
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@ -1,4 +1,4 @@
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/* $NetBSD: trap_subr.s,v 1.1 1997/04/25 01:33:18 thorpej Exp $ */
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/* $NetBSD: trap_subr.s,v 1.2 1997/06/04 22:12:43 is Exp $ */
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/*
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* Copyright (c) 1988 University of Utah.
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@ -75,6 +75,8 @@ ASENTRY(faultstkadj)
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/* for 68060 Branch Prediction Error handler */
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_ASM_LABEL(faultstkadjnotrap):
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lea sp@(12),sp | pop value args
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/* for new 68060 Branch Prediction Error handler */
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_ASM_LABEL(faultstkadjnotrap2):
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movl sp@(FR_SP),a0 | restore user SP
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movl a0,usp | from save area
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movw sp@(FR_ADJ),d0 | need to adjust stack?
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