Update for walnut.h/ibm405gp.h changes.
This commit is contained in:
simonb
parent
8980655597
commit
6d4b6ead83
@ -1,4 +1,4 @@
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/* $NetBSD: ibm405gp.c,v 1.2 2001/06/22 11:37:49 simonb Exp $ */
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/* $NetBSD: ibm405gp.c,v 1.3 2001/06/24 01:15:41 simonb Exp $ */
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/*
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* Copyright 2001 Wasabi Systems, Inc.
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@ -40,7 +40,6 @@
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#include <sys/systm.h>
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#include <machine/bus.h>
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#include <machine/walnut.h>
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#include <dev/pci/pcivar.h>
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#include <powerpc/ibm4xx/ibm405gp.h>
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@ -54,7 +53,7 @@ static void setup_pcicfg_window(void)
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{
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if (pcicfg_ioh)
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return;
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if (bus_space_map(pcicfg_iot, PCIL_BASE, 0x40 , 0, &pcicfg_ioh))
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if (bus_space_map(pcicfg_iot, PCIL0_BASE, 0x40 , 0, &pcicfg_ioh))
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panic("Cannot map PCI configuration registers\n");
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}
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@ -69,29 +68,29 @@ void galaxy_setup_pci(void)
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setup_pcicfg_window();
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/* Disable all three memory mappers */
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bus_space_write_4(pcicfg_iot, pcicfg_ioh, PMM0MA, 0x00000000); /* disabled */
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bus_space_write_4(pcicfg_iot, pcicfg_ioh, PMM1MA, 0x00000000); /* disabled */
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bus_space_write_4(pcicfg_iot, pcicfg_ioh, PMM2MA, 0x00000000); /* disabled */
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bus_space_write_4(pcicfg_iot, pcicfg_ioh, PTM1MS, 0x00000000); /* Can't really disable PTM1. */
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bus_space_write_4(pcicfg_iot, pcicfg_ioh, PTM2MS, 0x00000000); /* disabled */
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bus_space_write_4(pcicfg_iot, pcicfg_ioh, PCIL0_PMM0MA, 0x00000000); /* disabled */
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bus_space_write_4(pcicfg_iot, pcicfg_ioh, PCIL0_PMM1MA, 0x00000000); /* disabled */
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bus_space_write_4(pcicfg_iot, pcicfg_ioh, PCIL0_PMM2MA, 0x00000000); /* disabled */
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bus_space_write_4(pcicfg_iot, pcicfg_ioh, PCIL0_PTM1MS, 0x00000000); /* Can't really disable PTM1. */
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bus_space_write_4(pcicfg_iot, pcicfg_ioh, PCIL0_PTM2MS, 0x00000000); /* disabled */
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/* Setup memory map #0 */
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bus_space_write_4(pcicfg_iot, pcicfg_ioh, PMM0MA, 0xF0000001); /* 256M non-prefetchable, enabled */
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bus_space_write_4(pcicfg_iot, pcicfg_ioh, PCIL0_PMM0MA, 0xF0000001); /* 256M non-prefetchable, enabled */
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bus_space_write_4(pcicfg_iot, pcicfg_ioh, PMM0LA, PCI0_MEM_BASE);
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bus_space_write_4(pcicfg_iot, pcicfg_ioh, PMM0PCILA, PCI0_MEM_BASE);
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bus_space_write_4(pcicfg_iot, pcicfg_ioh, PMM0PCIHA, 0);
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bus_space_write_4(pcicfg_iot, pcicfg_ioh, PCIL0_PMM0LA, PCI0_MEM_BASE);
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bus_space_write_4(pcicfg_iot, pcicfg_ioh, PCIL0_PMM0PCILA, PCI0_MEM_BASE);
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bus_space_write_4(pcicfg_iot, pcicfg_ioh, PCIL0_PMM0PCIHA, 0);
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/* Configure PCI bridge */
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tag = pci_make_tag(0, 0, 0, 0);
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// x = pci_conf_read(0, tag, PCI0_CMD); /* Read PCI command register */
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// pci_conf_write(0, tag, PCI0_CMD, x | MA | ME); /* enable bus mastering and memory space */
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bus_space_write_4(pcicfg_iot, pcicfg_ioh, PTM1MS, 0xF0000001); /* Enable PTM1 */
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bus_space_write_4(pcicfg_iot, pcicfg_ioh, PTM1LA, 0);
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pci_conf_write(0, tag, PCI0_PTM1BAR, 0); /* Set up proper PCI->Local address base. Always enabled */
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pci_conf_write(0, tag, PCI0_PTM2BAR, 0);
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bus_space_write_4(pcicfg_iot, pcicfg_ioh, PCIL0_PTM1MS, 0xF0000001); /* Enable PTM1 */
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bus_space_write_4(pcicfg_iot, pcicfg_ioh, PCIL0_PTM1LA, 0);
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pci_conf_write(0, tag, PCIC0_PTM1BAR, 0); /* Set up proper PCI->Local address base. Always enabled */
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pci_conf_write(0, tag, PCIC0_PTM2BAR, 0);
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}
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void galaxy_show_pci_map(void)
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@ -102,38 +101,38 @@ void galaxy_show_pci_map(void)
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setup_pcicfg_window();
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printf("Local -> PCI map\n");
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la = bus_space_read_4(pcicfg_iot, pcicfg_ioh, PMM0LA);
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lm = bus_space_read_4(pcicfg_iot, pcicfg_ioh, PMM0MA);
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pl = bus_space_read_4(pcicfg_iot, pcicfg_ioh, PMM0PCILA);
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ph = bus_space_read_4(pcicfg_iot, pcicfg_ioh, PMM0PCIHA);
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la = bus_space_read_4(pcicfg_iot, pcicfg_ioh, PCIL0_PMM0LA);
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lm = bus_space_read_4(pcicfg_iot, pcicfg_ioh, PCIL0_PMM0MA);
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pl = bus_space_read_4(pcicfg_iot, pcicfg_ioh, PCIL0_PMM0PCILA);
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ph = bus_space_read_4(pcicfg_iot, pcicfg_ioh, PCIL0_PMM0PCIHA);
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printf("0: %08lx,%08lx -> %08lx%08lx %sprefetchable, %s\n", la, lm, ph, pl,
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(lm & 2) ? "":"not ",
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(lm & 1) ? "enabled":"disabled");
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la = bus_space_read_4(pcicfg_iot, pcicfg_ioh, PMM1LA);
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lm = bus_space_read_4(pcicfg_iot, pcicfg_ioh, PMM1MA);
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pl = bus_space_read_4(pcicfg_iot, pcicfg_ioh, PMM1PCILA);
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ph = bus_space_read_4(pcicfg_iot, pcicfg_ioh, PMM1PCIHA);
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la = bus_space_read_4(pcicfg_iot, pcicfg_ioh, PCIL0_PMM1LA);
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lm = bus_space_read_4(pcicfg_iot, pcicfg_ioh, PCIL0_PMM1MA);
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pl = bus_space_read_4(pcicfg_iot, pcicfg_ioh, PCIL0_PMM1PCILA);
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ph = bus_space_read_4(pcicfg_iot, pcicfg_ioh, PCIL0_PMM1PCIHA);
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printf("1: %08lx,%08lx -> %08lx%08lx %sprefetchable, %s\n", la, lm, ph, pl,
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(lm & 2) ? "":"not ",
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(lm & 1) ? "enabled":"disabled");
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la = bus_space_read_4(pcicfg_iot, pcicfg_ioh, PMM2LA);
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lm = bus_space_read_4(pcicfg_iot, pcicfg_ioh, PMM2MA);
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pl = bus_space_read_4(pcicfg_iot, pcicfg_ioh, PMM2PCILA);
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ph = bus_space_read_4(pcicfg_iot, pcicfg_ioh, PMM2PCIHA);
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la = bus_space_read_4(pcicfg_iot, pcicfg_ioh, PCIL0_PMM2LA);
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lm = bus_space_read_4(pcicfg_iot, pcicfg_ioh, PCIL0_PMM2MA);
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pl = bus_space_read_4(pcicfg_iot, pcicfg_ioh, PCIL0_PMM2PCILA);
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ph = bus_space_read_4(pcicfg_iot, pcicfg_ioh, PCIL0_PMM2PCIHA);
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printf("2: %08lx,%08lx -> %08lx%08lx %sprefetchable, %s\n", la, lm, ph, pl,
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(lm & 2) ? "":"not ",
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(lm & 1) ? "enabled":"disabled");
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printf("PCI -> Local map\n");
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tag = pci_make_tag(0, 0, 0, 0);
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pl = pci_conf_read(0, tag, PCI0_PTM1BAR);
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la = bus_space_read_4(pcicfg_iot, pcicfg_ioh, PTM1LA);
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lm = bus_space_read_4(pcicfg_iot, pcicfg_ioh, PTM1MS);
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pl = pci_conf_read(0, tag, PCIC0_PTM1BAR);
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la = bus_space_read_4(pcicfg_iot, pcicfg_ioh, PCIL0_PTM1LA);
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lm = bus_space_read_4(pcicfg_iot, pcicfg_ioh, PCIL0_PTM1MS);
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printf("1: %08lx -> %08lx,%08lx %s\n", pl, la, lm,
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(lm & 1)?"enabled":"disabled");
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pl = pci_conf_read(0, tag, PCI0_PTM2BAR);
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la = bus_space_read_4(pcicfg_iot, pcicfg_ioh, PTM2LA);
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lm = bus_space_read_4(pcicfg_iot, pcicfg_ioh, PTM2MS);
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pl = pci_conf_read(0, tag, PCIC0_PTM2BAR);
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la = bus_space_read_4(pcicfg_iot, pcicfg_ioh, PCIL0_PTM2LA);
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lm = bus_space_read_4(pcicfg_iot, pcicfg_ioh, PCIL0_PTM2MS);
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printf("2: %08lx -> %08lx,%08lx %s\n", pl, la, lm,
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(lm & 1)?"enabled":"disabled");
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}
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@ -1,4 +1,4 @@
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/* $NetBSD: pci_machdep.c,v 1.1 2001/06/13 06:02:00 simonb Exp $ */
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/* $NetBSD: pci_machdep.c,v 1.2 2001/06/24 01:15:41 simonb Exp $ */
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/*
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* Copyright (c) 1996 Christopher G. Demetriou. All rights reserved.
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@ -70,14 +70,12 @@
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static bus_space_tag_t pci_iot;
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static bus_space_handle_t pci_ioh;
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#define OFF(r) ((r)-PCI0_CFGADDR)
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void pci_machdep_init(void)
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{
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if (pci_ioh == 0) {
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pci_iot = 0;
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if (bus_space_map(pci_iot,PCI0_CFGADDR,8,0,&pci_ioh)){
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if (bus_space_map(pci_iot, PCIC0_BASE, 8, 0, &pci_ioh)){
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panic("Cannot map PCI registers\n");
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}
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}
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@ -141,9 +139,9 @@ pci_conf_read(pci_chipset_tag_t pc, pcitag_t tag, int reg)
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pcireg_t data;
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/* 405GT BIOS disables interrupts here. Should we? --Art */
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bus_space_write_4(pci_iot,pci_ioh, OFF(PCI0_CFGADDR), tag | reg);
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data = bus_space_read_4(pci_iot,pci_ioh,OFF(PCI0_CFGDATA));
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bus_space_write_4(pci_iot,pci_ioh,OFF(PCI0_CFGADDR), 0); /* 405GP pass2 errata #6 */
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bus_space_write_4(pci_iot, pci_ioh, PCIC0_CFGADDR, tag | reg);
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data = bus_space_read_4(pci_iot, pci_ioh, PCIC0_CFGDATA);
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bus_space_write_4(pci_iot, pci_ioh, PCIC0_CFGADDR, 0); /* 405GP pass2 errata #6 */
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return data;
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}
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@ -151,9 +149,9 @@ void
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pci_conf_write(pci_chipset_tag_t pc, pcitag_t tag, int reg, pcireg_t data)
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{
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bus_space_write_4(pci_iot,pci_ioh, OFF(PCI0_CFGADDR), tag | reg);
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bus_space_write_4(pci_iot,pci_ioh,OFF(PCI0_CFGDATA), data);
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bus_space_write_4(pci_iot,pci_ioh,OFF(PCI0_CFGADDR), 0); /* 405GP pass2 errata #6 */
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bus_space_write_4(pci_iot, pci_ioh, PCIC0_CFGADDR, tag | reg);
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bus_space_write_4(pci_iot, pci_ioh, PCIC0_CFGDATA, data);
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bus_space_write_4(pci_iot, pci_ioh, PCIC0_CFGADDR, 0); /* 405GP pass2 errata #6 */
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}
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@ -179,7 +177,7 @@ pci_intr_map(struct pci_attach_args *pa, pci_intr_handle_t *ihp)
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case 3: *ihp = 2; break; /* Slot 1 Ext IRQ 5 */
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case 4: *ihp = 1; break; /* Slot 0 Ext IRQ 6 */
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default:
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printf("Hmm.. PCI device %d should not exist on this board\n",dev);
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printf("Hmm.. PCI device %d should not exist on this board\n", dev);
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goto bad;
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}
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return 0;
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@ -192,7 +190,7 @@ bad:
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const char *
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pci_intr_string(pci_chipset_tag_t pc, pci_intr_handle_t ih)
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{
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static char irqstr[8]; /* 4 + 2 + NULL + sanity */
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static char irqstr[8]; /* 4 + 2 + NUL + sanity */
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if (ih == 0 || ih >= ICU_LEN)
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panic("pci_intr_string: bogus handle 0x%x\n", ih);
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@ -1,4 +1,4 @@
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/* $NetBSD: consinit.c,v 1.1 2001/06/13 06:02:01 simonb Exp $ */
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/* $NetBSD: consinit.c,v 1.2 2001/06/24 01:15:41 simonb Exp $ */
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/*
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* Copyright (c) 1998
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@ -31,7 +31,7 @@
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#include <sys/device.h>
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#include <machine/bus.h>
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#include <machine/walnut.h>
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#include <powerpc/ibm4xx/ibm405gp.h>
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#include "com.h"
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#if (NCOM > 0)
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@ -1,4 +1,4 @@
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/* $NetBSD: locore.S,v 1.1 2001/06/13 06:02:01 simonb Exp $ */
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/* $NetBSD: locore.S,v 1.2 2001/06/24 01:15:41 simonb Exp $ */
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/* $OpenBSD: locore.S,v 1.4 1997/01/26 09:06:38 rahnds Exp $ */
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/*
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@ -83,10 +83,8 @@
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#include <machine/psl.h>
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#include <machine/trap.h>
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#include <machine/asm.h>
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#include <machine/walnut.h>
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#include <powerpc/spr.h>
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#include <powerpc/ibm4xx/dcr.h>
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#include <powerpc/ibm4xx/pmap.h>
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@ -1,4 +1,4 @@
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/* $NetBSD: mainbus.c,v 1.3 2001/06/22 13:21:35 simonb Exp $ */
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/* $NetBSD: mainbus.c,v 1.4 2001/06/24 01:15:41 simonb Exp $ */
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/*
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* Copyright 2001 Wasabi Systems, Inc.
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@ -79,12 +79,12 @@
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#include <machine/bus.h>
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#include <machine/walnut.h>
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#include <powerpc/ibm4xx/ibm405gp.h>
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#include <dev/pci/pcivar.h>
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#include <dev/pci/pcidevs.h>
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#include <dev/pci/pciconf.h>
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#include <powerpc/ibm4xx/ibm405gp.h>
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/*
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* The devices built in to the 405GP cpu.
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*/
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@ -96,9 +96,9 @@ const struct ppc405gp_dev {
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{ "com", UART0_BASE, 5 },
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{ "com", UART1_BASE, 6 },
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{ "dsrtc", NVRAM_BASE, -1 },
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{ "emac", MIO6_START, 9 }, /* XXX: really irq 9..15 */
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{ "gpio", MIO5_START, -1 },
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{ "i2c", MIO4_START, -1 },
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{ "emac", EMAC0_BASE, 9 }, /* XXX: really irq 9..15 */
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{ "gpio", GPIO0_BASE, -1 },
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{ "i2c", IIC0_BASE, -1 },
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{ "wdog", -1, -1 },
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{ "pckbc", KEY_MOUSE_BASE, -1 }, /* XXX: really irq x..x+1 */
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{ NULL }
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