- Don't access VPD even if hardware advertised the capability.
It seems that some revisions of the controllers hang while accessing the VPD. Because VPD access routine is now unused, nuke it. - Let TWSI reload EEPROM if VPD capability is detected. Reloading the EEPROM will also set the Ethernet address, so age(4) now reads AGE_PAR0 and AGE_PAR1 register to get the Ethernet address. This removes removes a lot of hacks and enhance readability a lot. - Double PHY reset timeout as it takes more time to take the PHY out of power-saving state. - Explicitly check power-saving state by checking undocumented PHY registers. If link is not up, poke undocumented registers to take PHY out of power-saving state. This is the same thing done by the Linux driver. - Don't rely on auto-clearing feature of master reset bit, just wait 1ms and check idle status of MAC. From FreeBSD via OpenBSD.
This commit is contained in:
cegger
parent
b297f62c5a
commit
6d027845ab
@ -1,4 +1,4 @@
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/* $NetBSD: if_age.c,v 1.29 2009/08/04 13:17:55 cegger Exp $ */
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/* $NetBSD: if_age.c,v 1.30 2009/08/05 12:07:16 cegger Exp $ */
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/* $OpenBSD: if_age.c,v 1.1 2009/01/16 05:00:34 kevlo Exp $ */
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/*-
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@ -31,7 +31,7 @@
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/* Driver for Attansic Technology Corp. L1 Gigabit Ethernet. */
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#include <sys/cdefs.h>
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__KERNEL_RCSID(0, "$NetBSD: if_age.c,v 1.29 2009/08/04 13:17:55 cegger Exp $");
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__KERNEL_RCSID(0, "$NetBSD: if_age.c,v 1.30 2009/08/05 12:07:16 cegger Exp $");
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#include "bpfilter.h"
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#include "vlan.h"
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@ -97,7 +97,6 @@ static void age_mediastatus(struct ifnet *, struct ifmediareq *);
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static int age_mediachange(struct ifnet *);
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static int age_intr(void *);
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static int age_read_vpd_word(struct age_softc *, uint32_t, uint32_t, uint32_t *);
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static int age_dma_alloc(struct age_softc *);
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static void age_dma_free(struct age_softc *);
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static void age_get_macaddr(struct age_softc *, uint8_t[]);
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@ -558,37 +557,11 @@ back:
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return 1;
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}
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static int
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age_read_vpd_word(struct age_softc *sc, uint32_t vpdc, uint32_t offset,
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uint32_t *word)
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{
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int i;
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pcireg_t rv;
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pci_conf_write(sc->sc_pct, sc->sc_pcitag, PCI_VPD_ADDRESS(vpdc),
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offset << PCI_VPD_ADDRESS_SHIFT);
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for (i = AGE_TIMEOUT; i > 0; i--) {
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DELAY(10);
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rv = pci_conf_read(sc->sc_pct, sc->sc_pcitag,
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PCI_VPD_ADDRESS(vpdc));
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if ((rv & PCI_VPD_OPFLAG) == PCI_VPD_OPFLAG)
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break;
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}
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if (i == 0) {
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printf("%s: VPD read timeout!\n", device_xname(sc->sc_dev));
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*word = 0;
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return ETIMEDOUT;
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}
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*word = pci_conf_read(sc->sc_pct, sc->sc_pcitag, PCI_VPD_DATAREG(vpdc));
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return 0;
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}
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static void
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age_get_macaddr(struct age_softc *sc, uint8_t eaddr[])
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{
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uint32_t ea[2], off, reg, word;
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int vpd_error, match, vpdc;
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uint32_t ea[2], reg;
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int i, vpdc;
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reg = CSR_READ_4(sc, AGE_SPI_CTRL);
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if ((reg & SPI_VPD_ENB) != 0) {
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@ -597,67 +570,22 @@ age_get_macaddr(struct age_softc *sc, uint8_t eaddr[])
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CSR_WRITE_4(sc, AGE_SPI_CTRL, reg);
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}
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vpd_error = 0;
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ea[0] = ea[1] = 0;
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if ((vpd_error = pci_get_capability(sc->sc_pct, sc->sc_pcitag,
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PCI_CAP_VPD, &vpdc, NULL))) {
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if (pci_get_capability(sc->sc_pct, sc->sc_pcitag,
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PCI_CAP_VPD, &vpdc, NULL)) {
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/*
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* PCI VPD capability exists, but it seems that it's
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* not in the standard form as stated in PCI VPD
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* specification such that driver could not use
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* pci_get_vpd_readonly(9) with keyword 'NA'.
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* Search VPD data starting at address 0x0100. The data
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* should be used as initializers to set AGE_PAR0,
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* AGE_PAR1 register including other PCI configuration
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* registers.
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* PCI VPD capability found, let TWSI reload EEPROM.
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* This will set Ethernet address of controller.
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*/
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word = 0;
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match = 0;
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reg = 0;
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for (off = AGE_VPD_REG_CONF_START; off < AGE_VPD_REG_CONF_END;
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off += sizeof(uint32_t)) {
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vpd_error = age_read_vpd_word(sc, vpdc, off, &word);
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if (vpd_error != 0)
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break;
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if (match != 0) {
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switch (reg) {
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case AGE_PAR0:
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ea[0] = word;
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break;
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case AGE_PAR1:
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ea[1] = word;
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break;
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default:
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break;
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}
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match = 0;
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} else if ((word & 0xFF) == AGE_VPD_REG_CONF_SIG) {
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match = 1;
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reg = word >> 16;
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} else
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CSR_WRITE_4(sc, AGE_TWSI_CTRL, CSR_READ_4(sc, AGE_TWSI_CTRL) |
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TWSI_CTRL_SW_LD_START);
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for (i = 100; i > 0; i++) {
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DELAY(1000);
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reg = CSR_READ_4(sc, AGE_TWSI_CTRL);
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if ((reg & TWSI_CTRL_SW_LD_START) == 0)
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break;
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}
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if (off >= AGE_VPD_REG_CONF_END)
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vpd_error = ENOENT;
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if (vpd_error == 0) {
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/*
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* Don't blindly trust ethernet address obtained
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* from VPD. Check whether ethernet address is
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* valid one. Otherwise fall-back to reading
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* PAR register.
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*/
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ea[1] &= 0xFFFF;
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if ((ea[0] == 0 && ea[1] == 0) ||
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(ea[0] == 0xFFFFFFFF && ea[1] == 0xFFFF)) {
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if (agedebug)
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printf("%s: invalid ethernet address "
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"returned from VPD.\n",
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device_xname(sc->sc_dev));
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vpd_error = EINVAL;
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}
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}
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if (vpd_error != 0 && (agedebug))
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printf("%s: VPD access failure!\n",
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if (i == 0)
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printf("%s: reloading EEPROM timeout!\n",
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device_xname(sc->sc_dev));
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} else {
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if (agedebug)
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@ -665,26 +593,9 @@ age_get_macaddr(struct age_softc *sc, uint8_t eaddr[])
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device_xname(sc->sc_dev));
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}
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/*
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* It seems that L1 also provides a way to extract ethernet
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* address via SPI flash interface. Because SPI flash memory
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* device of different vendors vary in their instruction
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* codes for read ID instruction, it's very hard to get
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* instructions codes without detailed information for the
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* flash memory device used on ethernet controller. To simplify
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* code, just read AGE_PAR0/AGE_PAR1 register to get ethernet
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* address which is supposed to be set by hardware during
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* power on reset.
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*/
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if (vpd_error != 0) {
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/*
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* VPD is mapped to SPI flash memory or BIOS set it.
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*/
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ea[0] = CSR_READ_4(sc, AGE_PAR0);
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ea[1] = CSR_READ_4(sc, AGE_PAR1);
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}
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ea[0] = CSR_READ_4(sc, AGE_PAR0);
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ea[1] = CSR_READ_4(sc, AGE_PAR1);
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ea[1] &= 0xFFFF;
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eaddr[0] = (ea[1] >> 8) & 0xFF;
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eaddr[1] = (ea[1] >> 0) & 0xFF;
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eaddr[2] = (ea[0] >> 24) & 0xFF;
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@ -696,11 +607,79 @@ age_get_macaddr(struct age_softc *sc, uint8_t eaddr[])
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static void
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age_phy_reset(struct age_softc *sc)
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{
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uint16_t reg, pn;
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int i, linkup;
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/* Reset PHY. */
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CSR_WRITE_4(sc, AGE_GPHY_CTRL, GPHY_CTRL_RST);
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DELAY(1000);
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DELAY(2000);
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CSR_WRITE_4(sc, AGE_GPHY_CTRL, GPHY_CTRL_CLR);
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DELAY(1000);
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DELAY(2000);
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#define ATPHY_DBG_ADDR 0x1D
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#define ATPHY_DBG_DATA 0x1E
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#define ATPHY_CDTC 0x16
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#define PHY_CDTC_ENB 0x0001
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#define PHY_CDTC_POFF 8
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#define ATPHY_CDTS 0x1C
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#define PHY_CDTS_STAT_OK 0x0000
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#define PHY_CDTS_STAT_SHORT 0x0100
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#define PHY_CDTS_STAT_OPEN 0x0200
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#define PHY_CDTS_STAT_INVAL 0x0300
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#define PHY_CDTS_STAT_MASK 0x0300
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/* Check power saving mode. Magic from Linux. */
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age_miibus_writereg(sc->sc_dev, sc->age_phyaddr, MII_BMCR, BMCR_RESET);
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for (linkup = 0, pn = 0; pn < 4; pn++) {
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age_miibus_writereg(sc->sc_dev, sc->age_phyaddr, ATPHY_CDTC,
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(pn << PHY_CDTC_POFF) | PHY_CDTC_ENB);
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for (i = 200; i > 0; i--) {
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DELAY(1000);
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reg = age_miibus_readreg(sc->sc_dev, sc->age_phyaddr,
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ATPHY_CDTC);
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if ((reg & PHY_CDTC_ENB) == 0)
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break;
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}
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DELAY(1000);
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reg = age_miibus_readreg(sc->sc_dev, sc->age_phyaddr,
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ATPHY_CDTS);
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if ((reg & PHY_CDTS_STAT_MASK) != PHY_CDTS_STAT_OPEN) {
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linkup++;
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break;
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}
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}
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age_miibus_writereg(sc->sc_dev, sc->age_phyaddr, MII_BMCR,
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BMCR_RESET | BMCR_AUTOEN | BMCR_STARTNEG);
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if (linkup == 0) {
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age_miibus_writereg(sc->sc_dev, sc->age_phyaddr,
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ATPHY_DBG_ADDR, 0);
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age_miibus_writereg(sc->sc_dev, sc->age_phyaddr,
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ATPHY_DBG_DATA, 0x124E);
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age_miibus_writereg(sc->sc_dev, sc->age_phyaddr,
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ATPHY_DBG_ADDR, 1);
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reg = age_miibus_readreg(sc->sc_dev, sc->age_phyaddr,
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ATPHY_DBG_DATA);
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age_miibus_writereg(sc->sc_dev, sc->age_phyaddr,
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ATPHY_DBG_DATA, reg | 0x03);
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/* XXX */
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DELAY(1500 * 1000);
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age_miibus_writereg(sc->sc_dev, sc->age_phyaddr,
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ATPHY_DBG_ADDR, 0);
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age_miibus_writereg(sc->sc_dev, sc->age_phyaddr,
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ATPHY_DBG_DATA, 0x024E);
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}
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#undef ATPHY_DBG_ADDR
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#undef ATPHY_DBG_DATA
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#undef ATPHY_CDTC
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#undef PHY_CDTC_ENB
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#undef PHY_CDTC_POFF
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#undef ATPHY_CDTS
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#undef PHY_CDTS_STAT_OK
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#undef PHY_CDTS_STAT_SHORT
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#undef PHY_CDTS_STAT_OPEN
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#undef PHY_CDTS_STAT_INVAL
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#undef PHY_CDTS_STAT_MASK
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}
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static int
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@ -1616,14 +1595,8 @@ age_reset(struct age_softc *sc)
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int i;
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CSR_WRITE_4(sc, AGE_MASTER_CFG, MASTER_RESET);
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for (i = AGE_RESET_TIMEOUT; i > 0; i--) {
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DELAY(1);
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if ((CSR_READ_4(sc, AGE_MASTER_CFG) & MASTER_RESET) == 0)
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break;
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}
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if (i == 0)
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printf("%s: master reset timeout!\n", device_xname(sc->sc_dev));
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CSR_READ_4(sc, AGE_MASTER_CFG);
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DELAY(1000);
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for (i = AGE_RESET_TIMEOUT; i > 0; i--) {
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if ((reg = CSR_READ_4(sc, AGE_IDLE_STATUS)) == 0)
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break;
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