PR/49259: J. Lorec: Add support for Realtek 8111G chipset into re(4)
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@ -1,4 +1,4 @@
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/* $NetBSD: rtl8169.c,v 1.140 2014/08/10 16:44:35 tls Exp $ */
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/* $NetBSD: rtl8169.c,v 1.141 2014/10/10 17:41:05 christos Exp $ */
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/*
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* Copyright (c) 1997, 1998-2003
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@ -33,7 +33,7 @@
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*/
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#include <sys/cdefs.h>
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__KERNEL_RCSID(0, "$NetBSD: rtl8169.c,v 1.140 2014/08/10 16:44:35 tls Exp $");
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__KERNEL_RCSID(0, "$NetBSD: rtl8169.c,v 1.141 2014/10/10 17:41:05 christos Exp $");
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/* $FreeBSD: /repoman/r/ncvs/src/sys/dev/re/if_re.c,v 1.20 2004/04/11 20:34:08 ru Exp $ */
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/*
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@ -611,6 +611,14 @@ re_attach(struct rtk_softc *sc)
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sc->sc_quirk |= RTKQ_DESCV2 | RTKQ_NOEECMD |
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RTKQ_MACSTAT | RTKQ_CMDSTOP | RTKQ_NOJUMBO;
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break;
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case RTK_HWREV_8168G:
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case RTK_HWREV_8168G_SPIN1:
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case RTK_HWREV_8168G_SPIN2:
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case RTK_HWREV_8168G_SPIN4:
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sc->sc_quirk |= RTKQ_DESCV2 | RTKQ_NOEECMD |
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RTKQ_MACSTAT | RTKQ_CMDSTOP | RTKQ_NOJUMBO |
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RTKQ_RXDV_GATED;
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break;
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case RTK_HWREV_8100E:
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case RTK_HWREV_8100E_SPIN2:
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case RTK_HWREV_8101E:
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@ -1834,6 +1842,11 @@ re_init(struct ifnet *ifp)
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CSR_WRITE_4(sc, RTK_TXLIST_ADDR_LO,
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RE_ADDR_LO(sc->re_ldata.re_tx_list_map->dm_segs[0].ds_addr));
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if (sc->sc_quirk & RTKQ_RXDV_GATED) {
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CSR_WRITE_4(sc, RTK_MISC,
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CSR_READ_4(sc, RTK_MISC) & ~RTK_MISC_RXDV_GATED_EN);
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}
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/*
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* Enable transmit and receive.
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*/
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@ -1,4 +1,4 @@
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/* $NetBSD: rtl81x9reg.h,v 1.45 2013/12/13 20:52:48 jakllsch Exp $ */
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/* $NetBSD: rtl81x9reg.h,v 1.46 2014/10/10 17:41:05 christos Exp $ */
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/*
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* Copyright (c) 1997, 1998
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@ -136,6 +136,7 @@
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#define RTK_DBG_REG 0x00D1
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#define RTK_MAXRXPKTLEN 0x00DA /* 16 bits, chip multiplies by 8 */
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#define RTK_IM 0x00E2
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#define RTK_MISC 0x00F0
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/*
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* TX config register bits
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@ -165,6 +166,11 @@
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#define RTK_HWREV_8168E 0x2C000000
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#define RTK_HWREV_8168E_VL 0x2C800000
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#define RTK_HWREV_8168_SPIN1 0x30000000
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#define RTK_HWREV_8168G 0x4c000000
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#define RTK_HWREV_8168G_SPIN1 0x4c100000
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#define RTK_HWREV_8168G_SPIN2 0x50900000
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#define RTK_HWREV_8168G_SPIN4 0x5c800000
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#define RTK_HWREV_8168GU 0x50800000
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#define RTK_HWREV_8100E 0x30800000
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#define RTK_HWREV_8101E 0x34000000
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#define RTK_HWREV_8102E 0x34800000
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@ -214,6 +220,14 @@
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#define RTK_TXTH_256 8 /* (x) * 32 bytes */
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#define RTK_TXTH_1536 48
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/* MISC register */
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#define RTK_MISC_TXPLA_RST __BIT(29)
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#define RTK_MISC_DISABLE_LAN_EN __BIT(23) /* Enable GPIO pin */
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#define RTK_MISC_PWM_EN __BIT(22)
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#define RTK_MISC_RXDV_GATED_EN __BIT(19)
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#define RTK_MISC_EARLY_TALLY_EN __BIT(16)
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/*
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* Interrupt status register bits.
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*/
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@ -1,4 +1,4 @@
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/* $NetBSD: rtl81x9var.h,v 1.53 2012/02/02 19:43:03 tls Exp $ */
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/* $NetBSD: rtl81x9var.h,v 1.54 2014/10/10 17:41:05 christos Exp $ */
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/*
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* Copyright (c) 1997, 1998
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@ -192,6 +192,7 @@ struct rtk_softc {
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#define RTKQ_MACSTAT 0x00000100 /* set MACSTAT_DIS on init */
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#define RTKQ_CMDSTOP 0x00000200 /* set STOPREQ on stop */
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#define RTKQ_PHYWAKE_PM 0x00000400 /* wake PHY from power down */
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#define RTKQ_RXDV_GATED 0x00000800
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bus_dma_tag_t sc_dmat;
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