Assembly version of string functions.
Originally from SHIMIZU Ryo.
This commit is contained in:
itohy
parent
6e73936f81
commit
6cde54195b
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@ -1,6 +1,7 @@
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# $NetBSD: Makefile.inc,v 1.2 2002/08/24 06:39:48 itohy Exp $
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# $NetBSD: Makefile.inc,v 1.3 2002/11/20 14:23:54 itohy Exp $
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SRCS+= bcmp.c bcopy.c bzero.c ffs.S index.c memchr.c memcmp.c memset.c \
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SRCS+= bcmp.c bcopy.S bzero.S ffs.S index.c memchr.c memcmp.c memset.S \
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rindex.c strcat.c strcmp.c strcpy.c strcspn.c strlen.c \
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strncat.c strncmp.c strncpy.c strpbrk.c strsep.c \
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strspn.c strstr.c swab.c
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SRCS+= memcpy.S memmove.S
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@ -0,0 +1,269 @@
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/* $NetBSD: bcopy.S,v 1.1 2002/11/20 14:23:54 itohy Exp $ */
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/*
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* Copyright (c) 2000 SHIMIZU Ryo <ryo@misakimix.org>
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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||||
* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* 3. The name of the author may not be used to endorse or promote products
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* derived from this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
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||||
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
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||||
* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
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||||
* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
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* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
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* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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#include <machine/asm.h>
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#if defined(LIBC_SCCS) && !defined(lint)
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RCSID("$NetBSD: bcopy.S,v 1.1 2002/11/20 14:23:54 itohy Exp $")
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#endif
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#if defined(MEMCOPY) || defined(MEMMOVE)
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#define REG_DST0 r3
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#define REG_SRC r5
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#define REG_DST r4
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#else
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#define REG_SRC r4
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#define REG_DST r5
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#endif
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#define REG_LEN r6
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#ifdef MEMCOPY
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ENTRY(memcpy)
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#else
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#ifdef MEMMOVE
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ENTRY(memmove)
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#else
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ENTRY(bcopy)
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#endif
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#endif
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#ifdef REG_DST0
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mov REG_DST,REG_DST0
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#endif
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cmp/eq REG_DST,REG_SRC /* if ( src == dst ) return; */
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bt/s bcopy_return
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cmp/hi REG_DST,REG_SRC
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bf/s bcopy_overlap
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mov REG_SRC,r0
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xor REG_DST,r0
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and #3,r0
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mov r0,r1
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tst r0,r0 /* (src ^ dst) & 3 */
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bf/s word_align
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longword_align:
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tst REG_LEN,REG_LEN /* if ( len==0 ) return; */
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bt/s bcopy_return
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mov REG_SRC,r0
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tst #1,r0 /* if ( src & 1 ) */
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bt 1f
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mov.b @REG_SRC+,r0 /* *dst++ = *src++; */
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add #-1,REG_LEN
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mov.b r0,@REG_DST
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add #1,REG_DST
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1:
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mov #1,r0
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cmp/hi r0,REG_LEN /* if ( (len > 1) && */
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bf/s 1f
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mov REG_SRC,r0
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tst #2,r0 /* (src & 2) { */
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bt 1f
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mov.w @REG_SRC+,r0 /* *((unsigned short*)dst)++ = *((unsigned short*)src)++; */
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add #-2,REG_LEN /* len -= 2; */
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mov.w r0,@REG_DST
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add #2,REG_DST /* } */
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1:
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mov #3,r1
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cmp/hi r1,REG_LEN /* while ( len > 3 ) { */
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bf/s no_align_delay
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tst REG_LEN,REG_LEN
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2:
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mov.l @REG_SRC+,r0 /* *((unsigned long*)dst)++ = *((unsigned long*)src)++; */
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add #-4,REG_LEN /* len -= 4; */
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mov.l r0,@REG_DST
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cmp/hi r1,REG_LEN
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bt/s 2b
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add #4,REG_DST /* } */
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bra no_align_delay
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tst REG_LEN,REG_LEN
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word_align:
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mov r1,r0
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tst #1,r0
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bf/s no_align_delay
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tst REG_LEN,REG_LEN /* if ( len == 0 ) return; */
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bt bcopy_return
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mov REG_SRC,r0 /* if ( src & 1 ) */
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tst #1,r0
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bt 1f
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mov.b @REG_SRC+,r0 /* *dst++ = *src++; */
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add #-1,REG_LEN
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mov.b r0,@REG_DST
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add #1,REG_DST
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1:
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mov #1,r1
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cmp/hi r1,REG_LEN /* while ( len > 1 ) { */
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bf/s no_align_delay
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tst REG_LEN,REG_LEN
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2:
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mov.w @REG_SRC+,r0 /* *((unsigned short*)dst)++ = *((unsigned short*)src)++; */
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add #-2,REG_LEN /* len -= 2; */
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mov.w r0,@REG_DST
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cmp/hi r1,REG_LEN
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bt/s 2b
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add #2,REG_DST /* } */
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no_align:
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tst REG_LEN,REG_LEN /* while ( len!= ) { */
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no_align_delay:
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bt bcopy_return
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1:
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mov.b @REG_SRC+,r0 /* *dst++ = *src++; */
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add #-1,REG_LEN /* len--; */
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mov.b r0,@REG_DST
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tst REG_LEN,REG_LEN
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bf/s 1b
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add #1,REG_DST /* } */
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bcopy_return:
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rts
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#ifdef REG_DST0
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mov REG_DST0,r0
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#else
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nop
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#endif
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bcopy_overlap:
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add REG_LEN,REG_SRC
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add REG_LEN,REG_DST
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mov REG_SRC,r0
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xor REG_DST,r0
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and #3,r0
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mov r0,r1
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tst r0,r0 /* (src ^ dst) & 3 */
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bf/s ov_word_align
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ov_longword_align:
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tst REG_LEN,REG_LEN /* if ( len==0 ) return; */
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bt/s bcopy_return
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mov REG_SRC,r0
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tst #1,r0 /* if ( src & 1 ) */
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bt 1f
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add #-1,REG_SRC /* *--dst = *--src; */
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mov.b @REG_SRC,r0
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mov.b r0,@-REG_DST
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add #-1,REG_LEN
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1:
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mov #1,r0
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cmp/hi r0,REG_LEN /* if ( (len > 1) && */
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bf/s 1f
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mov REG_SRC,r0
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tst #2,r0 /* (src & 2) { */
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bt 1f
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add #-2,REG_SRC /* *--((unsigned short*)dst) = *--((unsigned short*)src); */
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mov.w @REG_SRC,r0
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add #-2,REG_LEN /* len -= 2; */
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mov.w r0,@-REG_DST /* } */
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1:
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mov #3,r1
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cmp/hi r1,REG_LEN /* while ( len > 3 ) { */
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bf/s ov_no_align_delay
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tst REG_LEN,REG_LEN
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2:
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add #-4,REG_SRC
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mov.l @REG_SRC,r0 /* *((unsigned long*)dst)++ = *((unsigned long*)src)++; */
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add #-4,REG_LEN /* len -= 4; */
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cmp/hi r1,REG_LEN
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bt/s 2b
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mov.l r0,@-REG_DST /* } */
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bra ov_no_align_delay
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tst REG_LEN,REG_LEN
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ov_word_align:
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mov r1,r0
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tst #1,r0
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bf/s ov_no_align_delay
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tst REG_LEN,REG_LEN /* if ( len == 0 ) return; */
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bt bcopy_return
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mov REG_SRC,r0 /* if ( src & 1 ) */
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tst #1,r0
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bt 1f
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add #-1,REG_SRC
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mov.b @REG_SRC,r0 /* *--dst = *--src; */
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add #-1,REG_LEN
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mov.b r0,@-REG_DST
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1:
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mov #1,r1
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cmp/hi r1,REG_LEN /* while ( len > 1 ) { */
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bf/s ov_no_align_delay
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tst REG_LEN,REG_LEN
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2:
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add #-2,REG_SRC
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mov.w @REG_SRC,r0 /* *--((unsigned short*)dst) = *--((unsigned short*)src); */
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add #-2,REG_LEN /* len -= 2; */
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cmp/hi r1,REG_LEN
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bt/s 2b
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mov.w r0,@-REG_DST /* } */
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ov_no_align:
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tst REG_LEN,REG_LEN /* while ( len!= ) { */
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ov_no_align_delay:
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bt 9f
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1:
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add #-1,REG_SRC
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mov.b @REG_SRC,r0 /* *--dst = *--src; */
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add #-1,REG_LEN /* len--; */
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tst REG_LEN,REG_LEN
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bf/s 1b
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mov.b r0,@-REG_DST /* } */
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9:
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rts
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#ifdef REG_DST0
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mov REG_DST0,r0
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#else
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nop
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#endif
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@ -0,0 +1,5 @@
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/* $NetBSD: bzero.S,v 1.1 2002/11/20 14:23:54 itohy Exp $ */
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#define BZERO
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#include "memset.S"
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@ -0,0 +1,4 @@
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/* $NetBSD: memcpy.S,v 1.1 2002/11/20 14:23:54 itohy Exp $ */
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#define MEMCOPY
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#include "bcopy.S"
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@ -0,0 +1,4 @@
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/* $NetBSD: memmove.S,v 1.1 2002/11/20 14:23:54 itohy Exp $ */
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#define MEMMOVE
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#include "bcopy.S"
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@ -0,0 +1,298 @@
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/* $NetBSD: memset.S,v 1.1 2002/11/20 14:23:54 itohy Exp $ */
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/*-
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* Copyright (c) 2002 SHIMIZU Ryo. All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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||||
* are met:
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||||
* 1. Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in the
|
||||
* documentation and/or other materials provided with the distribution.
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||||
* 3. The name of the author may not be used to endorse or promote products
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||||
* derived from this software without specific prior written permission.
|
||||
*
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||||
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
|
||||
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
|
||||
* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
|
||||
* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
|
||||
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
|
||||
* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
|
||||
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
|
||||
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
||||
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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#include <machine/asm.h>
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#if defined(LIBC_SCCS) && !defined(lint)
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RCSID("$NetBSD: memset.S,v 1.1 2002/11/20 14:23:54 itohy Exp $")
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#endif
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#define REG_PTR r0
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#define REG_TMP1 r1
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#ifdef BZERO
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# define REG_C r2
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# define REG_DST r4
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# define REG_LEN r5
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#else
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# define REG_DST0 r3
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# define REG_DST r4
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# define REG_C r5
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# define REG_LEN r6
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#endif
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#ifdef BZERO
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ENTRY(bzero)
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#else
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ENTRY(memset)
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mov REG_DST,REG_DST0 /* for return value */
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#endif
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/* small amount to fill ? */
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mov #28,REG_TMP1
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cmp/hs REG_TMP1,REG_LEN /* if (len >= 28) goto large; */
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bt/s large
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mov #12,REG_TMP1 /* if (len >= 12) goto small; */
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cmp/hs REG_TMP1,REG_LEN
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bt/s small
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#ifdef BZERO
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mov #0,REG_C
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#endif
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/* very little fill (0 ~ 11 bytes) */
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tst REG_LEN,REG_LEN
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add REG_DST,REG_LEN
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bt/s done
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add #1,REG_DST
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/* unroll 4 loops */
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cmp/eq REG_DST,REG_LEN
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1: mov.b REG_C,@-REG_LEN
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bt/s done
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cmp/eq REG_DST,REG_LEN
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mov.b REG_C,@-REG_LEN
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bt/s done
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cmp/eq REG_DST,REG_LEN
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mov.b REG_C,@-REG_LEN
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bt/s done
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cmp/eq REG_DST,REG_LEN
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mov.b REG_C,@-REG_LEN
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bf/s 1b
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cmp/eq REG_DST,REG_LEN
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done:
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#ifdef BZERO
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rts
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nop
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#else
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rts
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mov REG_DST0,r0
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#endif
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small:
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mov REG_DST,r0
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tst #1,r0
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bt/s small_aligned
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mov REG_DST,REG_TMP1
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shll REG_LEN
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mova 1f,r0 /* 1f must be 4bytes aligned! */
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add #16,REG_TMP1 /* REG_TMP1 = dst+16; */
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sub REG_LEN,r0
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jmp @r0
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mov REG_C,r0
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.align 2
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mov.b r0,@(15,REG_TMP1)
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mov.b r0,@(14,REG_TMP1)
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mov.b r0,@(13,REG_TMP1)
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mov.b r0,@(12,REG_TMP1)
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mov.b r0,@(11,REG_TMP1)
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mov.b r0,@(10,REG_TMP1)
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mov.b r0,@(9,REG_TMP1)
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mov.b r0,@(8,REG_TMP1)
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mov.b r0,@(7,REG_TMP1)
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mov.b r0,@(6,REG_TMP1)
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mov.b r0,@(5,REG_TMP1)
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mov.b r0,@(4,REG_TMP1)
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mov.b r0,@(3,REG_TMP1)
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mov.b r0,@(2,REG_TMP1)
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mov.b r0,@(1,REG_TMP1)
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mov.b r0,@REG_TMP1
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mov.b r0,@(15,REG_DST)
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mov.b r0,@(14,REG_DST)
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mov.b r0,@(13,REG_DST)
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mov.b r0,@(12,REG_DST)
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mov.b r0,@(11,REG_DST)
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mov.b r0,@(10,REG_DST)
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mov.b r0,@(9,REG_DST)
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mov.b r0,@(8,REG_DST)
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mov.b r0,@(7,REG_DST)
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mov.b r0,@(6,REG_DST)
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mov.b r0,@(5,REG_DST)
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mov.b r0,@(4,REG_DST)
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mov.b r0,@(3,REG_DST)
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mov.b r0,@(2,REG_DST)
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mov.b r0,@(1,REG_DST)
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#ifdef BZERO
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rts
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1: mov.b r0,@REG_DST
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#else
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mov.b r0,@REG_DST
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1: rts
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mov REG_DST0,r0
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#endif
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/* 2 bytes aligned small fill */
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small_aligned:
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#ifndef BZERO
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extu.b REG_C,REG_TMP1 /* REG_C = ??????xx, REG_TMP1 = ????00xx */
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shll8 REG_C /* REG_C = ????xx00, REG_TMP1 = ????00xx */
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or REG_TMP1,REG_C /* REG_C = ????xxxx */
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#endif
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mov REG_LEN,r0
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tst #1,r0 /* len is aligned? */
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bt/s 1f
|
||||
add #-1,r0
|
||||
mov.b REG_C,@(r0,REG_DST) /* fill last a byte */
|
||||
mov r0,REG_LEN
|
||||
1:
|
||||
|
||||
mova 1f,r0 /* 1f must be 4bytes aligned! */
|
||||
sub REG_LEN,r0
|
||||
jmp @r0
|
||||
mov REG_C,r0
|
||||
|
||||
.align 2
|
||||
mov.w r0,@(30,REG_DST)
|
||||
mov.w r0,@(28,REG_DST)
|
||||
mov.w r0,@(26,REG_DST)
|
||||
mov.w r0,@(24,REG_DST)
|
||||
mov.w r0,@(22,REG_DST)
|
||||
mov.w r0,@(20,REG_DST)
|
||||
mov.w r0,@(18,REG_DST)
|
||||
mov.w r0,@(16,REG_DST)
|
||||
mov.w r0,@(14,REG_DST)
|
||||
mov.w r0,@(12,REG_DST)
|
||||
mov.w r0,@(10,REG_DST)
|
||||
mov.w r0,@(8,REG_DST)
|
||||
mov.w r0,@(6,REG_DST)
|
||||
mov.w r0,@(4,REG_DST)
|
||||
mov.w r0,@(2,REG_DST)
|
||||
#ifdef BZERO
|
||||
rts
|
||||
1: mov.w r0,@REG_DST
|
||||
#else
|
||||
mov.w r0,@REG_DST
|
||||
1: rts
|
||||
mov REG_DST0,r0
|
||||
#endif
|
||||
|
||||
|
||||
|
||||
.align 2
|
||||
large:
|
||||
#ifdef BZERO
|
||||
mov #0,REG_C
|
||||
#else
|
||||
extu.b REG_C,REG_TMP1 /* REG_C = ??????xx, REG_TMP1 = ????00xx */
|
||||
shll8 REG_C /* REG_C = ????xx00, REG_TMP1 = ????00xx */
|
||||
or REG_C,REG_TMP1 /* REG_C = ????xx00, REG_TMP1 = ????xxxx */
|
||||
swap.w REG_TMP1,REG_C /* REG_C = xxxx????, REG_TMP1 = ????xxxx */
|
||||
xtrct REG_TMP1,REG_C /* REG_C = xxxxxxxx */
|
||||
#endif
|
||||
|
||||
mov #3,REG_TMP1
|
||||
tst REG_TMP1,REG_DST
|
||||
mov REG_DST,REG_PTR
|
||||
bf/s unaligned_dst
|
||||
add REG_LEN,REG_PTR /* REG_PTR = dst + len; */
|
||||
tst REG_TMP1,REG_LEN
|
||||
bf/s unaligned_len
|
||||
|
||||
aligned:
|
||||
/* fill 32*n bytes */
|
||||
mov #32,REG_TMP1
|
||||
cmp/hi REG_LEN,REG_TMP1
|
||||
bt 9f
|
||||
.align 2
|
||||
1: sub REG_TMP1,REG_PTR
|
||||
mov.l REG_C,@REG_PTR
|
||||
sub REG_TMP1,REG_LEN
|
||||
mov.l REG_C,@(4,REG_PTR)
|
||||
cmp/hi REG_LEN,REG_TMP1
|
||||
mov.l REG_C,@(8,REG_PTR)
|
||||
mov.l REG_C,@(12,REG_PTR)
|
||||
mov.l REG_C,@(16,REG_PTR)
|
||||
mov.l REG_C,@(20,REG_PTR)
|
||||
mov.l REG_C,@(24,REG_PTR)
|
||||
bf/s 1b
|
||||
mov.l REG_C,@(28,REG_PTR)
|
||||
9:
|
||||
|
||||
/* fill left 4*n bytes */
|
||||
cmp/eq REG_DST,REG_PTR
|
||||
bt 9f
|
||||
add #4,REG_DST
|
||||
cmp/eq REG_DST,REG_PTR
|
||||
1: mov.l REG_C,@-REG_PTR
|
||||
bt/s 9f
|
||||
cmp/eq REG_DST,REG_PTR
|
||||
mov.l REG_C,@-REG_PTR
|
||||
bt/s 9f
|
||||
cmp/eq REG_DST,REG_PTR
|
||||
mov.l REG_C,@-REG_PTR
|
||||
bt/s 9f
|
||||
cmp/eq REG_DST,REG_PTR
|
||||
mov.l REG_C,@-REG_PTR
|
||||
bf/s 1b
|
||||
cmp/eq REG_DST,REG_PTR
|
||||
9:
|
||||
#ifdef BZERO
|
||||
rts
|
||||
nop
|
||||
#else
|
||||
rts
|
||||
mov REG_DST0,r0
|
||||
#endif
|
||||
|
||||
|
||||
unaligned_dst:
|
||||
mov #1,REG_TMP1
|
||||
tst REG_TMP1,REG_DST /* if (dst & 1) { */
|
||||
add #1,REG_TMP1
|
||||
bt/s 2f
|
||||
tst REG_TMP1,REG_DST
|
||||
mov.b REG_C,@REG_DST /* *dst++ = c; */
|
||||
add #1,REG_DST
|
||||
tst REG_TMP1,REG_DST
|
||||
2: /* } */
|
||||
/* if (dst & 2) { */
|
||||
bt 4f
|
||||
mov.w REG_C,@REG_DST /* *(u_int16_t*)dst++ = c; */
|
||||
add #2,REG_DST
|
||||
4: /* } */
|
||||
|
||||
|
||||
tst #3,REG_PTR /* if (ptr & 3) { */
|
||||
bt/s 4f /* */
|
||||
unaligned_len:
|
||||
tst #1,REG_PTR /* if (ptr & 1) { */
|
||||
bt/s 2f
|
||||
tst #2,REG_PTR
|
||||
mov.b REG_C,@-REG_PTR /* --ptr = c; */
|
||||
2: /* } */
|
||||
/* if (ptr & 2) { */
|
||||
bt 4f
|
||||
mov.w REG_C,@-REG_PTR /* *--(u_int16_t*)ptr = c; */
|
||||
4: /* } */
|
||||
/* } */
|
||||
|
||||
mov REG_PTR,REG_LEN
|
||||
bra aligned
|
||||
sub REG_DST,REG_LEN
|
||||
|
||||
Loading…
Reference in New Issue