improve interrupt response.
This commit is contained in:
uch
parent
b77ae95a9e
commit
6c1c0aff9c
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@ -1,4 +1,4 @@
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/* $NetBSD: interrupt.c,v 1.3 2001/09/15 19:51:38 uch Exp $ */
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/* $NetBSD: interrupt.c,v 1.4 2001/09/23 14:32:52 uch Exp $ */
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/*-
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* Copyright (c) 2001 The NetBSD Foundation, Inc.
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@ -44,97 +44,10 @@
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#include <uvm/uvm_extern.h>
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#include <machine/locore.h> /* mips3_cp0_*() */
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#include <machine/sysconf.h>
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#ifdef DEBUG
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#define STATIC
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#else
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#define STATIC static
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#endif
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#if defined(VR41XX) && defined(TX39XX)
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STATIC void (*__cpu_intr)(u_int32_t, u_int32_t, u_int32_t, u_int32_t);
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#define VR_INTR vr_intr
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#define TX_INTR tx_intr
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#elif defined(VR41XX)
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#define VR_INTR cpu_intr
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#elif defined(TX39XX)
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#define TX_INTR cpu_intr
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#endif
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/*
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* This is a mask of bits to clear in the SR when we go to a
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* given interrupt priority level.
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*/
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#ifdef VR41XX
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const u_int32_t __ipl_sr_bits_vr[_IPL_N] = {
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0, /* IPL_NONE */
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MIPS_SOFT_INT_MASK_0, /* IPL_SOFT */
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MIPS_SOFT_INT_MASK_0, /* IPL_SOFTCLOCK */
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MIPS_SOFT_INT_MASK_0|
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MIPS_SOFT_INT_MASK_1, /* IPL_SOFTNET */
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MIPS_SOFT_INT_MASK_0|
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MIPS_SOFT_INT_MASK_1, /* IPL_SOFTSERIAL */
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MIPS_SOFT_INT_MASK_0|
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MIPS_SOFT_INT_MASK_1|
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MIPS_INT_MASK_0, /* IPL_BIO */
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MIPS_SOFT_INT_MASK_0|
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MIPS_SOFT_INT_MASK_1|
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MIPS_INT_MASK_0, /* IPL_NET */
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MIPS_SOFT_INT_MASK_0|
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MIPS_SOFT_INT_MASK_1|
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MIPS_INT_MASK_0, /* IPL_{TTY,SERIAL} */
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MIPS_SOFT_INT_MASK_0|
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MIPS_SOFT_INT_MASK_1|
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MIPS_INT_MASK_0|
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MIPS_INT_MASK_1, /* IPL_{CLOCK,HIGH} */
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};
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#endif /* VR41XX */
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#ifdef TX39XX
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const u_int32_t __ipl_sr_bits_tx[_IPL_N] = {
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0, /* IPL_NONE */
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MIPS_SOFT_INT_MASK_0, /* IPL_SOFT */
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MIPS_SOFT_INT_MASK_0, /* IPL_SOFTCLOCK */
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MIPS_SOFT_INT_MASK_0|
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MIPS_SOFT_INT_MASK_1, /* IPL_SOFTNET */
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MIPS_SOFT_INT_MASK_0|
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MIPS_SOFT_INT_MASK_1, /* IPL_SOFTSERIAL */
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MIPS_SOFT_INT_MASK_0|
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MIPS_SOFT_INT_MASK_1|
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MIPS_INT_MASK_2|
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MIPS_INT_MASK_4, /* IPL_BIO */
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MIPS_SOFT_INT_MASK_0|
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MIPS_SOFT_INT_MASK_1|
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MIPS_INT_MASK_2|
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MIPS_INT_MASK_4, /* IPL_NET */
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MIPS_SOFT_INT_MASK_0|
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MIPS_SOFT_INT_MASK_1|
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MIPS_INT_MASK_2|
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MIPS_INT_MASK_4, /* IPL_{TTY,SERIAL} */
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MIPS_SOFT_INT_MASK_0|
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MIPS_SOFT_INT_MASK_1|
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MIPS_INT_MASK_2|
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MIPS_INT_MASK_4, /* IPL_{CLOCK,HIGH} */
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};
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#endif /* TX39XX */
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extern const u_int32_t __ipl_sr_bits_vr[];
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extern const u_int32_t __ipl_sr_bits_tx[];
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const u_int32_t ipl_si_to_sr[_IPL_NSOFT] = {
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MIPS_SOFT_INT_MASK_0, /* IPL_SOFT */
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@ -146,7 +59,6 @@ const u_int32_t ipl_si_to_sr[_IPL_NSOFT] = {
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const u_int32_t *ipl_sr_bits;
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struct hpcmips_soft_intrhand *softnet_intrhand;
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struct hpcmips_soft_intr hpcmips_soft_intrs[_IPL_NSOFT];
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STATIC void softintr(u_int32_t);
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void
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intr_init()
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@ -162,49 +74,22 @@ intr_init()
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}
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#if defined(VR41XX) && defined(TX39XX)
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/*
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* cpu_intr:
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*
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* handle MIPS CPU interrupt.
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* if VR41XX only or TX39XX only kernel, directly jump to each handler
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* (tx/tx39icu.c, vr/vr.c), don't use this dispather.
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*
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*/
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void
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cpu_intr(u_int32_t status, u_int32_t cause, u_int32_t pc, u_int32_t ipending)
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{
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(*__cpu_intr)(status, caust, pc, ipending);
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(*platform.cpu_intr)(status, cause, pc, ipending);
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}
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#endif /* VR41XX && TX39XX */
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#ifdef VR41XX
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void
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VR_INTR(u_int32_t status, u_int32_t cause, u_int32_t pc, u_int32_t ipending)
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{
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uvmexp.intrs++;
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if (ipending & MIPS_INT_MASK_5) {
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/*
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* Writing a value to the Compare register,
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* as a side effect, clears the timer
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* interrupt request.
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*/
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mips3_cp0_compare_write(mips3_cp0_count_read());
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}
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if (ipending & MIPS3_HARD_INT_MASK)
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_splset((*platform.iointr)(status, cause, pc, ipending));
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softintr(ipending);
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}
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#endif /* VR41XX */
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#ifdef TX39XX
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void
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TX_INTR(u_int32_t status, u_int32_t cause, u_int32_t pc, u_int32_t ipending)
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{
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uvmexp.intrs++;
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if (ipending & MIPS_HARD_INT_MASK)
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_splset((*platform.iointr)(status, cause, pc, ipending));
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softintr(ipending);
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}
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#endif /* TX39XX */
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/*
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* softintr:
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*
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@ -1,4 +1,4 @@
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/* $NetBSD: intr.h,v 1.14 2001/09/16 15:45:44 uch Exp $ */
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/* $NetBSD: intr.h,v 1.15 2001/09/23 14:32:52 uch Exp $ */
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/*
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* Copyright (c) 1998 Jonathan Stone. All rights reserved.
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@ -148,6 +148,7 @@ struct hpcmips_soft_intr {
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};
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void softintr_init(void);
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void softintr(u_int32_t);
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void *softintr_establish(int, void (*)(void *), void *);
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void softintr_disestablish(void *);
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void softintr_dispatch(void);
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@ -1,4 +1,4 @@
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/* $NetBSD: sysconf.h,v 1.10 2001/09/18 17:37:28 uch Exp $ */
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/* $NetBSD: sysconf.h,v 1.11 2001/09/23 14:32:52 uch Exp $ */
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/*
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* Copyright (c) 1996 Christopher G. Demetriou. All rights reserved.
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@ -54,17 +54,17 @@ struct clock_ymdhms;
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extern struct platform {
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/*
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* cpu_intr - interrupt handler
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* cpu_idle - CPU dependend idle routine.
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* cons_init - console initialization
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* iointr - I/O interrupt handler
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* fb_init - frame buffer initialization
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* mem_init - Count available memory
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* reboot - reboot or powerdown
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* clock -
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*/
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void (*cpu_intr)(u_int32_t, u_int32_t, u_int32_t, u_int32_t);
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void (*cpu_idle)(void);
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void (*cons_init)(void);
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int (*iointr)(u_int32_t, u_int32_t, u_int32_t, u_int32_t);
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void (*fb_init)(caddr_t*);
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void (*mem_init)(paddr_t);
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void (*reboot)(int, char *);
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@ -1,4 +1,4 @@
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/* $NetBSD: tx39.c,v 1.26 2001/09/17 17:03:45 uch Exp $ */
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/* $NetBSD: tx39.c,v 1.27 2001/09/23 14:32:53 uch Exp $ */
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/*-
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* Copyright (c) 1999, 2000 The NetBSD Foundation, Inc.
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@ -36,6 +36,8 @@
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* POSSIBILITY OF SUCH DAMAGE.
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*/
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#include "opt_vr41xx.h"
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#include "opt_tx39xx.h"
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#include "opt_tx39_debug.h"
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#include "m38813c.h"
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#include "tc5165buf.h"
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#endif
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void tx_init(void);
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int tx39icu_intr(u_int32_t, u_int32_t, u_int32_t, u_int32_t);
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#if defined(VR41XX) && defined(TX39XX)
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#define TX_INTR tx_intr
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#else
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#define TX_INTR cpu_intr /* locore_mips3 directly call this */
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#endif
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extern void TX_INTR(u_int32_t, u_int32_t, u_int32_t, u_int32_t);
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void tx39clock_cpuspeed(int *, int *);
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/* TX39-specific initialization vector */
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void tx_mem_init(paddr_t);
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void tx_find_dram(paddr_t, paddr_t);
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void tx_reboot(int, char *);
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int tx_intr(u_int32_t, u_int32_t, u_int32_t, u_int32_t);
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void
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tx_init()
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/*
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* Platform Specific Function Hooks
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*/
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platform.cpu_intr = TX_INTR;
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platform.cpu_idle = NULL; /* not implemented yet */
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platform.cons_init = tx_cons_init;
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platform.fb_init = tx_fb_init;
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platform.mem_init = tx_mem_init;
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platform.reboot = tx_reboot;
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platform.iointr = tx39icu_intr;
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model = MIPS_PRID_REV(cpu_id);
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@ -1,7 +1,7 @@
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/* $NetBSD: tx39icu.c,v 1.13 2001/09/18 17:37:28 uch Exp $ */
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/* $NetBSD: tx39icu.c,v 1.14 2001/09/23 14:32:53 uch Exp $ */
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/*-
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* Copyright (c) 1999, 2000 The NetBSD Foundation, Inc.
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* Copyright (c) 1999-2001 The NetBSD Foundation, Inc.
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* All rights reserved.
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*
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* This code is derived from software contributed to The NetBSD Foundation
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@ -36,6 +36,9 @@
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* POSSIBILITY OF SUCH DAMAGE.
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*/
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#include "opt_vr41xx.h"
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#include "opt_tx39xx.h"
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#include "opt_tx39_debug.h"
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#include "opt_use_poll.h"
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#include "opt_tx39icudebug.h"
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@ -47,6 +50,8 @@
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#include <sys/malloc.h>
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#include <sys/queue.h>
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#include <uvm/uvm_extern.h>
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#include <mips/cpuregs.h>
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#include <machine/bus.h>
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@ -59,6 +64,12 @@
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#undef TX39ICUDEBUG_PRINT_PENDING_INTERRUPT /* For explorer. good luck! */
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#if defined(VR41XX) && defined(TX39XX)
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#define TX_INTR tx_intr
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#else
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#define TX_INTR cpu_intr /* locore_mips3 directly call this */
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#endif
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#ifdef TX39ICUDEBUG
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#define DPRINTF(arg) printf arg
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#else
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@ -66,6 +77,44 @@
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#endif
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u_int32_t tx39intrvec;
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/*
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* This is a mask of bits to clear in the SR when we go to a
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* given interrupt priority level.
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*/
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const u_int32_t __ipl_sr_bits_tx[_IPL_N] = {
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0, /* IPL_NONE */
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MIPS_SOFT_INT_MASK_0, /* IPL_SOFT */
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MIPS_SOFT_INT_MASK_0, /* IPL_SOFTCLOCK */
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MIPS_SOFT_INT_MASK_0|
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MIPS_SOFT_INT_MASK_1, /* IPL_SOFTNET */
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MIPS_SOFT_INT_MASK_0|
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MIPS_SOFT_INT_MASK_1, /* IPL_SOFTSERIAL */
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MIPS_SOFT_INT_MASK_0|
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MIPS_SOFT_INT_MASK_1|
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MIPS_INT_MASK_2|
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MIPS_INT_MASK_4, /* IPL_BIO */
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MIPS_SOFT_INT_MASK_0|
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MIPS_SOFT_INT_MASK_1|
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MIPS_INT_MASK_2|
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MIPS_INT_MASK_4, /* IPL_NET */
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MIPS_SOFT_INT_MASK_0|
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MIPS_SOFT_INT_MASK_1|
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MIPS_INT_MASK_2|
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MIPS_INT_MASK_4, /* IPL_{TTY,SERIAL} */
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MIPS_SOFT_INT_MASK_0|
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MIPS_SOFT_INT_MASK_1|
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MIPS_INT_MASK_2|
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MIPS_INT_MASK_4, /* IPL_{CLOCK,HIGH} */
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};
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/* IRQHIGH lines list */
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static const struct irqhigh_list {
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int qh_pri; /* IRQHIGH priority */
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@ -179,13 +228,14 @@ void tx39_irqhigh_intr(u_int32_t, u_int32_t, u_int32_t, u_int32_t);
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int tx39_irqhigh(int, int);
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struct cfattach tx39icu_ca = {
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sizeof(struct tx39icu_softc), tx39icu_match, tx39icu_attach
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sizeof(struct tx39icu_softc), tx39icu_match, tx39icu_attach
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};
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int
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tx39icu_match(struct device *parent, struct cfdata *cf, void *aux)
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{
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return (ATTACH_FIRST);
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return (ATTACH_FIRST);
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}
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void
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@ -196,7 +246,7 @@ tx39icu_attach(struct device *parent, struct device *self, void *aux)
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tx_chipset_tag_t tc = ta->ta_tc;
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txreg_t reg, *regs;
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int i;
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printf("\n");
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sc->sc_tc = ta->ta_tc;
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@ -272,15 +322,19 @@ tx39icu_attach(struct device *parent, struct device *self, void *aux)
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tx_conf_register_intr(tc, self);
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}
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int
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tx39icu_intr(u_int32_t status, u_int32_t cause, u_int32_t pc,
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u_int32_t ipending)
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void
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TX_INTR(u_int32_t status, u_int32_t cause, u_int32_t pc, u_int32_t ipending)
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{
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struct tx39icu_softc *sc;
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tx_chipset_tag_t tc;
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txreg_t reg, pend, *regs;
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int i, j;
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uvmexp.intrs++;
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if ((ipending & MIPS_HARD_INT_MASK) == 0)
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goto softintr;
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tc = tx_conf_get_tag();
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sc = tc->tc_intrt;
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/*
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@ -314,7 +368,7 @@ tx39icu_intr(u_int32_t status, u_int32_t cause, u_int32_t pc,
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if (ipending & MIPS_INT_MASK_4) {
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tx39_irqhigh_intr(ipending, pc, status, cause);
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return (0);
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goto softintr;
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}
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/* IRQLOW */
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@ -371,7 +425,11 @@ tx39icu_intr(u_int32_t status, u_int32_t cause, u_int32_t pc,
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reg = TX39_INTRENABLE6_PRIORITYMASK_SET(reg, 0xffff);
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tx_conf_write(tc, TX39_INTRENABLE6_REG, reg);
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#endif
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return (MIPS_SR_INT_IE | (status & ~cause & MIPS_HARD_INT_MASK));
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softintr:
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_splset((status & ~cause & MIPS_HARD_INT_MASK) | MIPS_SR_INT_IE);
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softintr(ipending);
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}
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int
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@ -1,7 +1,7 @@
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/* $NetBSD: vr.c,v 1.30 2001/09/17 17:03:46 uch Exp $ */
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/* $NetBSD: vr.c,v 1.31 2001/09/23 14:32:53 uch Exp $ */
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/*-
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* Copyright (c) 1999
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* Copyright (c) 1999-2001
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* Shin Takemura and PocketBSD Project. All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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@ -35,12 +35,15 @@
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*/
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||||
#include "opt_vr41xx.h"
|
||||
#include "opt_tx39xx.h"
|
||||
#include "opt_kgdb.h"
|
||||
|
||||
#include <sys/param.h>
|
||||
#include <sys/systm.h>
|
||||
#include <sys/reboot.h>
|
||||
|
||||
#include <uvm/uvm_extern.h>
|
||||
|
||||
#include <machine/sysconf.h>
|
||||
#include <machine/bus.h>
|
||||
#include <machine/bootinfo.h>
|
||||
|
|
@ -99,27 +102,74 @@
|
|||
#include <arch/hpcmips/vr/vrkiuvar.h>
|
||||
#endif
|
||||
|
||||
void vr_init(void);
|
||||
int vr_intr(u_int32_t, u_int32_t, u_int32_t, u_int32_t);
|
||||
void vr_cons_init(void);
|
||||
void vr_fb_init(caddr_t *);
|
||||
void vr_mem_init(paddr_t);
|
||||
void vr_find_dram(paddr_t, paddr_t);
|
||||
void vr_reboot(int, char *);
|
||||
void vr_idle(void);
|
||||
#ifdef DEBUG
|
||||
#define STATIC
|
||||
#else
|
||||
#define STATIC static
|
||||
#endif
|
||||
|
||||
/*
|
||||
* This is a mask of bits to clear in the SR when we go to a
|
||||
* given interrupt priority level.
|
||||
*/
|
||||
const u_int32_t __ipl_sr_bits_vr[_IPL_N] = {
|
||||
0, /* IPL_NONE */
|
||||
|
||||
MIPS_SOFT_INT_MASK_0, /* IPL_SOFT */
|
||||
|
||||
MIPS_SOFT_INT_MASK_0, /* IPL_SOFTCLOCK */
|
||||
|
||||
MIPS_SOFT_INT_MASK_0|
|
||||
MIPS_SOFT_INT_MASK_1, /* IPL_SOFTNET */
|
||||
|
||||
MIPS_SOFT_INT_MASK_0|
|
||||
MIPS_SOFT_INT_MASK_1, /* IPL_SOFTSERIAL */
|
||||
|
||||
MIPS_SOFT_INT_MASK_0|
|
||||
MIPS_SOFT_INT_MASK_1|
|
||||
MIPS_INT_MASK_0, /* IPL_BIO */
|
||||
|
||||
MIPS_SOFT_INT_MASK_0|
|
||||
MIPS_SOFT_INT_MASK_1|
|
||||
MIPS_INT_MASK_0, /* IPL_NET */
|
||||
|
||||
MIPS_SOFT_INT_MASK_0|
|
||||
MIPS_SOFT_INT_MASK_1|
|
||||
MIPS_INT_MASK_0, /* IPL_{TTY,SERIAL} */
|
||||
|
||||
MIPS_SOFT_INT_MASK_0|
|
||||
MIPS_SOFT_INT_MASK_1|
|
||||
MIPS_INT_MASK_0|
|
||||
MIPS_INT_MASK_1, /* IPL_{CLOCK,HIGH} */
|
||||
};
|
||||
|
||||
#if defined(VR41XX) && defined(TX39XX)
|
||||
#define VR_INTR vr_intr
|
||||
#else
|
||||
#define VR_INTR cpu_intr /* locore_mips3 directly call this */
|
||||
#endif
|
||||
|
||||
void vr_init(void);
|
||||
void VR_INTR(u_int32_t, u_int32_t, u_int32_t, u_int32_t);
|
||||
extern void vr_idle(void);
|
||||
STATIC void vr_cons_init(void);
|
||||
STATIC void vr_fb_init(caddr_t *);
|
||||
STATIC void vr_mem_init(paddr_t);
|
||||
STATIC void vr_find_dram(paddr_t, paddr_t);
|
||||
STATIC void vr_reboot(int, char *);
|
||||
|
||||
/*
|
||||
* CPU interrupt dispatch table (HwInt[0:3])
|
||||
*/
|
||||
int null_handler(void *, u_int32_t, u_int32_t);
|
||||
static int (*intr_handler[4])(void*, u_int32_t, u_int32_t) =
|
||||
STATIC int vr_null_handler(void *, u_int32_t, u_int32_t);
|
||||
STATIC int (*vr_intr_handler[4])(void *, u_int32_t, u_int32_t) =
|
||||
{
|
||||
null_handler,
|
||||
null_handler,
|
||||
null_handler,
|
||||
null_handler
|
||||
vr_null_handler,
|
||||
vr_null_handler,
|
||||
vr_null_handler,
|
||||
vr_null_handler
|
||||
};
|
||||
static void *intr_arg[4];
|
||||
STATIC void *vr_intr_arg[4];
|
||||
|
||||
void
|
||||
vr_init()
|
||||
|
|
@ -128,7 +178,7 @@ vr_init()
|
|||
* Platform Specific Function Hooks
|
||||
*/
|
||||
platform.cpu_idle = vr_idle;
|
||||
platform.iointr = vr_intr;
|
||||
platform.cpu_intr = VR_INTR;
|
||||
platform.cons_init = vr_cons_init;
|
||||
platform.fb_init = vr_fb_init;
|
||||
platform.mem_init = vr_mem_init;
|
||||
|
|
@ -175,7 +225,7 @@ vr_find_dram(paddr_t addr, paddr_t end)
|
|||
#ifdef VR_FIND_DRAMLIM
|
||||
if (VR_FIND_DRAMLIM < end)
|
||||
end = VR_FIND_DRAMLIM;
|
||||
#endif
|
||||
#endif /* VR_FIND_DRAMLIM */
|
||||
n = mem_cluster_cnt;
|
||||
for (; addr < end; addr += NBPG) {
|
||||
|
||||
|
|
@ -215,7 +265,7 @@ vr_find_dram(paddr_t addr, paddr_t end)
|
|||
for (i = 0; i < NBPG; i += 4)
|
||||
if (*(volatile int *)(page+i) != (x ^ i))
|
||||
goto bad;
|
||||
#endif
|
||||
#endif /* NARLY_MEMORY_PROBE */
|
||||
|
||||
if (!mem_clusters[n].size)
|
||||
mem_clusters[n].start = addr;
|
||||
|
|
@ -339,15 +389,38 @@ vr_reboot(int howto, char *bootstr)
|
|||
/*
|
||||
* Handle interrupts.
|
||||
*/
|
||||
int
|
||||
vr_intr(u_int32_t status, u_int32_t cause, u_int32_t pc, u_int32_t ipending)
|
||||
void
|
||||
VR_INTR(u_int32_t status, u_int32_t cause, u_int32_t pc, u_int32_t ipending)
|
||||
{
|
||||
int hwintr;
|
||||
uvmexp.intrs++;
|
||||
|
||||
hwintr = (ffs(ipending >> 10) -1) & 0x3;
|
||||
(*intr_handler[hwintr])(intr_arg[hwintr], pc, status);
|
||||
|
||||
return (MIPS_SR_INT_IE | (status & ~cause & MIPS_HARD_INT_MASK));
|
||||
if (ipending & MIPS_INT_MASK_5) {
|
||||
/*
|
||||
* spl* uses MIPS_INT_MASK not MIPS3_INT_MASK. it causes
|
||||
* INT5 interrupt.
|
||||
*/
|
||||
mips3_cp0_compare_write(mips3_cp0_count_read());
|
||||
}
|
||||
|
||||
/* for spllowersoftclock */
|
||||
_splset(((status & ~cause) & MIPS_HARD_INT_MASK) | MIPS_SR_INT_IE);
|
||||
|
||||
if (ipending & MIPS_INT_MASK_1) {
|
||||
(*vr_intr_handler[1])(vr_intr_arg[1], pc, status);
|
||||
|
||||
cause &= ~MIPS_INT_MASK_1;
|
||||
_splset(((status & ~cause) & MIPS_HARD_INT_MASK)
|
||||
| MIPS_SR_INT_IE);
|
||||
}
|
||||
|
||||
if (ipending & MIPS_INT_MASK_0) {
|
||||
(*vr_intr_handler[0])(vr_intr_arg[0], pc, status);
|
||||
|
||||
cause &= ~MIPS_INT_MASK_0;
|
||||
}
|
||||
_splset(((status & ~cause) & MIPS_HARD_INT_MASK) | MIPS_SR_INT_IE);
|
||||
|
||||
softintr(ipending);
|
||||
}
|
||||
|
||||
void *
|
||||
|
|
@ -355,30 +428,28 @@ vr_intr_establish(int line, int (*ih_fun)(void *, u_int32_t, u_int32_t),
|
|||
void *ih_arg)
|
||||
{
|
||||
|
||||
if (intr_handler[line] != null_handler) {
|
||||
panic("vr_intr_establish:"
|
||||
" can't establish duplicated intr handler.");
|
||||
}
|
||||
intr_handler[line] = ih_fun;
|
||||
intr_arg[line] = ih_arg;
|
||||
KDASSERT(vr_intr_handler[line] == vr_null_handler);
|
||||
|
||||
return ((void*)line);
|
||||
vr_intr_handler[line] = ih_fun;
|
||||
vr_intr_arg[line] = ih_arg;
|
||||
|
||||
return ((void *)line);
|
||||
}
|
||||
|
||||
|
||||
void
|
||||
vr_intr_disestablish(void *ih)
|
||||
{
|
||||
int line = (int)ih;
|
||||
|
||||
intr_handler[line] = null_handler;
|
||||
intr_arg[line] = NULL;
|
||||
vr_intr_handler[line] = vr_null_handler;
|
||||
vr_intr_arg[line] = NULL;
|
||||
}
|
||||
|
||||
int
|
||||
null_handler(void *arg, u_int32_t pc, u_int32_t statusReg)
|
||||
vr_null_handler(void *arg, u_int32_t pc, u_int32_t status)
|
||||
{
|
||||
printf("null_handler\n");
|
||||
|
||||
printf("vr_null_handler\n");
|
||||
|
||||
return (0);
|
||||
}
|
||||
|
|
|
|||
Loading…
Reference in New Issue