From 6a298274ec3f4f89292cbc46eea49bf25b264206 Mon Sep 17 00:00:00 2001 From: garbled Date: Mon, 29 May 2006 22:11:15 +0000 Subject: [PATCH] Add code to decode small vendor items that are documented. Namely we can now decode the chipid, and L2 processor affinity data. Also fix a bug where we were reporting the service processor type as a memory controller. --- sys/arch/prep/include/chpidpnp.h | 145 +++++++++++++++++++++++++++++++ sys/arch/prep/prep/residual.c | 129 ++++++++++++++++++++++----- 2 files changed, 252 insertions(+), 22 deletions(-) create mode 100644 sys/arch/prep/include/chpidpnp.h diff --git a/sys/arch/prep/include/chpidpnp.h b/sys/arch/prep/include/chpidpnp.h new file mode 100644 index 000000000000..efc08b64c772 --- /dev/null +++ b/sys/arch/prep/include/chpidpnp.h @@ -0,0 +1,145 @@ +/* $NetBSD: chpidpnp.h,v 1.1 2006/05/29 22:11:15 garbled Exp $ */ +/*- + * Copyright (c) 2006 The NetBSD Foundation, Inc. + * All rights reserved. + * + * This code is derived from software contributed to The NetBSD Foundation + * by Tim Rightnour + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * 3. All advertising materials mentioning features or use of this software + * must display the following acknowledgement: + * This product includes software developed by the NetBSD + * Foundation, Inc. and its contributors. + * 4. Neither the name of The NetBSD Foundation nor the names of its + * contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS + * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED + * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS + * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +/* + * Based on: + * IBM Power Personal Systems Architecture: Residual Data + * Document Number: PPS-AR-FW0001 Rev 0.5 April 3, 1996 + */ + +#ifndef _CHPIDPNP_H_ +#define _CHPIDPNP_H_ + +#define ChipID_Packet 0x70 /* tag for ChipIdPack without size */ + +/* + * The chipid is the vendor id followed by 4 hex digits, e.g. for IBM + * platforms: Chip_ID=IBMxxxx. To avoid confusion with PnP Device IDs, IBM + * Chip IDs will begin at 0x8000. + */ +typedef enum _Chip_Type { + Chip_MemCont = 0, + Chip_ISABridge = 1, + Chip_PCIBridge = 2, + Chip_PCMCIABridge = 3, + Chip_EISABridge = 4, + Chip_MCABridge = 5, + Chip_L2Cache = 6, + Chip_PM = 7, + Chip_IntrCont = 8, + Chip_MiscPlanar = 9, +} Chip_Type; + +typedef enum _Chip_ID { + +/* Memory Controllers Memory Controller range: IBM80xx */ +Dakota = 0x8001, /* IBM8001: IBM North/South Dakota */ +Idaho = 0x8002, /* IBM8002: IBM Idaho */ +Eagle = 0x8003, /* IBM8003: Motorola Eagle */ +Kauai_Lanai = 0x8004, /* IBM8004: IBM Kauai/Lanai */ +Montana_Nevada = 0x8005, /* IBM8005: IBM Montana/Nevada */ +Union = 0x8006, /* IBM8006: IBM Union */ +Cobra_Viper = 0x8007, /* IBM8007: IBM Cobra/Viper */ +Grackle = 0x8008, /* IBM8008: Motorola Grackle */ + +/* ISA Bridge chips Bus Bridge Range: IBM81xx */ +SIO_ZB = 0x8100, /* IBM8100: Intel 82378ZB */ +FireCoral = 0x8101, /* IBM8101: IBM FireCoral */ + +/* PCI Bridge chips */ +Python = 0x8102, /* IBM8102: IBM Python */ +DEC21050 = 0x8102, /* IBM8103: PCI-PCI (dec 21050) */ +IBM2782351 = 0x8106, /* IBM8106: PCI-PCI */ +IBM2782352 = 0x8109, /* IBM8109: PCI-PCI352 */ + +/* PCMCIA Bridge Chips */ +INTEL_8236SL = 0x8104, /* IBM8104: Intel 8236SL */ +RICOH_RF5C366C = 0x8105, /* IBM8105: RICOH RF5C366C */ + +/* EISA Bridge Chips */ +INTEL_82374 = 0x8108, /* IBM8108: Intel 82374/82375 */ + +/* MCA Bridge Chips */ +MCACoral = 0x8107, /* IBM8107: 6xxxMx - T=1 MCA (servers) */ + +/* L2 Cache controller L2 Controller Range: IBM82xx */ +Cheyenne = 0x8200, /* IBM8200: IBM Cheyenne */ +IDT = 0x8201, /* IBM8201: IDT */ +Sony1PB = 0x8202, /* IBM8202: Sony1PB */ +Mamba = 0x8203, /* IBM8203: IBM Mamba */ +Alaska = 0x8204, /* IBM8204: IBM Alaska */ +Glance = 0x8205, /* IBM8205: IBM Glance */ +Ocelot = 0x8206, /* IBM8206: IBM Ocelot */ + +/* Power management chips PM Range: IBM83xx */ +Carrera = 0x8300, /* IBM8300: IBM Carrera */ +Sig750 = 0x8301, /* IBM8301: Signetics 87C750 */ + +/* Interrupt controller chips PIC Chip range: IBM84xx */ +MPIC_2 = 0x8400, /* IBM8400: IBM MPIC-2 */ + +/* Miscellaneous Planar chips MISC Chip Range: IBM8Fxx */ +DallasRTC = 0x8F00, /* IBM8F00: Dallas 1385 compatible */ +Dallas1585 = 0x8F01, /* IBM8F01: Dallas 1585 compatible */ +Timer8254 = 0x8F10, /* IBM8F10: 8254-compatible timer */ +HarddiskLt = 0x8FF0, /* IBM8FF0: Op Panel HD light */ +} Chip_ID; + +/* small tag = 0x7n with n bytes. Type == 1 for ChipID + * VendorID0: + * bit(7) = 0 + * bits(6:2) 1st character in compressed ASCII + * bits(1:0) 2nd character in compressed ASCII bits(4:3) + * VendorID1: + * bits(7:5) 2nd character in compressed ASCII bits(2:0) + * bits(4:0) 3rd character in compressed ASCII + * Name: + * Example: IBM8001 + * I,B,M = 01001, 00010, 01101 + * bytes 0,1 = 00100100,01001101 + * = 2 4 4 D + * byte0 = 24 byte1 = 4D byte2 = 01 byte3 = 80 + */ +typedef struct _ChipIDPack { + unsigned char Tag; + unsigned char Type; + unsigned char VendorID0; + unsigned char VendorID1; + unsigned char Name[2]; +} ChipIDPack; + +#endif /* _CHPIDPNP_H_ */ diff --git a/sys/arch/prep/prep/residual.c b/sys/arch/prep/prep/residual.c index 77ac9166b72c..9d69bfdbffbe 100644 --- a/sys/arch/prep/prep/residual.c +++ b/sys/arch/prep/prep/residual.c @@ -1,4 +1,4 @@ -/* $NetBSD: residual.c,v 1.11 2006/05/25 02:11:13 garbled Exp $ */ +/* $NetBSD: residual.c,v 1.12 2006/05/29 22:11:15 garbled Exp $ */ /*- * Copyright (c) 2002 The NetBSD Foundation, Inc. @@ -37,7 +37,7 @@ */ #include -__KERNEL_RCSID(0, "$NetBSD: residual.c,v 1.11 2006/05/25 02:11:13 garbled Exp $"); +__KERNEL_RCSID(0, "$NetBSD: residual.c,v 1.12 2006/05/29 22:11:15 garbled Exp $"); #include #include @@ -49,6 +49,8 @@ __KERNEL_RCSID(0, "$NetBSD: residual.c,v 1.11 2006/05/25 02:11:13 garbled Exp $" #include "opt_residual.h" #ifdef RESIDUAL_DATA_DUMP +#include + static void make_pnp_device_tree(void *); static void bustype_subr(DEVICE_ID *); @@ -542,6 +544,84 @@ make_pnp_device_tree(void *v) } } +static void small_vendor_chipid(void *v) +{ + ChipIDPack *p = v; + char chipid[8]; + int16_t id; + int i, j; + struct _svid { + int16_t id; + const char *name; + int type; + } svid[] = { + { Dakota, "IBM North/South Dakota", Chip_MemCont }, + { Idaho, "IBM Idaho", Chip_MemCont }, + { Eagle, "Motorola Eagle", Chip_MemCont }, + { Kauai_Lanai, "IBM Kauai/Lanai", Chip_MemCont }, + { Montana_Nevada,"IBM Montana/Nevada", Chip_MemCont }, + { Union, "IBM Union", Chip_MemCont }, + { Cobra_Viper, "IBM Cobra/Viper", Chip_MemCont }, + { Grackle, "Motorola Grackle", Chip_MemCont }, + { SIO_ZB, "Intel 82378ZB", Chip_ISABridge }, + { FireCoral, "IBM FireCoral", Chip_ISABridge }, + { Python, "IBM Python", Chip_PCIBridge }, + { DEC21050, "PCI-PCI (DEC 21050)", Chip_PCIBridge }, + { IBM2782351, "PCI-PCI (IBM 2782351)", Chip_PCIBridge }, + { IBM2782352, "PCI-PCI (IBM 2782352)", Chip_PCIBridge }, + { INTEL_8236SL, "Intel 8236SL", Chip_PCMCIABridge }, + { RICOH_RF5C366C,"RICOH RF5C366C", Chip_PCMCIABridge }, + { INTEL_82374, "Intel 82374/82375", Chip_EISABridge }, + { MCACoral, "MCA Coral", Chip_MCABridge }, + { Cheyenne, "IBM Cheyenne", Chip_L2Cache }, + { IDT, "IDT", Chip_L2Cache }, + { Sony1PB, "Sony1PB", Chip_L2Cache }, + { Mamba, "IBM Mamba", Chip_L2Cache }, + { Alaska, "IBM Alaska", Chip_L2Cache }, + { Glance, "IBM Glance", Chip_L2Cache }, + { Ocelot, "IBM Ocelot", Chip_L2Cache }, + { Carrera, "IBM Carrera", Chip_PM }, + { Sig750, "Signetics 87C750", Chip_PM }, + { MPIC_2, "IBM MPIC-2", Chip_IntrCont }, + { DallasRTC, "Dallas 1385 compatible", Chip_MiscPlanar }, + { Dallas1585, "Dallas 1585 compatible", Chip_MiscPlanar }, + { Timer8254, "8254-compatible timer", Chip_MiscPlanar }, + { HarddiskLt, "Op Panel HD light", Chip_MiscPlanar }, + { 0, NULL, -1 }, + }; + const char *chiptype[] = { + "Memory Controller", + "ISA Bridge", + "PCI Bridge", + "PCMCIA Bridge", + "EISA Bridge", + "MCA Bridge", + "L2 Cache Controller", + "Power Management Controller", + "Interrupt Controller", + "Misc. Planar Device" + }; + + id = le16dec(&p->Name[0]); + snprintf(chipid, 8, "%c%c%c%0hX", + ((p->VendorID0 >> 2) & 0x1f) + 'A' - 1, + (((p->VendorID0 & 3) << 3) | ((p->VendorID1 >> 5) & 7)) + 'A' - 1, + (p->VendorID1 & 0x1f) + 'A' - 1, id); + for (i = 0, j = -1; svid[i].name != NULL; i++) { + if (id == svid[i].id) { + j = i; + break; + } + } + printf("Chip ID: %s\n", chipid); + if (j == -1) { + printf(" Unknown Chip Type\n"); + return; + } + printf(" %s: %s\n", chiptype[svid[j].type], svid[j].name); + return; +} + static int pnp_small_pkt(void *v) { @@ -687,29 +767,28 @@ IRQout: printf(" SmallVendorItem: "); switch (p[1]) { case 1: - printf("%c%c%c", - ((p[2] >> 2) & 0x1f) + 'A' - 1, - (((p[2] & 3) << 3) | ((p[3] >> 5) & 7)) + 'A' - 1, - (p[3] & 0x1f) + 'A' - 1); + small_vendor_chipid(v); + break; + + case 3: + printf("Processor Number: %d\n", p[2]); break; default: + printf("\n"); + for (i = 0; i < size - 1; i++) { + if ((i % 16) == 0) + printf(" "); + printf("%02x ", p[i + 1]); + if ((i % 16) == 15) + printf("\n"); + } + if ((i % 16) != 0) + printf("\n"); break; } - - printf("\n"); - for (i = 0; i < size - 1; i++) { - if ((i % 16) == 0) - printf(" "); - printf("%02x ", p[i + 1]); - if ((i % 16) == 15) - printf("\n"); - } - if ((i % 16) != 0) - printf("\n"); - } break; - + } default: { unsigned char *p = v; @@ -1516,11 +1595,17 @@ service_subr(DEVICE_ID *id) const char *p, *q = NULL; switch (id->SubType) { - case GeneralMemoryController: - p = "GeneralMemoryController"; + case ServiceProcessorClass1: + p = "ServiceProcessorClass1"; + break; + case ServiceProcessorClass2: + p = "ServiceProcessorClass2"; + break; + case ServiceProcessorClass3: + p = "ServiceProcessorClass3"; break; default: - p = "UnknownMemoryController"; + p = "UnknownServiceProcessor"; break; }