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Move common exception vector and scheduler code to

Browse Source 
sh3/sh3/exception_vector.S and sh3/sh3/locore_subr.S. exception
vectors are installed by sh_cpu_init().  machine/locore.S contains
kernel entry, interrupt handler, and some MD code.
This commit is contained in:
uch 2002-02-24 18:19:40 +00:00
parent 72589177e0
commit 693be1956c
32 changed files with 2251 additions and 6906 deletions
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109
sys/arch/dreamcast/dreamcast/genassym.cf
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@ -1,109 +0,0 @@
# $NetBSD: genassym.cf,v 1.2 2001/02/15 18:30:31 marcus Exp $
#
# Copyright (c) 1995, 1997 Charles M. Hannum. All rights reserved.
# Copyright (c) 1982, 1990 The Regents of the University of California.
# All rights reserved.
#
# This code is derived from software contributed to Berkeley by
# William Jolitz.
#
# Redistribution and use in source and binary forms, with or without
# modification, are permitted provided that the following conditions
# are met:
# 1. Redistributions of source code must retain the above copyright
# notice, this list of conditions and the following disclaimer.
# 2. Redistributions in binary form must reproduce the above copyright
# notice, this list of conditions and the following disclaimer in the
# documentation and/or other materials provided with the distribution.
# 3. All advertising materials mentioning features or use of this software
# must display the following acknowledgement:
# This product includes software developed by the University of
# California, Berkeley and its contributors.
# 4. Neither the name of the University nor the names of its contributors
# may be used to endorse or promote products derived from this software
# without specific prior written permission.
#
# THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
# ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
# IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
# ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
# FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
# DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
# OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
# HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
# LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
# OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
# SUCH DAMAGE.
#
# @(#)genassym.c 5.11 (Berkeley) 5/10/91
#
include "opt_memsize.h"
include "opt_led_addr.h"
include <sys/param.h>
include <sys/proc.h>
include <sys/resourcevar.h>
include <sys/device.h>
include <sys/user.h>
include <sys/mbuf.h>
include <uvm/uvm_extern.h>
include <sh3/mmureg.h>
include <machine/trap.h>
include <machine/pmap.h>
include <machine/vmparam.h>
define SRUN SRUN
define SONPROC SONPROC
define PDSLOT_PTE PDSLOT_PTE
define PDSLOT_APTE PDSLOT_APTE
define PDSLOT_KERN PDSLOT_KERN
define NKPTP_MIN NKPTP_MIN
define NKPTP_MAX NKPTP_MAX
define VM_MAXUSER_ADDRESS (int)VM_MAXUSER_ADDRESS
define P_ADDR offsetof(struct proc, p_addr)
define P_BACK offsetof(struct proc, p_back)
define P_FORW offsetof(struct proc, p_forw)
define P_PRIORITY offsetof(struct proc, p_priority)
define P_STAT offsetof(struct proc, p_stat)
define P_WCHAN offsetof(struct proc, p_wchan)
define P_VMSPACE offsetof(struct proc, p_vmspace)
define P_FLAG offsetof(struct proc, p_flag)
define P_SYSTEM P_SYSTEM
define M_DATA offsetof(struct mbuf, m_data)
define M_LEN offsetof(struct mbuf, m_len)
define M_NEXT offsetof(struct mbuf, m_next)
define V_TRAP offsetof(struct uvmexp, traps)
define V_INTR offsetof(struct uvmexp, intrs)
define PCB_PAGEDIRREG offsetof(struct pcb, pageDirReg)
define PCB_ONFAULT offsetof(struct pcb, pcb_onfault)
define PCB_R15 offsetof(struct pcb, r15)
define PCB_R14 offsetof(struct pcb, r14)
define PCB_KR15 offsetof(struct pcb, kr15)
define TF_SPC offsetof(struct trapframe, tf_spc)
define TF_TRAPNO offsetof(struct trapframe, tf_trapno)
define SIGF_HANDLER offsetof(struct sigframe, sf_handler)
define SIGF_SC offsetof(struct sigframe, sf_sc)
define SC_EFLAGS offsetof(struct sigcontext, sc_ssr)
define IOM_RAM_BEGIN IOM_RAM_BEGIN
define IOM_RAM_SIZE IOM_RAM_SIZE
define IOM_ROM_BEGIN IOM_ROM_BEGIN
# XXX SH4 only
ifdef MMUCR_VALIDBITS
define MMUCR_VALIDBITS MMUCR_VALIDBITS
endif

176
sys/arch/dreamcast/dreamcast/locore.S Normal file
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@ -0,0 +1,176 @@
/* $NetBSD: locore.S,v 1.1 2002/02/24 18:19:41 uch Exp $ */
/*-
* Copyright (c) 2002 The NetBSD Foundation, Inc.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* 3. All advertising materials mentioning features or use of this software
* must display the following acknowledgement:
* This product includes software developed by the NetBSD
* Foundation, Inc. and its contributors.
* 4. Neither the name of The NetBSD Foundation nor the names of its
* contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
* ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
* TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
* BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*/
#include "opt_memsize.h"
#include "assym.h"
#include <sh3/asm.h>
#include <sh3/locore.h>
#include <sh3/mmu_sh4.h>
#include <sh3/cache_sh4.h>
/* bootstrap stack is near upper address of RAM. don't increase MSGBUFSIZE */
#define INIT_STACK IOM_RAM_BEGIN + IOM_RAM_SIZE - 0x00001000
/*
* void start(void) __attribute__((__noreturn__)):
* Kernel entry point.
*/
NENTRY(start)
/* Set bootstrap stack pointer */
mov.l _L.bootstrap_stack, r15
/* Mask all interrupt */
__INTR_MASK_r0_r1
/*
* Cache initialize.
* I/D-cache enable, P0, U0, P3 write-back P1 write-through.
*/
mov.l _L.sh4_icache_sync_all, r0
jsr @r0
nop
mov.l _L.CCR, r0
mov.l _L.CCRconfig, r1
mov.l r1, @r0
/* MMU off */
mov.l _L.MMUCR, r0
xor r1, r1
mov.l r1, @r0
/* Make sure to change register bank 0 */
mov #0x20, r1
stc sr, r0
swap.b r1, r1
swap.w r1, r1
not r1, r1
and r1, r0
ldc r0, sr /* SR.RB = 0 */
/* Go! */
mov.l _L.dreamcast_startup, r0
jmp @r0
nop
/* NOTREACHED */
.align 2
_L.dreamcast_startup: .long _C_LABEL(dreamcast_startup)
_L.bootstrap_stack: .long INIT_STACK
_L.sh4_icache_sync_all: .long _C_LABEL(sh4_icache_sync_all)
_L.CCR: .long SH4_CCR
_L.CCRconfig: .long 0x00000909
_L.MMUCR: .long SH4_MMUCR
/*
* void interrupt_exp(int, int, int, int, stuct trapframe)
* __attribute__((__noreturn__)):
* on entry, SR.BL = 1, SR_RB = 0, all regsiters are saved,
* stack is already setuped.
*/
.align 2
recurse:
stc sr, r4
ldc r5, spc
ldc r4, ssr
RECURSEENTRY
bra 1f
nop
NENTRY(interrupt_exp)
1:
MOV (INTEVT, r0)
mov.l @r0, r0
mov.l r0, @(TF_TRAPNO, r15) /* trapframe->tf_trapno = INTEVT */
__INTR_MASK_r0_r1 /* mask all interrupt */
__EXCEPTION_UNBLOCK_r0_r1 /* enable exception for TLB handling */
mov.l _L.intrhandler, r0
jsr @r0
nop
tst r0, r0 /* intrhandler() == 0, fast intr return */
bt 2f
mov.l _L.check_ipending, r0
jsr @r0
nop
tst r0, r0
bf 1b /* handle pending interrupt. */
/* Check for ASTs on exit to user mode. */
mov.l _L.ast, r0
jsr @r0
mov r15, r4
2:
EXCEPTION_RETURN
/* NOTREACHED */
.align 2
REG_SYMBOL(INTEVT)
_L.intrhandler: .long _C_LABEL(intrhandler)
_L.ast: .long _C_LABEL(ast)
NENTRY(Xspllower)
sts.l pr, @-r15
restart:
__INTR_MASK_r0_r1
__EXCEPTION_UNBLOCK_r0_r1
mov.l _L.check_ipending, r0
jsr @r0
nop
tst r0, r0
bt 1f
mov.l _L.restart, r5
mov.l _L.recurse, r0
jmp @r0
nop
1:
__INTR_UNMASK_r0_r1
lds.l @r15+, pr
rts
nop
.align 2
_L.check_ipending: .long _C_LABEL(check_ipending)
_L.recurse: .long recurse
_L.restart: .long restart
.data
.align 2
.globl _C_LABEL(intrcnt), _C_LABEL(eintrcnt)
.globl _C_LABEL(intrnames), _C_LABEL(eintrnames)
_C_LABEL(intrcnt):
_C_LABEL(eintrcnt):
_C_LABEL(intrnames):
_C_LABEL(eintrnames):

1653
sys/arch/dreamcast/dreamcast/locore.s
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File diff suppressed because it is too large Load Diff

290
sys/arch/dreamcast/dreamcast/machdep.c
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@ -1,4 +1,4 @@
/* $NetBSD: machdep.c,v 1.8 2002/02/22 19:43:59 uch Exp $ */
/* $NetBSD: machdep.c,v 1.9 2002/02/24 18:19:41 uch Exp $ */
/*-
* Copyright (c) 1996, 1997, 1998 The NetBSD Foundation, Inc.
@ -180,23 +180,10 @@ struct extent *ioport_ex;
struct extent *iomem_ex;
static int ioport_malloc_safe;
void main(void) __attribute__((__noreturn__));
void dreamcast_startup(void) __attribute__((__noreturn__));
void setup_bootinfo __P((void));
void dumpsys __P((void));
void identifycpu __P((void));
void initSH3 __P((void *));
void InitializeSci __P((unsigned char));
void sh3_cache_on __P((void));
void LoadAndReset __P((char *));
void XLoadAndReset __P((char *));
void Sh3Reset __P((void));
#ifdef SH4
void sh4_cache_flush __P((vaddr_t));
#endif
#include <dev/ic/comreg.h>
#include <dev/ic/comvar.h>
void consinit __P((void));
/*
@ -241,7 +228,6 @@ cpu_sysctl(name, namelen, oldp, oldlenp, newp, newlen, p)
dev_t consdev;
struct btinfo_bootpath *bibp;
struct trapframe *tf;
char *osimage;
/* all sysctl names at this level are terminal */
if (namelen != 1)
@ -277,16 +263,6 @@ cpu_sysctl(name, namelen, oldp, oldlenp, newp, newlen, p)
case CPU_DEBUGMODE:
return (sysctl_int(oldp, oldlenp, newp, newlen,
&cpu_debug_mode));
case CPU_LOADANDRESET:
if (newp != NULL) {
osimage = (char *)(*(u_long *)newp);
LoadAndReset(osimage);
/* not reach here */
}
return (0);
default:
return (EOPNOTSUPP);
}
@ -524,21 +500,13 @@ dumpsys()
/*
* Initialize segments and descriptor tables
*/
#define VBRINIT ((char *)IOM_RAM_BEGIN)
#define Trap100Vec (VBRINIT + 0x100)
#define Trap600Vec (VBRINIT + 0x600)
#define TLBVECTOR (VBRINIT + 0x400)
#define VADDRSTART VM_MIN_KERNEL_ADDRESS
extern int nkpde;
extern char MonTrap100[], MonTrap100_end[];
extern char MonTrap600[], MonTrap600_end[];
extern char _start[], _etext[], _edata[], _end[];
extern char tlbmisshandler_stub[], tlbmisshandler_stub_end[];
extern char start[], _etext[], _edata[], _end[];
void
initSH3(pc)
void *pc; /* XXX return address */
dreamcast_startup()
{
paddr_t avail;
pd_entry_t *pagedir;
@ -560,14 +528,6 @@ initSH3(pc)
memset(_edata, 0, p - _edata);
sh_cpu_init(CPU_ARCH_SH4, CPU_PRODUCT_7750);
/*
* install trap handler
*/
memcpy(Trap100Vec, MonTrap100, MonTrap100_end - MonTrap100);
memcpy(Trap600Vec, MonTrap600, MonTrap600_end - MonTrap600);
__asm ("ldc %0, vbr" :: "r"(VBRINIT));
/*
* edata end
* +-------------+------+-----+----------+-------------+------------+
@ -605,11 +565,6 @@ initSH3(pc)
/* set PageDirReg */
SH_MMU_TTB_WRITE((u_int32_t)pagedir);
/* Set TLB miss handler */
p = tlbmisshandler_stub;
x = tlbmisshandler_stub_end - p;
memcpy(TLBVECTOR, p, x);
/*
* Activate MMU
*/
@ -651,7 +606,7 @@ initSH3(pc)
(caddr_t)iomem_ex_storage, sizeof(iomem_ex_storage),
EX_NOCOALESCE|EX_NOWAIT);
#if 0
#if 1
consinit(); /* XXX SHOULD NOT BE DONE HERE */
#endif
@ -669,8 +624,8 @@ initSH3(pc)
u_short *p, sum;
int size;
size = _etext - _start;
p = (u_short *)_start;
size = _etext - start;
p = (u_short *)start;
sum = 0;
size >>= 1;
while (size--)
@ -721,18 +676,16 @@ initSH3(pc)
*/
setup_bootinfo();
#if 0
sh3_cache_on();
#endif
/* setup proc0 stack */
sp = avail + NBPG + USPACE - 16 - sizeof(struct trapframe);
/*
* XXX We can't return here, because we change stack pointer.
* So jump to return address directly.
*/
__asm __volatile ("jmp @%0; mov %1, r15" :: "r"(pc), "r"(sp));
/* jump to main */
__asm__ __volatile__(
"jmp @%0;"
"mov %1, sp" :: "r"(main), "r"(sp));
/* NOTREACHED */
while (1)
;
}
void
@ -792,218 +745,7 @@ cpu_reset()
_cpu_exception_suspend();
Sh3Reset();
goto *(u_int32_t *)0xa0000000;
for (;;)
;
}
#if !defined(DONT_INIT_BSC)
/*
* InitializeBsc
* : BSC(Bus State Controler)
*/
void InitializeBsc __P((void));
void
InitializeBsc()
{
/*
* Drive RAS,CAS in stand by mode and bus release mode
* Area0 = Normal memory, Area5,6=Normal(no burst)
* Area2 = Normal memory, Area3 = SDRAM, Area5 = Normal memory
* Area4 = Normal Memory
* Area6 = Normal memory
*/
SHREG_BCR1 = BSC_BCR1_VAL;
/*
* Bus Width
* Area4: Bus width = 16bit
* Area6,5 = 16bit
* Area1 = 8bit
* Area2,3: Bus width = 32bit
*/
SHREG_BCR2 = BSC_BCR2_VAL;
/*
* Idle cycle number in transition area and read to write
* Area6 = 3, Area5 = 3, Area4 = 3, Area3 = 3, Area2 = 3
* Area1 = 3, Area0 = 3
*/
SHREG_WCR1 = BSC_WCR1_VAL;
/*
* Wait cycle
* Area 6 = 6
* Area 5 = 2
* Area 4 = 10
* Area 3 = 3
* Area 2,1 = 3
* Area 0 = 6
*/
SHREG_WCR2 = BSC_WCR2_VAL;
#if defined(SH4) && defined(BSC_WCR3_VAL)
SHREG_WCR3 = BSC_WCR3_VAL;
#endif
/*
* RAS pre-charge = 2cycle, RAS-CAS delay = 3 cycle,
* write pre-charge=1cycle
* CAS before RAS refresh RAS assert time = 3 cycle
* Disable burst, Bus size=32bit, Column Address=10bit, Refresh ON
* CAS before RAS refresh ON, EDO DRAM
*/
SHREG_MCR = BSC_MCR_VAL;
#if defined(BSC_SDMR2_VAL)
#define SDMR2 (*(volatile unsigned char *)BSC_SDMR2_VAL)
SDMR2 = 0;
#endif
#if defined(BSC_SDMR3_VAL)
#if !(defined(COMPUTEXEVB) && defined(SH7709A))
#define SDMR3 (*(volatile unsigned char *)BSC_SDMR3_VAL)
SDMR3 = 0;
#else
#define ADDSET (*(volatile unsigned short *)0x1A000000)
#define ADDRST (*(volatile unsigned short *)0x18000000)
#define SDMR3 (*(volatile unsigned char *)BSC_SDMR3_VAL)
ADDSET = 0;
SDMR3 = 0;
ADDRST = 0;
#endif
#endif
/*
* PCMCIA Control Register
* OE/WE assert delay 3.5 cycle
* OE/WE negate-address delay 3.5 cycle
*/
#ifdef BSC_PCR_VAL
SHREG_PCR = BSC_PCR_VAL;
#endif
/*
* Refresh Timer Control/Status Register
* Disable interrupt by CMF, closk 1/16, Disable OVF interrupt
* Count Limit = 1024
* In following statement, the reason why high byte = 0xa5(a4 in RFCR)
* is the rule of SH3 in writing these register.
*/
SHREG_RTCSR = BSC_RTCSR_VAL;
/*
* Refresh Timer Counter
* Initialize to 0
*/
#ifdef BSC_RTCNT_VAL
SHREG_RTCNT = BSC_RTCNT_VAL;
#endif
/* set Refresh Time Constant Register */
SHREG_RTCOR = BSC_RTCOR_VAL;
/* init Refresh Count Register */
#ifdef BSC_RFCR_VAL
SHREG_RFCR = BSC_RFCR_VAL;
#endif
/* Set Clock mode (make internal clock double speed) */
SHREG_FRQCR = FRQCR_VAL;
#ifndef MMEYE_NO_CACHE
/* Cache ON */
SHREG_CCR = CCR_CE;
#endif
}
#endif
void
sh3_cache_on(void)
{
#ifndef MMEYE_NO_CACHE
/* Cache ON */
SHREG_CCR = CCR_CE;
SHREG_CCR = CCR_CF | CCR_CE; /* cache clear */
SHREG_CCR = CCR_CE; /* cache on */
#endif
}
#ifdef SH4
void
sh4_cache_flush(addr)
vaddr_t addr;
{
#if 1
#define SH_ADDR_ARRAY_BASE_ADDR 0xf4000000
#define WRITE_ADDR_ARRAY( entry ) \
(*(volatile u_int32_t *)(SH_ADDR_ARRAY_BASE_ADDR|(entry)|0x00))
int entry;
entry = ((u_int32_t)addr) & 0x3fe0;
WRITE_ADDR_ARRAY(entry) = 0;
#else
volatile int *p = (int *)IOM_RAM_BEGIN;
int i;
/* volatile */int d;
for(i = 0; i < 512; i++){
d = *p;
p += 8;
}
#endif
}
#endif
#include <machine/mmeye.h>
/* XXX This value depends on physical available memory */
#define OSIMAGE_BUF_ADDR (IOM_RAM_BEGIN + 0x00400000)
void
LoadAndReset(osimage)
char *osimage;
{
void *buf_addr;
u_long size;
u_long *src;
u_long *dest;
u_long csum = 0;
u_long csum2 = 0;
u_long size2;
printf("LoadAndReset: copy start\n");
buf_addr = (void *)OSIMAGE_BUF_ADDR;
size = *(u_long *)osimage;
src = (u_long *)osimage;
dest = buf_addr;
size = (size + sizeof(u_long) * 2 + 3) >> 2;
size2 = size;
while (size--) {
csum += *src;
*dest++ = *src++;
}
dest = buf_addr;
while (size2--)
csum2 += *dest++;
printf("LoadAndReset: copy end[%lx,%lx]\n", csum, csum2);
printf("start XLoadAndReset\n");
/* mask all externel interrupt (XXX) */
XLoadAndReset(buf_addr);
}

110
sys/arch/evbsh3/evbsh3/genassym.cf
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@ -1,110 +0,0 @@
# $NetBSD: genassym.cf,v 1.9 2000/09/04 05:50:45 msaitoh Exp $
#
# Copyright (c) 1995, 1997 Charles M. Hannum. All rights reserved.
# Copyright (c) 1982, 1990 The Regents of the University of California.
# All rights reserved.
#
# This code is derived from software contributed to Berkeley by
# William Jolitz.
#
# Redistribution and use in source and binary forms, with or without
# modification, are permitted provided that the following conditions
# are met:
# 1. Redistributions of source code must retain the above copyright
# notice, this list of conditions and the following disclaimer.
# 2. Redistributions in binary form must reproduce the above copyright
# notice, this list of conditions and the following disclaimer in the
# documentation and/or other materials provided with the distribution.
# 3. All advertising materials mentioning features or use of this software
# must display the following acknowledgement:
# This product includes software developed by the University of
# California, Berkeley and its contributors.
# 4. Neither the name of the University nor the names of its contributors
# may be used to endorse or promote products derived from this software
# without specific prior written permission.
#
# THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
# ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
# IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
# ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
# FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
# DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
# OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
# HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
# LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
# OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
# SUCH DAMAGE.
#
# @(#)genassym.c 5.11 (Berkeley) 5/10/91
#
include "opt_memsize.h"
include "opt_led_addr.h"
include <sys/param.h>
include <sys/proc.h>
include <sys/resourcevar.h>
include <sys/device.h>
include <sys/user.h>
include <sys/mbuf.h>
include <uvm/uvm_extern.h>
include <sh3/mmureg.h>
include <machine/trap.h>
include <machine/pmap.h>
include <machine/vmparam.h>
define SRUN SRUN
define SONPROC SONPROC
define PDSLOT_PTE PDSLOT_PTE
define PDSLOT_APTE PDSLOT_APTE
define PDSLOT_KERN PDSLOT_KERN
define NKPTP_MIN NKPTP_MIN
define NKPTP_MAX NKPTP_MAX
define VM_MAXUSER_ADDRESS (int)VM_MAXUSER_ADDRESS
define P_ADDR offsetof(struct proc, p_addr)
define P_BACK offsetof(struct proc, p_back)
define P_FORW offsetof(struct proc, p_forw)
define P_PRIORITY offsetof(struct proc, p_priority)
define P_STAT offsetof(struct proc, p_stat)
define P_WCHAN offsetof(struct proc, p_wchan)
define P_VMSPACE offsetof(struct proc, p_vmspace)
define P_FLAG offsetof(struct proc, p_flag)
define P_SYSTEM P_SYSTEM
define M_DATA offsetof(struct mbuf, m_data)
define M_LEN offsetof(struct mbuf, m_len)
define M_NEXT offsetof(struct mbuf, m_next)
define V_TRAP offsetof(struct uvmexp, traps)
define V_INTR offsetof(struct uvmexp, intrs)
define PCB_PAGEDIRREG offsetof(struct pcb, pageDirReg)
define PCB_ONFAULT offsetof(struct pcb, pcb_onfault)
define PCB_R15 offsetof(struct pcb, r15)
define PCB_R14 offsetof(struct pcb, r14)
define PCB_KR15 offsetof(struct pcb, kr15)
define TF_SPC offsetof(struct trapframe, tf_spc)
define TF_TRAPNO offsetof(struct trapframe, tf_trapno)
define SIGF_HANDLER offsetof(struct sigframe, sf_handler)
define SIGF_SC offsetof(struct sigframe, sf_sc)
define SC_EFLAGS offsetof(struct sigcontext, sc_ssr)
define IOM_RAM_BEGIN IOM_RAM_BEGIN
define IOM_RAM_SIZE IOM_RAM_SIZE
define IOM_ROM_BEGIN IOM_ROM_BEGIN
# XXX SH4 only
ifdef MMUCR_VALIDBITS
define MMUCR_VALIDBITS MMUCR_VALIDBITS
endif
define LED_ADDR LED_ADDR

354
sys/arch/evbsh3/evbsh3/locore.S Normal file
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@ -0,0 +1,354 @@
/* $NetBSD: locore.S,v 1.1 2002/02/24 18:19:41 uch Exp $ */
/*-
* Copyright (c) 1993, 1994, 1995, 1997
* Charles M. Hannum. All rights reserved.
* Copyright (c) 1990 The Regents of the University of California.
* All rights reserved.
*
* This code is derived from software contributed to Berkeley by
* William Jolitz.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* 3. All advertising materials mentioning features or use of this software
* must display the following acknowledgement:
* This product includes software developed by the University of
* California, Berkeley and its contributors.
* 4. Neither the name of the University nor the names of its contributors
* may be used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
* SUCH DAMAGE.
*
* @(#)locore.s 7.3 (Berkeley) 5/13/91
*/
#include "opt_ddb.h"
#include "opt_lockdebug.h"
#include "opt_memsize.h"
#include "assym.h"
#include <sys/errno.h>
#include <sys/syscall.h>
#include <sh3/locore.h>
#include <machine/asm.h>
#include <machine/cputypes.h>
#include <machine/param.h>
#include <machine/pte.h>
#include <machine/trap.h>
#define INIT_STACK IOM_RAM_BEGIN + IOM_RAM_SIZE - 0x00001000
#ifdef SH4
#define SHREG_BBRA 0xff200008
#define SHREG_CCR 0xff00001c
#define SHREG_EXPEVT 0xff000024
#define SHREG_INTEVT 0xff000028
#define SHREG_MMUCR 0xff000010
#define SHREG_TTB 0xff000008
#else
#define SHREG_BBRA 0xffffffb8
#define SHREG_CCR 0xffffffec
#define SHREG_EXPEVT 0xffffffd4
#define SHREG_INTEVT 0xffffffd8
#define SHREG_MMUCR 0xffffffe0
#define SHREG_TTB 0xfffffff8
#endif
NENTRY(start)
/* Set SP to initial position */
mov.l XLtmpstk, r15
__INTR_MASK_r0_r1
/* Set Register Bank to Bank 0 */
mov.l SR_init, r0
ldc r0, sr
xor r0, r0
mov.l XL_SHREG_MMUCR, r2
mov.l r0, @r2 /* MMU OFF */
bra start1
nop
.align 2
SR_init: .long 0x500000F0
XL_SHREG_MMUCR: .long SHREG_MMUCR
start1:
#ifdef ROMIMAGE
/* Initialize BUS State Control Regs. */
mov.l _ROM_START, r3
mov.l XL_ram_start, r4
mov.l @r4, r4
sub r3, r4
/* Set Bus State Controler */
mov.l XLInitializeBsc, r0
sub r4, r0
jsr @r0
nop
/* Move kernel image from ROM area to RAM area */
mov.l ___end, r0
mov.l ___start, r1
mov.l _KERNBASE, r2
sub r2, r0
sub r2, r1
sub r1, r0
add #4, r0 /* size of bytes to be copied */
shlr2 r0 /* number of long word */
mov.l _ROM_START, r3
add r3, r1 /* src address */
mov.l ___start, r3
sub r2, r3
mov.l XL_ram_start, r4
mov.l @r4, r4
add r4, r3 /* dest address */
1:
mov.l @r1+, r4
mov.l r4, @r3
add #4, r3
dt r0 /* decrement and Test */
bf 1b
/* kernel image copy end */
mov.l LXstart_in_RAM, r0
jmp @r0 /* jump to RAM area */
nop
.align 2
LXstart_in_RAM:
.long start_in_RAM
XL_ram_start:
.long _C_LABEL(ram_start)
#else
#ifndef DONT_INIT_BSC
/* Set Bus State Controler */
mov.l XLInitializeBsc, r0
jsr @r0
nop
#endif
#endif
start_in_RAM:
mova 1f, r0
mov r0, r4
mov.l XLinitSH3, r0
jsr @r0 /* call initSH3() */
nop
.align 2
1:
#ifdef SH4
/* CCR must be accessed from P2 area */
mova cache_on, r0
mov r0, r5
mov.l XLtoP2, r1
add r1, r5
mova main_label, r0
mov r0, r2
mov.l XL_SHREG_CCR, r3
mov.l XL_CCRVAL, r4
jmp @r5
nop
.align 2
cache_on:
mov.l r4, @r3 /* Write to CCR */
nop
nop
nop
nop
nop
nop
nop
nop
jmp @r2
nop
.align 2
main_label:
#endif
mov.l XLmain, r0
jsr @r0 /* call main() */
nop
.align 2
#ifndef DONT_INIT_BSC
XLInitializeBsc:.long _C_LABEL(InitializeBsc)
#endif
___start: .long start
___etext: .long _etext
___end: .long _end
XLtmpstk: .long INIT_STACK
_KERNBASE: .long KERNBASE
_ROM_START: .long IOM_ROM_BEGIN
XLinitSH3: .long _C_LABEL(initSH3)
XLmain: .long _C_LABEL(main)
XLtoP2: .long 0x20000000
XL_SHREG_CCR: .long SHREG_CCR
#ifdef SH4
#if 1
XL_CCRVAL: .long 0x0909 /* Operand cache ON */
#else
XL_CCRVAL: .long 0x0000 /* cache OFF */
#endif
#endif
load_and_reset:
mov.l XL_start_address, r0
mov r0, r8
mov.l @r4+, r1 /* r1 = osimage size */
mov.l @r4+, r2 /* r2 = check sum */
shlr2 r1 /* r1 = osimage size in dword */
1:
mov.l @r4+, r3
mov.l r3, @r0
add #4, r0
dt r1
bf 1b
jmp @r8 /* jump to start address */
nop
.align 2
XL_start_address:
.long IOM_RAM_BEGIN + 0x00010000
load_and_reset_end:
ENTRY(XLoadAndReset)
__INTR_MASK_r0_r1
/* copy trampoline code to RAM area top */
mov.l XL_load_and_reset, r0
mov.l XL_load_and_reset_end, r1
mov.l XL_load_trampoline_addr, r2
mov r2, r8
sub r0, r1 /* r1 = bytes to be copied */
1: mov.b @r0+, r3
mov.b r3, @r2
add #1, r2
dt r1
bf 1b
jmp @r8 /* jump to trampoline code */
nop
.align 2
XL_load_trampoline_addr:
.long IOM_RAM_BEGIN + 0x00008000
XL_load_and_reset:
.long load_and_reset
XL_load_and_reset_end:
.long load_and_reset_end
ENTRY(Sh3Reset)
mov.l XL_reset_vector, r8
jmp @r8
nop
.align 2
XL_reset_vector:
.long 0xa0000000
/*
* void interrupt_exp(int, int, int, int, stuct trapframe)
* __attribute__((__noreturn__)):
* on entry, SR.BL = 1, SR_RB = 0, all regsiters are saved,
* stack is already setuped.
*/
.align 2
recurse:
stc sr, r4
ldc r5, spc
ldc r4, ssr
RECURSEENTRY
bra 1f
nop
NENTRY(interrupt_exp)
1:
MOV (INTEVT, r0)
mov.l @r0, r0
mov.l r0, @(TF_TRAPNO, r15) /* trapframe->tf_trapno = INTEVT */
__INTR_MASK_r0_r1 /* mask all interrupt */
__EXCEPTION_UNBLOCK_r0_r1 /* enable exception for TLB handling */
mov.l _L.intrhandler, r0
jsr @r0
nop
tst r0, r0 /* intrhandler() == 0, fast intr return */
bt 2f
mov.l _L.check_ipending, r0
jsr @r0
nop
tst r0, r0
bf 1b /* handle pending interrupt. */
/* Check for ASTs on exit to user mode. */
mov.l _L.ast, r0
jsr @r0
mov r15, r4
2:
EXCEPTION_RETURN
/* NOTREACHED */
.align 2
REG_SYMBOL(INTEVT)
_L.intrhandler: .long _C_LABEL(intrhandler)
_L.ast: .long _C_LABEL(ast)
NENTRY(Xspllower)
sts.l pr, @-r15
restart:
__INTR_MASK_r0_r1
__EXCEPTION_UNBLOCK_r0_r1
mov.l _L.check_ipending, r0
jsr @r0
nop
tst r0, r0
bt 1f
mov.l _L.restart, r5
mov.l _L.recurse, r0
jmp @r0
nop
1:
__INTR_UNMASK_r0_r1
lds.l @r15+, pr
rts
nop
.align 2
_L.check_ipending: .long _C_LABEL(check_ipending)
_L.recurse: .long recurse
_L.restart: .long restart
.data
.align 2
.globl _C_LABEL(intrcnt), _C_LABEL(eintrcnt)
.globl _C_LABEL(intrnames), _C_LABEL(eintrnames)
_C_LABEL(intrcnt):
_C_LABEL(eintrcnt):
_C_LABEL(intrnames):
_C_LABEL(eintrnames):

1655
sys/arch/evbsh3/evbsh3/locore.s
View File

File diff suppressed because it is too large Load Diff

26
sys/arch/evbsh3/evbsh3/machdep.c
View File

@ -1,4 +1,4 @@
/* $NetBSD: machdep.c,v 1.31 2002/02/19 17:21:19 uch Exp $ */
/* $NetBSD: machdep.c,v 1.32 2002/02/24 18:19:41 uch Exp $ */
/*-
* Copyright (c) 1996, 1997, 1998 The NetBSD Foundation, Inc.
@ -517,17 +517,10 @@ dumpsys()
/*
* Initialize segments and descriptor tables
*/
#define VBRINIT ((char *)IOM_RAM_BEGIN)
#define Trap100Vec (VBRINIT + 0x100)
#define Trap600Vec (VBRINIT + 0x600)
#define TLBVECTOR (VBRINIT + 0x400)
#define VADDRSTART VM_MIN_KERNEL_ADDRESS
extern int nkpde;
extern char MonTrap100[], MonTrap100_end[];
extern char MonTrap600[], MonTrap600_end[];
extern char _start[], etext[], edata[], end[];
extern char tlbmisshandler_stub[], tlbmisshandler_stub_end[];
extern char start[], etext[], edata[], end[];
void
initSH3(pc)
@ -561,12 +554,6 @@ initSH3(pc)
#else
#error "define SH3 or SH4"
#endif
/*
* install trap handler
*/
memcpy(Trap100Vec, MonTrap100, MonTrap100_end - MonTrap100);
memcpy(Trap600Vec, MonTrap600, MonTrap600_end - MonTrap600);
__asm ("ldc %0, vbr" :: "r"(VBRINIT));
/*
* edata end
@ -605,11 +592,6 @@ initSH3(pc)
/* set PageDirReg */
SH_MMU_TTB_WRITE((u_int32_t)pagedir);
/* Set TLB miss handler */
p = tlbmisshandler_stub;
x = tlbmisshandler_stub_end - p;
memcpy(TLBVECTOR, p, x);
/*
* Activate MMU
*/
@ -669,8 +651,8 @@ initSH3(pc)
u_short *p, sum;
int size;
size = etext - _start;
p = (u_short *)_start;
size = etext - start;
p = (u_short *)start;
sum = 0;
size >>= 1;
while (size--)

4
sys/arch/hpcsh/conf/files.hpcsh
View File

@ -1,4 +1,4 @@
# $NetBSD: files.hpcsh,v 1.20 2002/02/22 19:44:03 uch Exp $
# $NetBSD: files.hpcsh,v 1.21 2002/02/24 18:19:43 uch Exp $
#
maxpartitions 8
@ -9,6 +9,8 @@ defflag debug_hpcsh.h BUS_SPACE_DEBUG
HD64461VIDEO_DEBUG
HD64461PCMCIA_DEBUG
defparam opt_memsize.h IOM_ROM_BEGIN IOM_ROM_SIZE IOM_RAM_BEGIN IOM_RAM_SIZE
file arch/hpcsh/hpcsh/conf.c
file arch/hpcsh/hpcsh/machdep.c
file arch/hpcsh/hpcsh/console.c

6
sys/arch/hpcsh/conf/shl-_elf.x
View File

@ -1,8 +1,8 @@
/* $NetBSD: shl-_elf.x,v 1.2 2001/11/20 12:56:28 lukem Exp $ */
/* $NetBSD: shl-_elf.x,v 1.3 2002/02/24 18:19:44 uch Exp $ */
OUTPUT_FORMAT("elf32-shl-unx")
OUTPUT_ARCH(sh)
ENTRY(_start)
ENTRY(start)
MEMORY
{
@ -10,8 +10,6 @@ MEMORY
}
SECTIONS
{
_trap_base = 0x8c000000;
PROVIDE (_trap_base = .);
.text :
{
_ftext = . ;

4
sys/arch/hpcsh/conf/shl-coff.x
View File

@ -1,4 +1,4 @@
/* $NetBSD: shl-coff.x,v 1.3 2001/11/20 12:56:28 lukem Exp $ */
/* $NetBSD: shl-coff.x,v 1.4 2002/02/24 18:19:44 uch Exp $ */
OUTPUT_FORMAT("coff-shl")
OUTPUT_ARCH(sh)
@ -10,8 +10,6 @@ MEMORY
SECTIONS
{
_trap_base = 0x8c000000;
PROVIDE (_trap_base = .);
.text :
{
_ftext = . ;

6
sys/arch/hpcsh/conf/shl-elf.x
View File

@ -1,8 +1,8 @@
/* $NetBSD: shl-elf.x,v 1.3 2001/11/20 12:56:28 lukem Exp $ */
/* $NetBSD: shl-elf.x,v 1.4 2002/02/24 18:19:44 uch Exp $ */
OUTPUT_FORMAT("elf32-shl-unx")
OUTPUT_ARCH(sh)
ENTRY(_start)
ENTRY(start)
MEMORY
{
@ -10,8 +10,6 @@ MEMORY
}
SECTIONS
{
trap_base = 0x8c000000;
PROVIDE (trap_base = .);
.text :
{
ftext = . ;

3
sys/arch/hpcsh/conf/std.hpcsh
View File

@ -1,10 +1,11 @@
# $NetBSD: std.hpcsh,v 1.2 2001/11/20 12:56:28 lukem Exp $
# $NetBSD: std.hpcsh,v 1.3 2002/02/24 18:19:44 uch Exp $
#
# standard, required NetBSD/hpcsh 'options'
machine hpcsh sh3
options EXEC_SCRIPT # exec #! scripts
options IOM_RAM_BEGIN=0x8c000000
makeoptions ENDIAN="-EL"
#makeoptions LDSCRIPTBASE="shl-coff.x" # for COFF kernel

96
sys/arch/hpcsh/hpcsh/genassym.cf
View File

@ -1,96 +0,0 @@
# $NetBSD: genassym.cf,v 1.3 2002/02/17 21:01:18 uch Exp $
#
# Copyright (c) 1995, 1997 Charles M. Hannum. All rights reserved.
# Copyright (c) 1982, 1990 The Regents of the University of California.
# All rights reserved.
#
# This code is derived from software contributed to Berkeley by
# William Jolitz.
#
# Redistribution and use in source and binary forms, with or without
# modification, are permitted provided that the following conditions
# are met:
# 1. Redistributions of source code must retain the above copyright
# notice, this list of conditions and the following disclaimer.
# 2. Redistributions in binary form must reproduce the above copyright
# notice, this list of conditions and the following disclaimer in the
# documentation and/or other materials provided with the distribution.
# 3. All advertising materials mentioning features or use of this software
# must display the following acknowledgement:
# This product includes software developed by the University of
# California, Berkeley and its contributors.
# 4. Neither the name of the University nor the names of its contributors
# may be used to endorse or promote products derived from this software
# without specific prior written permission.
#
# THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
# ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
# IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
# ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
# FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
# DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
# OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
# HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
# LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
# OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
# SUCH DAMAGE.
#
# @(#)genassym.c 5.11 (Berkeley) 5/10/91
#
include <sys/param.h>
include <sys/proc.h>
include <sys/resourcevar.h>
include <sys/device.h>
include <sys/user.h>
include <sys/mbuf.h>
include <uvm/uvm_extern.h>
include <sh3/mmureg.h>
include <machine/trap.h>
include <machine/pmap.h>
include <machine/vmparam.h>
define SRUN SRUN
define SONPROC SONPROC
define PDSLOT_PTE PDSLOT_PTE
define PDSLOT_APTE PDSLOT_APTE
define PDSLOT_KERN PDSLOT_KERN
define NKPTP_MIN NKPTP_MIN
define NKPTP_MAX NKPTP_MAX
define VM_MAXUSER_ADDRESS (int)VM_MAXUSER_ADDRESS
define P_ADDR offsetof(struct proc, p_addr)
define P_BACK offsetof(struct proc, p_back)
define P_FORW offsetof(struct proc, p_forw)
define P_PRIORITY offsetof(struct proc, p_priority)
define P_STAT offsetof(struct proc, p_stat)
define P_WCHAN offsetof(struct proc, p_wchan)
define P_VMSPACE offsetof(struct proc, p_vmspace)
define P_FLAG offsetof(struct proc, p_flag)
define P_SYSTEM P_SYSTEM
define M_DATA offsetof(struct mbuf, m_data)
define M_LEN offsetof(struct mbuf, m_len)
define M_NEXT offsetof(struct mbuf, m_next)
define V_TRAP offsetof(struct uvmexp, traps)
define V_INTR offsetof(struct uvmexp, intrs)
define PCB_PAGEDIRREG offsetof(struct pcb, pageDirReg)
define PCB_ONFAULT offsetof(struct pcb, pcb_onfault)
define PCB_R15 offsetof(struct pcb, r15)
define PCB_R14 offsetof(struct pcb, r14)
define PCB_KR15 offsetof(struct pcb, kr15)
define TF_SPC offsetof(struct trapframe, tf_spc)
define TF_TRAPNO offsetof(struct trapframe, tf_trapno)
define SIGF_HANDLER offsetof(struct sigframe, sf_handler)
define SIGF_SC offsetof(struct sigframe, sf_sc)
define SC_EFLAGS offsetof(struct sigcontext, sc_ssr)

138
sys/arch/hpcsh/hpcsh/locore.S Normal file
View File

@ -0,0 +1,138 @@
/* $NetBSD: locore.S,v 1.1 2002/02/24 18:19:40 uch Exp $ */
/*-
* Copyright (c) 2002 The NetBSD Foundation, Inc.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* 3. All advertising materials mentioning features or use of this software
* must display the following acknowledgement:
* This product includes software developed by the NetBSD
* Foundation, Inc. and its contributors.
* 4. Neither the name of The NetBSD Foundation nor the names of its
* contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
* ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
* TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
* BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*/
#include "assym.h"
#include <sh3/asm.h>
#include <sh3/locore.h>
/*
* void start(int argc, char *argv[], struct bootinfo *bi)
* __attribute__((__noreturn__)):
* Kernel entry point. setup bootstrap stack pointer.
* Don't pollute r4, r5, r6, since these are passed down to
* machine_startup().
*/
NENTRY(start)
mov.l _L.machine_startup, r0
mov.l _L.bootstrap_stack, r1
jmp @r0
mov r1, r15
/* NOTREACHED */
.align 2
_L.machine_startup: .long _C_LABEL(machine_startup)
_L.bootstrap_stack: .long _C_LABEL(start)
/*
* void interrupt_exp(int, int, int, int, stuct trapframe)
* __attribute__((__noreturn__)):
* on entry, SR.BL = 1, SR_RB = 0, all regsiters are saved,
* stack is already setuped.
*/
.align 2
recurse:
stc sr, r4
ldc r5, spc
ldc r4, ssr
RECURSEENTRY
bra 1f
nop
NENTRY(interrupt_exp)
1:
MOV (INTEVT, r0)
mov.l @r0, r0
mov.l r0, @(TF_TRAPNO, r15) /* trapframe->tf_trapno = INTEVT */
__INTR_MASK_r0_r1 /* mask all interrupt */
__EXCEPTION_UNBLOCK_r0_r1 /* enable exception for TLB handling */
mov.l _L.intrhandler, r0
jsr @r0
nop
tst r0, r0 /* intrhandler() == 0, fast intr return */
bt 2f
mov.l _L.check_ipending, r0
jsr @r0
nop
tst r0, r0
bf 1b /* handle pending interrupt. */
/* Check for ASTs on exit to user mode. */
mov.l _L.ast, r0
jsr @r0
mov r15, r4
2:
EXCEPTION_RETURN
/* NOTREACHED */
.align 2
REG_SYMBOL(INTEVT)
_L.intrhandler: .long _C_LABEL(intrhandler)
_L.ast: .long _C_LABEL(ast)
NENTRY(Xspllower)
sts.l pr, @-r15
restart:
__INTR_MASK_r0_r1
__EXCEPTION_UNBLOCK_r0_r1
mov.l _L.check_ipending, r0
jsr @r0
nop
tst r0, r0
bt 1f
mov.l _L.restart, r5
mov.l _L.recurse, r0
jmp @r0
nop
1:
__INTR_UNMASK_r0_r1
lds.l @r15+, pr
rts
nop
.align 2
_L.check_ipending: .long _C_LABEL(check_ipending)
_L.recurse: .long recurse
_L.restart: .long restart
.data
.align 2
.globl _C_LABEL(intrcnt), _C_LABEL(eintrcnt)
.globl _C_LABEL(intrnames), _C_LABEL(eintrnames)
_C_LABEL(intrcnt):
_C_LABEL(eintrcnt):
_C_LABEL(intrnames):
_C_LABEL(eintrnames):

1243
sys/arch/hpcsh/hpcsh/locore.s
View File

File diff suppressed because it is too large Load Diff

48
sys/arch/hpcsh/hpcsh/machdep.c
View File

@ -1,4 +1,4 @@
/* $NetBSD: machdep.c,v 1.25 2002/02/22 19:44:01 uch Exp $ */
/* $NetBSD: machdep.c,v 1.26 2002/02/24 18:19:40 uch Exp $ */
/*-
* Copyright (c) 2001, 2002 The NetBSD Foundation, Inc.
@ -121,13 +121,11 @@ extern int nfs_mountroot(void);
extern int (*mountroot)(void);
#endif
/* curpcb is defined in locore.s */
struct user *proc0paddr;
char machine[] = MACHINE;
char machine_arch[] = MACHINE_ARCH;
paddr_t msgbuf_paddr;
vaddr_t ram_start = SH3_PHYS_TO_P1SEG(DRAM_BANK0_START);
extern int nkpde;
extern char cpu_model[];
extern paddr_t avail_start, avail_end; // XXX
@ -159,20 +157,16 @@ static int __check_dram(paddr_t, paddr_t);
int mem_cluster_cnt;
phys_ram_seg_t mem_clusters[VM_PHYSSEG_MAX];
int physmem;
u_int32_t __sh_BBRA; //XXX
void main(void);
void machine_startup(int, char *[], struct bootinfo *);
void main(void) __attribute__((__noreturn__));
void machine_startup(int, char *[], struct bootinfo *)
__attribute__((__noreturn__));
struct bootinfo *bootinfo;
void
machine_startup(int argc, char *argv[], struct bootinfo *bi)
{
extern char trap_base[], edata[], end[];
/* exception handler */
extern char MonTrap100[], MonTrap100_end[];
extern char MonTrap600[], MonTrap600_end[];
extern char tlbmisshandler_stub[], tlbmisshandler_stub_end[];
extern char edata[], end[];
vaddr_t proc0_sp;
vaddr_t kernend;
psize_t sz;
@ -210,24 +204,16 @@ machine_startup(int argc, char *argv[], struct bootinfo *bi)
platid.dw.dw1 = bootinfo->platid_machine;
}
/* CPU initialize */
if (platid_match(&platid, &platid_mask_CPU_SH_3))
sh_cpu_init(CPU_ARCH_SH3, CPU_PRODUCT_7709A);
else if (platid_match(&platid, &platid_mask_CPU_SH_4))
sh_cpu_init(CPU_ARCH_SH4, CPU_PRODUCT_7750);
__sh_BBRA = CPU_IS_SH3 ? 0xffffffb8 : 0xff200008; //XXX
/* ICU initiailze */
switch (cpu_product) {
case CPU_PRODUCT_7709:
/* FALLTHROUGH */
case CPU_PRODUCT_7709A:
_reg_write_2(0xfffffee2, 0); /* IPRA */
_reg_write_2(0xfffffee4, 0); /* IPRB */
_reg_write_2(0xa4000016, 0); /* IPRC */
_reg_write_2(0xa4000018, 0); /* IPRD */
_reg_write_2(0xa400001a, 0); /* IPRE */
/* FALLTHROUGH */
case CPU_PRODUCT_7709:
_reg_write_2(0xfffffee2, 0); /* IPRA */
_reg_write_2(0xfffffee4, 0); /* IPRB */
break;
case CPU_PRODUCT_7750:
_reg_write_2(0xffd00004, 0); /* IPRA */
@ -239,6 +225,12 @@ machine_startup(int argc, char *argv[], struct bootinfo *bi)
hd64465_intr_disable();
#endif
/* CPU initialize */
if (platid_match(&platid, &platid_mask_CPU_SH_3))
sh_cpu_init(CPU_ARCH_SH3, CPU_PRODUCT_7709A);
else if (platid_match(&platid, &platid_mask_CPU_SH_4))
sh_cpu_init(CPU_ARCH_SH4, CPU_PRODUCT_7750);
/* Start to determine heap area */
kernend = (vaddr_t)sh3_round_page(end + symbolsize);
@ -343,13 +335,6 @@ machine_startup(int argc, char *argv[], struct bootinfo *bi)
/* set PageDirReg */
SH_MMU_TTB_WRITE((u_int32_t)pagedir);
/* install trap handler */
memcpy(trap_base + 0x100, MonTrap100, MonTrap100_end - MonTrap100);
memcpy(trap_base + 0x600, MonTrap600, MonTrap600_end - MonTrap600);
memcpy(trap_base + 0x400, tlbmisshandler_stub,
tlbmisshandler_stub_end - tlbmisshandler_stub);
__asm__ __volatile__ ("ldc %0, vbr" :: "r"(trap_base));
/* enable MMU */
sh_mmu_start();
@ -396,8 +381,9 @@ machine_startup(int argc, char *argv[], struct bootinfo *bi)
__asm__ __volatile__(
"jmp @%0;"
"mov %1, sp" :: "r"(main), "r"(proc0_sp));
/* NOTREACHED */
while (1)
;
}
void

100
sys/arch/mmeye/mmeye/genassym.cf
View File

@ -1,100 +0,0 @@
# $NetBSD: genassym.cf,v 1.5 2000/06/29 08:07:48 mrg Exp $
#
# Copyright (c) 1995, 1997 Charles M. Hannum. All rights reserved.
# Copyright (c) 1982, 1990 The Regents of the University of California.
# All rights reserved.
#
# This code is derived from software contributed to Berkeley by
# William Jolitz.
#
# Redistribution and use in source and binary forms, with or without
# modification, are permitted provided that the following conditions
# are met:
# 1. Redistributions of source code must retain the above copyright
# notice, this list of conditions and the following disclaimer.
# 2. Redistributions in binary form must reproduce the above copyright
# notice, this list of conditions and the following disclaimer in the
# documentation and/or other materials provided with the distribution.
# 3. All advertising materials mentioning features or use of this software
# must display the following acknowledgement:
# This product includes software developed by the University of
# California, Berkeley and its contributors.
# 4. Neither the name of the University nor the names of its contributors
# may be used to endorse or promote products derived from this software
# without specific prior written permission.
#
# THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
# ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
# IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
# ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
# FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
# DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
# OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
# HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
# LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
# OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
# SUCH DAMAGE.
#
# @(#)genassym.c 5.11 (Berkeley) 5/10/91
#
include "opt_memsize.h"
include <sys/param.h>
include <sys/proc.h>
include <sys/resourcevar.h>
include <sys/device.h>
include <sys/user.h>
include <sys/mbuf.h>
include <uvm/uvm_extern.h>
include <machine/trap.h>
include <machine/pmap.h>
include <machine/vmparam.h>
define SRUN SRUN
define SONPROC SONPROC
define PDSLOT_PTE PDSLOT_PTE
define PDSLOT_APTE PDSLOT_APTE
define PDSLOT_KERN PDSLOT_KERN
define NKPTP_MIN NKPTP_MIN
define NKPTP_MAX NKPTP_MAX
define VM_MAXUSER_ADDRESS (int)VM_MAXUSER_ADDRESS
define P_ADDR offsetof(struct proc, p_addr)
define P_BACK offsetof(struct proc, p_back)
define P_FORW offsetof(struct proc, p_forw)
define P_PRIORITY offsetof(struct proc, p_priority)
define P_STAT offsetof(struct proc, p_stat)
define P_WCHAN offsetof(struct proc, p_wchan)
define P_VMSPACE offsetof(struct proc, p_vmspace)
define P_FLAG offsetof(struct proc, p_flag)
define P_SYSTEM P_SYSTEM
define M_DATA offsetof(struct mbuf, m_data)
define M_LEN offsetof(struct mbuf, m_len)
define M_NEXT offsetof(struct mbuf, m_next)
define V_TRAP offsetof(struct uvmexp, traps)
define V_INTR offsetof(struct uvmexp, intrs)
define PCB_PAGEDIRREG offsetof(struct pcb, pageDirReg)
define PCB_ONFAULT offsetof(struct pcb, pcb_onfault)
define PCB_R15 offsetof(struct pcb, r15)
define PCB_R14 offsetof(struct pcb, r14)
define PCB_KR15 offsetof(struct pcb, kr15)
define TF_SPC offsetof(struct trapframe, tf_spc)
define TF_TRAPNO offsetof(struct trapframe, tf_trapno)
define SIGF_HANDLER offsetof(struct sigframe, sf_handler)
define SIGF_SC offsetof(struct sigframe, sf_sc)
define SC_EFLAGS offsetof(struct sigcontext, sc_ssr)
define IOM_RAM_BEGIN IOM_RAM_BEGIN
define IOM_ROM_BEGIN IOM_ROM_BEGIN

306
sys/arch/mmeye/mmeye/locore.S Normal file
View File

@ -0,0 +1,306 @@
/* $NetBSD: locore.S,v 1.1 2002/02/24 18:19:42 uch Exp $ */
/*-
* Copyright (c) 1993, 1994, 1995, 1997
* Charles M. Hannum. All rights reserved.
* Copyright (c) 1990 The Regents of the University of California.
* All rights reserved.
*
* This code is derived from software contributed to Berkeley by
* William Jolitz.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* 3. All advertising materials mentioning features or use of this software
* must display the following acknowledgement:
* This product includes software developed by the University of
* California, Berkeley and its contributors.
* 4. Neither the name of the University nor the names of its contributors
* may be used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
* SUCH DAMAGE.
*
* @(#)locore.s 7.3 (Berkeley) 5/13/91
*/
#define DIAGNOSTIC 1
#include "opt_ddb.h"
#include "opt_lockdebug.h"
#include "opt_memsize.h"
#include "assym.h"
#include <sh3/locore.h>
#include <sys/errno.h>
#include <sys/syscall.h>
#include <machine/asm.h>
#include <machine/cputypes.h>
#include <machine/param.h>
#include <machine/pte.h>
#include <machine/trap.h>
#define INIT_STACK 0x8c3ff000
#define SHREG_BBRA 0xffffffb8
#define SHREG_EXPEVT 0xffffffd4
#define SHREG_INTEVT 0xffffffd8
#define SHREG_MMUCR 0xffffffe0
#define SHREG_TTB 0xfffffff8
NENTRY(start)
/* Set SP to initial position */
mov.l XLtmpstk, r15
__INTR_MASK_r0_r1
/* Set Register Bank to Bank 0 */
mov.l SR_init, r0
ldc r0, sr
xor r0, r0
mov #SHREG_MMUCR, r2
mov.l r0, @r2 /* MMU OFF */
bra start1
nop
#if 0
mov #0x20, r8
swap.b r8, r8
swap.w r8, r8
not r8, r8
stc sr, r9
and r8, r9
ldc r9, sr /* Change Register Bank to 0 */
#endif
.align 2
SR_init: .long 0x500000F0
start1:
#ifdef ROMIMAGE
/* Initialize BUS State Control Regs. */
mov.l _ROM_START, r3
mov.l _C_LABEL(ram_start), r4
sub r3, r4
/* Set Bus State Controler */
mov.l XLInitializeBsc, r0
sub r4, r0
jsr @r0
nop
/* Move kernel image from ROM area to RAM area */
mov.l ___end, r0
mov.l ___start, r1
mov.l _KERNBASE, r2
sub r2, r0
sub r2, r1
sub r1, r0
add #4, r0 /* size of bytes to be copied */
shlr2 r0 /* number of long word */
mov.l _ROM_START, r3
add r3, r1 /* src address */
mov.l ___start, r3
sub r2, r3
mov.l _C_LABEL(ram_start), r4
add r4, r3 /* dest address */
1:
mov.l @r1+, r4
mov.l r4, @r3
add #4, r3
dt r0 /* decrement and Test */
bf 1b
/* kernel image copy end */
mov.l LXstart_in_RAM, r0
jmp @r0 /* jump to RAM area */
nop
.align 2
LXstart_in_RAM:
.long start_in_RAM
#else
/* Set Bus State Controler */
mov.l XLInitializeBsc, r0
jsr @r0
nop
#endif
start_in_RAM:
mova 1f, r0
mov r0, r4
mov.l XLinitSH3, r0
jsr @r0 /* call initSH3() */
nop
.align 2
1:
mov.l XLmain, r0
jsr @r0 /* call main() */
nop
.align 2
XLInitializeBsc:.long _C_LABEL(InitializeBsc)
___start: .long start
___etext: .long _etext
___end: .long _end
XLtmpstk: .long INIT_STACK
_KERNBASE: .long KERNBASE
_ROM_START: .long IOM_ROM_BEGIN
XLinitSH3: .long _C_LABEL(initSH3)
XLmain: .long _C_LABEL(main)
load_and_reset:
mov.l XL_start_address, r0
mov r0, r8
mov.l @r4+, r1 /* r1 = osimage size */
mov.l @r4+, r2 /* r2 = check sum */
shlr2 r1 /* r1 = osimage size in dword */
1:
mov.l @r4+, r3
mov.l r3, @r0
add #4, r0
dt r1
bf 1b
jmp @r8 /* jump to start address */
nop
.align 2
XL_start_address:
.long IOM_RAM_BEGIN + 0x00010000
load_and_reset_end:
ENTRY(XLoadAndReset)
__INTR_MASK_r0_r1
/* copy trampoline code to RAM area top */
mov.l XL_load_and_reset, r0
mov.l XL_load_and_reset_end, r1
mov.l XL_load_trampoline_addr, r2
mov r2, r8
sub r0, r1 /* r1 = bytes to be copied */
1: mov.b @r0+, r3
mov.b r3, @r2
add #1, r2
dt r1
bf 1b
jmp @r8 /* jump to trampoline code */
nop
.align 2
XL_load_trampoline_addr:
.long IOM_RAM_BEGIN + 0x00008000
XL_load_and_reset:
.long load_and_reset
XL_load_and_reset_end:
.long load_and_reset_end
ENTRY(Sh3Reset)
mov.l XL_reset_vector, r8
jmp @r8
nop
.align 2
XL_reset_vector:
.long 0xa0000000
/*
* void interrupt_exp(int, int, int, int, stuct trapframe)
* __attribute__((__noreturn__)):
* on entry, SR.BL = 1, SR_RB = 0, all regsiters are saved,
* stack is already setuped.
*/
.align 2
recurse:
stc sr, r4
ldc r5, spc
ldc r4, ssr
RECURSEENTRY
bra 1f
nop
NENTRY(interrupt_exp)
1:
MOV (INTEVT, r0)
mov.l @r0, r0
mov.l r0, @(TF_TRAPNO, r15) /* trapframe->tf_trapno = INTEVT */
__INTR_MASK_r0_r1 /* mask all interrupt */
__EXCEPTION_UNBLOCK_r0_r1 /* enable exception for TLB handling */
mov.l _L.intrhandler, r0
jsr @r0
nop
tst r0, r0 /* intrhandler() == 0, fast intr return */
bt 2f
mov.l _L.check_ipending, r0
jsr @r0
nop
tst r0, r0
bf 1b /* handle pending interrupt. */
/* Check for ASTs on exit to user mode. */
mov.l _L.ast, r0
jsr @r0
mov r15, r4
2:
EXCEPTION_RETURN
/* NOTREACHED */
.align 2
REG_SYMBOL(INTEVT)
_L.intrhandler: .long _C_LABEL(intrhandler)
_L.ast: .long _C_LABEL(ast)
NENTRY(Xspllower)
sts.l pr, @-r15
restart:
__INTR_MASK_r0_r1
__EXCEPTION_UNBLOCK_r0_r1
mov.l _L.check_ipending, r0
jsr @r0
nop
tst r0, r0
bt 1f
mov.l _L.restart, r5
mov.l _L.recurse, r0
jmp @r0
nop
1:
__INTR_UNMASK_r0_r1
lds.l @r15+, pr
rts
nop
.align 2
_L.check_ipending: .long _C_LABEL(check_ipending)
_L.recurse: .long recurse
_L.restart: .long restart
.data
.align 2
.globl _C_LABEL(intrcnt), _C_LABEL(eintrcnt)
.globl _C_LABEL(intrnames), _C_LABEL(eintrnames)
_C_LABEL(intrcnt):
_C_LABEL(eintrcnt):
_C_LABEL(intrnames):
_C_LABEL(eintrnames):

1411
sys/arch/mmeye/mmeye/locore.s
View File

File diff suppressed because it is too large Load Diff

23
sys/arch/mmeye/mmeye/machdep.c
View File

@ -1,4 +1,4 @@
/* $NetBSD: machdep.c,v 1.17 2002/02/19 17:21:20 uch Exp $ */
/* $NetBSD: machdep.c,v 1.18 2002/02/24 18:19:42 uch Exp $ */
/*-
* Copyright (c) 1996, 1997, 1998 The NetBSD Foundation, Inc.
@ -503,10 +503,7 @@ dumpsys()
#define VADDRSTART VM_MIN_KERNEL_ADDRESS
extern int nkpde;
extern char MonTrap100[], MonTrap100_end[];
extern char MonTrap600[], MonTrap600_end[];
extern char _start[], etext[], edata[], end[];
extern char tlbmisshandler_stub[], tlbmisshandler_stub_end[];
extern char start[], etext[], edata[], end[];
void
initSH3(pc)
@ -538,13 +535,6 @@ initSH3(pc)
sh_cpu_init(CPU_ARCH_SH3, CPU_PRODUCT_UNKNOWN);
/*
* install trap handler
*/
memcpy(Trap100Vec, MonTrap100, MonTrap100_end - MonTrap100);
memcpy(Trap600Vec, MonTrap600, MonTrap600_end - MonTrap600);
__asm ("ldc %0, vbr" :: "r"(VBRINIT));
/*
* edata end
* +-------------+------+-----+----------+-------------+------------+
@ -583,11 +573,6 @@ initSH3(pc)
/* set PageDirReg */
SH_MMU_TTB_WRITE((u_int32_t)pagedir);
/* Set TLB miss handler */
p = tlbmisshandler_stub;
x = tlbmisshandler_stub_end - p;
memcpy(TLBVECTOR, p, x);
/*
* Activate MMU
*/
@ -661,8 +646,8 @@ initSH3(pc)
u_short *p, sum;
int size;
size = etext - _start;
p = (u_short *)_start;
size = etext - start;
p = (u_short *)start;
sum = 0;
size >>= 1;
while (size--)

4
sys/arch/sh3/Makefile.inc Normal file
View File

@ -0,0 +1,4 @@
# $NetBSD: Makefile.inc,v 1.1 2002/02/24 18:19:43 uch Exp $
SSH3= ../sh3/sh3/*.[ch] ../sh3/include/*.h ../sh3/dev/*.[ch]
ASH3= ../sh3/sh3/*.S

8
sys/arch/sh3/conf/Makefile.sh3
View File

@ -1,4 +1,4 @@
# $NetBSD: Makefile.sh3,v 1.16 2001/12/09 05:00:50 atatat Exp $
# $NetBSD: Makefile.sh3,v 1.17 2002/02/24 18:19:44 uch Exp $
# Makefile for NetBSD
#
@ -26,7 +26,7 @@ NEED_OWN_INSTALL_TARGET?=no
##
THISSH3= $S/arch/${MACHINE}
SH3= $S/arch/sh3
GENASSYM= ${THISSH3}/${MACHINE}/genassym.cf
GENASSYM= ${SH3}/sh3/genassym.cf
.-include "${THISSH3}/conf/Makefile.${MACHINE}.inc"
##
@ -47,9 +47,9 @@ COPTS?= -O1
##
MD_OBJS= locore.o
MD_CFILES=
MD_SFILES= ${THISSH3}/${MACHINE}/locore.s
MD_SFILES= ${THISSH3}/${MACHINE}/locore.S
locore.o: ${THISSH3}/${MACHINE}/locore.s assym.h
locore.o: ${THISSH3}/${MACHINE}/locore.S assym.h
${NORMAL_S}
# XXX compile ffs_inode.c always with -O0 to avoid egcs-1.1.2 bug.

3
sys/arch/sh3/conf/files.sh3
View File

@ -1,4 +1,4 @@
# $NetBSD: files.sh3,v 1.18 2002/02/22 19:55:33 uch Exp $
# $NetBSD: files.sh3,v 1.19 2002/02/24 18:19:44 uch Exp $
#
# new style config file for sh3 architecture
#
@ -13,6 +13,7 @@ file arch/sh3/sh3/sh3disasm.c ddb
file arch/sh3/sh3/in_cksum.S inet
file netinet/in4_cksum.c inet
file arch/sh3/sh3/kgdb_machdep.c kgdb
file arch/sh3/sh3/exception_vector.S
file arch/sh3/sh3/Locore.c
file arch/sh3/sh3/locore_subr.S
file arch/sh3/sh3/mem.c

15
sys/arch/sh3/include/cpu.h
View File

@ -1,4 +1,4 @@
/* $NetBSD: cpu.h,v 1.18 2002/02/22 19:44:02 uch Exp $ */
/* $NetBSD: cpu.h,v 1.19 2002/02/24 18:19:42 uch Exp $ */
/*-
* Copyright (c) 1990 The Regents of the University of California.
@ -88,17 +88,14 @@ extern struct cpu_info cpu_info_store;
*
* XXX intrframe has a lot of gunk we don't need.
*/
#define clockframe intrframe
#define clockframe trapframe
#define CLKF_USERMODE(frame) (!KERNELMODE((frame)->if_r15, (frame)->if_ssr))
#if 0
#define CLKF_BASEPRI(frame) ((frame)->if_pri == 0)
#else
#define CLKF_USERMODE(frame) (!KERNELMODE((frame)->tf_r15, (frame)->tf_ssr))
/* XXX we should fix this */
#define CLKF_BASEPRI(frame) (0)
#endif
#define CLKF_PC(frame) ((frame)->if_spc)
#define CLKF_INTR(frame) (0) /* XXX should have an interrupt stack */
#define CLKF_PC(frame) ((frame)->tf_spc)
/* XXX we should have an interrupt stack */
#define CLKF_INTR(frame) (0)
/*
* Preempt the current process if in interrupt from user mode,

34
sys/arch/sh3/include/frame.h
View File

@ -1,4 +1,4 @@
/* $NetBSD: frame.h,v 1.2 2000/09/08 10:15:23 tsubai Exp $ */
/* $NetBSD: frame.h,v 1.3 2002/02/24 18:19:42 uch Exp $ */
/*-
* Copyright (c) 1995 Charles M. Hannum. All rights reserved.
@ -52,8 +52,10 @@
* Exception/Trap Stack Frame
*/
struct trapframe {
/* software member */
int tf_trapno;
int tf_ubc;
/* hardware registers */
int tf_spc;
int tf_ssr;
int tf_macl;
@ -77,36 +79,6 @@ struct trapframe {
int tf_r15;
};
/*
* Interrupt stack frame
*/
struct intrframe {
int if_trapno;
int dummy;
int if_spc;
int if_ssr;
int if_macl;
int if_mach;
int if_pr;
int if_r14;
int if_r13;
int if_r12;
int if_r11;
int if_r10;
int if_r9;
int if_r8;
int if_r7;
int if_r6;
int if_r5;
int if_r4;
int if_r3;
int if_r2;
int if_r1;
int if_r0;
int if_r15;
int if_pri;
};
/*
* Stack frame inside cpu_switch()
*/

221
sys/arch/sh3/include/locore.h Normal file
View File

@ -0,0 +1,221 @@
/* $NetBSD: locore.h,v 1.1 2002/02/24 18:19:42 uch Exp $ */
/*-
* Copyright (c) 2002 The NetBSD Foundation, Inc.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* 3. All advertising materials mentioning features or use of this software
* must display the following acknowledgement:
* This product includes software developed by the NetBSD
* Foundation, Inc. and its contributors.
* 4. Neither the name of The NetBSD Foundation nor the names of its
* contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
* ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
* TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
* BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*/
/* XXX XXX XXX */
#define SH3_BBRA 0xffffffb8
#define SH4_BBRA 0xff200008
#define SH3_EXPEVT 0xffffffd4
#define SH3_INTEVT 0xffffffd8
#define SH4_EXPEVT 0xff000024
#define SH4_INTEVT 0xff000028
/* XXX XXX XXX */
#if defined(SH3) && defined(SH4)
#define MOV(x, r) mov.l _L./**/x, r; mov.l @r, r
#define REG_SYMBOL(x) _L./**/x: .long _C_LABEL(__sh_/**/x)
#define FUNC_SYMBOL(x) _L./**/x: .long _C_LABEL(__sh_/**/x)
#elif defined(SH3)
#define MOV(x, r) mov.l _L./**/x, r
#define REG_SYMBOL(x) _L./**/x: .long SH3_/**/x
#define FUNC_SYMBOL(x) _L./**/x: .long _C_LABEL(sh3_/**/x)
#elif defined(SH4)
#define MOV(x, r) mov.l _L./**/x, r
#define REG_SYMBOL(x) _L./**/x: .long SH4_/**/x
#define FUNC_SYMBOL(x) _L./**/x: .long _C_LABEL(sh4_/**/x)
#endif
/*
* BANK1 r7 contains kernel stack top address.
*/
/*
* EXCEPTION_ENTRY:
* + setup stack pointer
* + save all register to stack. (struct trapframe)
* + change bank from 1 to 0
* + set BANK0 (r4, r5) = (ssr, spc)
*/
#define EXCEPTION_ENTRY ;\
/* Check kernel/user mode. */ ;\
mov #0x40, r3 ;\
swap.b r3, r3 ;\
stc ssr, r1 ;\
swap.w r3, r3 /* r3 = 0x40000000 */ ;\
mov r1, r0 /* r1 = r0 = SSR */ ;\
and r3, r0 ;\
tst r0, r0 /* if (SSR.MD == 0) T = 1 */ ;\
bf/s 1f /* T==0 ...Exception from kernel mode */;\
mov r15, r0 /* r0 = old stack */ ;\
/* Exception from user mode */ ;\
mov r7, r15 /* change to kernel stack */ ;\
1: ;\
/* Save registers */ ;\
mov.l r0, @-r15 /* tf_r15 */ ;\
stc.l r0_bank,@-r15 /* tf_r0 */ ;\
stc.l r1_bank,@-r15 /* tf_r1 */ ;\
stc.l r2_bank,@-r15 /* tf_r2 */ ;\
stc.l r3_bank,@-r15 /* tf_r3 */ ;\
stc.l r4_bank,@-r15 /* tf_r4 */ ;\
stc.l r5_bank,@-r15 /* tf_r5 */ ;\
stc.l r6_bank,@-r15 /* tf_r6 */ ;\
stc.l r7_bank,@-r15 /* tf_r7 */ ;\
mov.l r8, @-r15 /* tf_r8 */ ;\
mov.l r9, @-r15 /* tf_r9 */ ;\
mov.l r10, @-r15 /* tf_r10 */ ;\
mov.l r11, @-r15 /* tf_r11 */ ;\
mov.l r12, @-r15 /* tf_r12 */ ;\
mov.l r13, @-r15 /* tf_r13 */ ;\
mov.l r14, @-r15 /* tf_r14 */ ;\
sts.l pr, @-r15 /* tf_pr */ ;\
sts.l mach, @-r15 /* tf_mach*/ ;\
sts.l macl, @-r15 /* tf_macl*/ ;\
mov.l r1, @-r15 /* tf_ssr */ ;\
stc.l spc, @-r15 /* tf_spc */ ;\
add #-8, r15 /* skip tf_ubc, tf_trapno */ ;\
/* Change register bank to 0 */ ;\
shlr r3 /* r3 = 0x20000000 */ ;\
stc sr, r0 /* r0 = SR */ ;\
not r3, r3 ;\
and r0, r3 ;\
ldc r3, sr /* SR.RB = 0 */ ;\
/* Set up argument. r4 = ssr, r5 = spc */ ;\
stc r1_bank,r4 ;\
stc spc, r5
/*
* EXCEPTION_RETURN:
* + block exception
* + restore all register from stack.
* + rte.
*/
#define EXCEPTION_RETURN ;\
mov #0x10, r0 ;\
swap.b r0, r0 ;\
swap.w r0, r0 /* r0 = 0x10000000 */ ;\
stc sr, r1 ;\
or r0, r1 ;\
ldc r1, sr /* SR.BL = 1 */ ;\
add #8, r15 /* skip tf_trapno, tf_ubc */ ;\
mov.l @r15+, r0 /* tf_spc */ ;\
ldc r0, spc ;\
mov.l @r15+, r0 /* tf_ssr */ ;\
ldc r0, ssr ;\
lds.l @r15+, macl /* tf_macl*/ ;\
lds.l @r15+, mach /* tf_mach*/ ;\
lds.l @r15+, pr /* tf_pr */ ;\
mov.l @r15+, r14 /* tf_r14 */ ;\
mov.l @r15+, r13 /* tf_r13 */ ;\
mov.l @r15+, r12 /* tf_r12 */ ;\
mov.l @r15+, r11 /* tf_r11 */ ;\
mov.l @r15+, r10 /* tf_r10 */ ;\
mov.l @r15+, r9 /* tf_r9 */ ;\
mov.l @r15+, r8 /* tf_r8 */ ;\
mov.l @r15+, r7 /* tf_r7 */ ;\
mov.l @r15+, r6 /* tf_r6 */ ;\
mov.l @r15+, r5 /* tf_r5 */ ;\
mov.l @r15+, r4 /* tf_r4 */ ;\
mov.l @r15+, r3 /* tf_r3 */ ;\
mov.l @r15+, r2 /* tf_r2 */ ;\
mov.l @r15+, r1 /* tf_r1 */ ;\
mov.l @r15+, r0 /* tf_r0 */ ;\
mov.l @r15, r15 /* tf_r15 */ ;\
rte ;\
nop
/*
* Macros to disable and enable exceptions (including interrupts).
* This modifies SR.BL
*/
#define __EXCEPTION_BLOCK_r0_r1 ;\
mov #0x10, r0 ;\
swap.b r0, r0 ;\
swap.w r0, r0 /* r0 = 0x10000000 */ ;\
stc sr, r1 ;\
or r0, r1 ;\
ldc r1, sr /* block exceptions */
#define __EXCEPTION_UNBLOCK_r0_r1 ;\
mov #0x10, r0 ;\
swap.b r0, r0 ;\
swap.w r0, r0 /* r0 = 0x10000000 */ ;\
not r0, r0 ;\
stc sr, r1 ;\
and r0, r1 ;\
ldc r1, sr /* unblock exceptions */
/*
* Macros to disable and enable interrupts.
* This modifies SR.I[0-3]
*/
#define __INTR_MASK_r0_r1 ;\
mov #0x78, r0 ;\
shll r0 /* r0 = 0x000000f0 */ ;\
stc sr, r1 ;\
or r0, r1 ;\
ldc r1, sr /* mask all interrupt */
#define __INTR_UNMASK_r0_r1 ;\
mov #0x78, r0 ;\
shll r0 /* r0 = 0x000000f0 */ ;\
not r0, r0 ;\
stc sr, r1 ;\
and r0, r1 ;\
ldc r1, sr /* unmask all interrupt */
#define RECURSEENTRY ;\
mov r15, r0 ;\
mov.l r0, @-r15 ;\
mov.l r0, @-r15 ;\
mov.l r1, @-r15 ;\
mov.l r2, @-r15 ;\
mov.l r3, @-r15 ;\
mov.l r4, @-r15 ;\
mov.l r5, @-r15 ;\
mov.l r6, @-r15 ;\
mov.l r7, @-r15 ;\
mov.l r8, @-r15 ;\
mov.l r9, @-r15 ;\
mov.l r10, @-r15 ;\
mov.l r11, @-r15 ;\
mov.l r12, @-r15 ;\
mov.l r13, @-r15 ;\
mov.l r14, @-r15 ;\
sts.l pr, @-r15 ;\
sts.l mach, @-r15 ;\
sts.l macl, @-r15 ;\
stc.l ssr, @-r15 ;\
stc.l spc, @-r15 ;\
add #-8, r15 /* tf_ubc, tf_trapno */

163
sys/arch/sh3/sh3/exception_vector.S Normal file
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@ -0,0 +1,163 @@
/* $NetBSD: exception_vector.S,v 1.1 2002/02/24 18:19:43 uch Exp $ */
/*-
* Copyright (c) 2002 The NetBSD Foundation, Inc.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* 3. All advertising materials mentioning features or use of this software
* must display the following acknowledgement:
* This product includes software developed by the NetBSD
* Foundation, Inc. and its contributors.
* 4. Neither the name of The NetBSD Foundation nor the names of its
* contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
* ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
* TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
* BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*/
#include "assym.h"
#include <sh3/asm.h>
#include <sh3/locore.h>
/*
* Exception vectors. following routines are copied to vector addreses.
* sh_vector_generic: VBR + 0x100
* sh_vector_tlbmiss: VBR + 0x400
* sh_vector_interrupt: VBR + 0x600
*/
/*
* void sh_vector_generic(void) __attribute__((__noreturn__)):
* copied to VBR+0x100. This code should be relocatable and max 384
* instructions.
* 0x40 TLB miss (load)
* 0x60 TLB miss (store)
* 0xc0 TLB protection (store)
* -> tlbmiss_exp()
* 0xa0 TLB protection (load)
* 0x80 Initial page write.
* and other...
* -> trap()
*/
.globl _C_LABEL(sh_vector_generic), _C_LABEL(sh_vector_generic_end)
.align 2
_C_LABEL(sh_vector_generic):
EXCEPTION_ENTRY
/* Identify exception cause */
MOV (EXPEVT, r0)
mov.l @r0, r0
/*
* TLB exception.
*/
cmp/eq #0x40, r0 /* T_TLBINVALIDR */
bf 1f
3:
__INTR_MASK_r0_r1
__EXCEPTION_UNBLOCK_r0_r1
mov.l _L.tlb_handler, r0
jsr @r0
nop
bra 4f
nop
1:
cmp/eq #0x60, r0 /* T_TLBINVALIDW */
bt 3b
mov.l _L.TLBPROTWR, r1 /* T_TLBPRIVW */
cmp/eq r0, r1
bt 3b
/*
* General exception.
*/
#ifdef DDB
mov #0, r2
MOV (BBRA, r1)
mov.w r2, @r1 /* disable UBC */
mov.l r2, @(TF_UBC, r15) /* clear trapframe->tf_ubc */
#endif /* DDB */
mov.l r0, @(TF_TRAPNO, r15) /* trapframe->tf_trapno = EXPEVT */
__INTR_UNMASK_r0_r1
__EXCEPTION_UNBLOCK_r0_r1
mov.l _L.trap, r0
jsr @r0
mov r15, r4
/* Check for ASTs on exit to user mode. */
mov.l _L.ast, r0
jsr @r0
mov r15, r4
#ifdef DDB /* BBRA = trapframe->tf_ubc */
__EXCEPTION_BLOCK_r0_r1
mov.l @(TF_UBC, r15), r0
MOV (BBRA, r1)
mov.w r0, @r1
#endif /* DDB */
4:
EXCEPTION_RETURN
/* NOTREACHED */
.align 2
REG_SYMBOL(EXPEVT)
REG_SYMBOL(BBRA)
_L.TLBPROTWR: .long 0x000000c0
_L.trap: .long _C_LABEL(trap)
_L.ast: .long _C_LABEL(ast)
_L.tlb_handler: .long _C_LABEL(tlb_handler)
_C_LABEL(sh_vector_generic_end):
/*
* void sh_vector_tlbmiss(void) __attribute__((__noreturn__)):
* copied to VBR+0x400. This code should be relocatable and max 256
* instructions.
*/
.globl _C_LABEL(sh_vector_tlbmiss), _C_LABEL(sh_vector_tlbmiss_end)
.align 2
_C_LABEL(sh_vector_tlbmiss):
EXCEPTION_ENTRY
__INTR_MASK_r0_r1
__EXCEPTION_UNBLOCK_r0_r1
mov.l 1f, r0
jsr @r0
nop
EXCEPTION_RETURN
.align 2
1: .long _C_LABEL(tlb_handler)
_C_LABEL(sh_vector_tlbmiss_end):
/*
* void sh_vector_interrupt(void) __attribute__((__noreturn__)):
* copied to VBR+0x600. This code should be relocatable.
*/
.globl _C_LABEL(sh_vector_interrupt), _C_LABEL(sh_vector_interrupt_end)
.align 2
_C_LABEL(sh_vector_interrupt):
EXCEPTION_ENTRY
mov.l 1f, r0
jmp @r0
nop
.align 2
1: .long _C_LABEL(interrupt_exp)
_C_LABEL(sh_vector_interrupt_end):

91
sys/arch/sh3/sh3/genassym.cf Normal file
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@ -0,0 +1,91 @@
# $NetBSD: genassym.cf,v 1.1 2002/02/24 18:19:43 uch Exp $
#-
# Copyright (c) 2002 The NetBSD Foundation, Inc.
# All rights reserved.
#
# Redistribution and use in source and binary forms, with or without
# modification, are permitted provided that the following conditions
# are met:
# 1. Redistributions of source code must retain the above copyright
# notice, this list of conditions and the following disclaimer.
# 2. Redistributions in binary form must reproduce the above copyright
# notice, this list of conditions and the following disclaimer in the
# documentation and/or other materials provided with the distribution.
# 3. All advertising materials mentioning features or use of this software
# must display the following acknowledgement:
# This product includes software developed by the NetBSD
# Foundation, Inc. and its contributors.
# 4. Neither the name of The NetBSD Foundation nor the names of its
# contributors may be used to endorse or promote products derived
# from this software without specific prior written permission.
#
# THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
# ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
# TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
# PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
# BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
# CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
# SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
# INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
# CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
# ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
# POSSIBILITY OF SUCH DAMAGE.
#
include <sys/param.h>
include <sys/proc.h>
include <sys/signal.h>
include <sys/mbuf.h>
include <sh3/pcb.h>
include <sh3/locore.h>
define TF_SIZE sizeof(struct trapframe)
define TF_TRAPNO offsetof(struct trapframe, tf_trapno)
define TF_UBC offsetof(struct trapframe, tf_ubc)
define TF_SPC offsetof(struct trapframe, tf_spc)
define TF_SSR offsetof(struct trapframe, tf_ssr)
define TF_MACL offsetof(struct trapframe, tf_macl)
define TF_MACH offsetof(struct trapframe, tf_mach)
define TF_PR offsetof(struct trapframe, tf_pr)
define TF_R14 offsetof(struct trapframe, tf_r14)
define TF_R13 offsetof(struct trapframe, tf_r13)
define TF_R12 offsetof(struct trapframe, tf_r12)
define TF_R11 offsetof(struct trapframe, tf_r11)
define TF_R10 offsetof(struct trapframe, tf_r10)
define TF_R9 offsetof(struct trapframe, tf_r9)
define TF_R8 offsetof(struct trapframe, tf_r8)
define TF_R7 offsetof(struct trapframe, tf_r7)
define TF_R6 offsetof(struct trapframe, tf_r6)
define TF_R5 offsetof(struct trapframe, tf_r5)
define TF_R4 offsetof(struct trapframe, tf_r4)
define TF_R3 offsetof(struct trapframe, tf_r3)
define TF_R2 offsetof(struct trapframe, tf_r2)
define TF_R1 offsetof(struct trapframe, tf_r1)
define TF_R0 offsetof(struct trapframe, tf_r0)
define TF_R15 offsetof(struct trapframe, tf_r15)
define P_ADDR offsetof(struct proc, p_addr)
define P_BACK offsetof(struct proc, p_back)
define P_FORW offsetof(struct proc, p_forw)
define P_STAT offsetof(struct proc, p_stat)
define P_WCHAN offsetof(struct proc, p_wchan)
define PCB_PAGEDIRREG offsetof(struct pcb, pageDirReg)
define PCB_R15 offsetof(struct pcb, r15)
define PCB_KR15 offsetof(struct pcb, kr15)
define SIGF_HANDLER offsetof(struct sigframe, sf_handler)
define SIGF_SC offsetof(struct sigframe, sf_sc)
define SC_EFLAGS offsetof(struct sigcontext, sc_ssr)
# can't include sys/proc.h directly.
define SONPROC SONPROC
define SRUN SRUN
#
# in_cksum.S
#
define M_DATA offsetof(struct mbuf, m_data)
define M_LEN offsetof(struct mbuf, m_len)
define M_NEXT offsetof(struct mbuf, m_next)

685
sys/arch/sh3/sh3/locore_subr.S
View File

@ -1,4 +1,4 @@
/* $NetBSD: locore_subr.S,v 1.2 2002/02/22 19:44:04 uch Exp $ */
/* $NetBSD: locore_subr.S,v 1.3 2002/02/24 18:19:43 uch Exp $ */
/*-
* Copyright (c) 2002 The NetBSD Foundation, Inc.
@ -32,11 +32,60 @@
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*/
/*-
* Copyright (c) 1993, 1994, 1995, 1997
* Charles M. Hannum. All rights reserved.
* Copyright (c) 1990 The Regents of the University of California.
* All rights reserved.
*
* This code is derived from software contributed to Berkeley by
* William Jolitz.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* 3. All advertising materials mentioning features or use of this software
* must display the following acknowledgement:
* This product includes software developed by the University of
* California, Berkeley and its contributors.
* 4. Neither the name of the University nor the names of its contributors
* may be used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
* SUCH DAMAGE.
*
* @(#)locore.s 7.3 (Berkeley) 5/13/91
*/
#include "opt_ddb.h"
#include "opt_kgdb.h"
#include <machine/asm.h>
#include "assym.h"
#include <sh3/asm.h>
#include <sh3/locore.h>
#include <sys/syscall.h>/* SYS___sigreturn14, SYS_exit */
#include <sh3/trap.h> /* T_ASTFLT */
#include <sh3/param.h> /* NBPG */
#include <sh3/pte.h> /* PDSHIFT */
#include <sh3/mmu_sh3.h>
#include <sh3/mmu_sh4.h>
.text
.align 5 /* align cache line size (32B) */
@ -167,3 +216,635 @@ ENTRY(longjmp)
rts
nop
#endif /* DDB || KGDB */
/*
* Call the service funciton with one argument specified by the r12 and r11
* respectively.
*/
NENTRY(proc_trampoline)
jsr @r12
mov r11, r4
EXCEPTION_RETURN
/* NOTREACHED */
/*
* Signal trampoline; copied to top of user stack.
*/
.globl _C_LABEL(esigcode)
NENTRY(sigcode)
mov r15, r0
mov.l @r0, r4 /* sig_no param */
add #SIGF_HANDLER, r0
mov.l @r0, r0
jsr @r0
nop
mov r15, r0
add #SIGF_SC, r0
mov.l r0, @-r15 /* junk to fake return address */
mov r0, r4
mov.l _L.SYS___sigreturn14, r0
trapa #0x80 /* enter kernel with args on stack */
mov.l _L.SYS_exit, r0
trapa #0x80 /* exit if sigreturn fails */
.align 2
_L.SYS___sigreturn14: .long SYS___sigreturn14
_L.SYS_exit: .long SYS_exit
_C_LABEL(esigcode):
/*
* The following primitives manipulate the run queues.
* _whichqs tells which of the 32 queues _qs
* have processes in them. Setrq puts processes into queues, Remrq
* removes them from queues. The running process is on no queue,
* other processes are on a queue related to p->p_pri, divided by 4
* actually to shrink the 0-127 range of priorities into the 32 available
* queues.
*/
/*
* When no processes are on the runq, cpu_switch() branches to here to wait for
* something to come ready.
*/
ENTRY(idle)
/*
* When we get here, interrupts are off (via INTR_DISABLE) and
* sched_lock is held.
*/
mov.l X_L.sched_whichqs, r0
mov.l @r0, r0
mov r0, r14
tst r0, r0
bf sw1
#if defined(LOCKDEBUG)
mov.l _L.sched_unlock, r0
jsr @r0
nop
#endif
__INTR_UNMASK_r0_r1
sleep
__INTR_MASK_r0_r1
#if defined(LOCKDEBUG)
mov.l _L.sched_lock, r0
jsr @r0
nop
#endif
bra _C_LABEL(idle)
nop
.align 2
X_L.sched_whichqs: .long _C_LABEL(sched_whichqs)
/*
* void cpu_switch(struct proc *)
* Find a runnable process and switch to it. Wait if necessary. If the new
* process is the same as the old one, we short-circuit the context save and
* restore.
*/
#ifdef DIAGNOSTIC
switch_error:
mova 1f, r0
mov r0, r4
mov.l 2f, r0
jsr @r0
nop
.align 2
1: .asciz "cpu_switch"
.align 2
2: .long _C_LABEL(panic)
#endif /* DIAGNOSTIC */
ENTRY(cpu_switch)
sts.l pr, @-r15
mov.l r8, @-r15
mov.l r9, @-r15
mov.l r10, @-r15
mov.l r11, @-r15
mov.l r12, @-r15
mov.l r13, @-r15
mov.l r14, @-r15
mov.l X_L.cpl, r0
mov.l @r0, r0
mov.l r0, @-r15
mov.l X_L.curproc, r12
mov.l @r12, r12
tst r12, r12
bt 1f
/* Save stack pointers. */
mov r12, r4
mov.l _L.P_ADDR, r1
add r1, r4
MOV (mmu_pt_kaddr, r0)
jsr @r0
nop
mov.l @r0, r4 /* r4 = oldCurproc->p_addr */
mov #PCB_R15, r1
add r1, r4
MOV (mmu_pt_kaddr, r0)
jsr @r0
nop
mov.l r15, @r0
1:
/*
* Clear curproc so that we don't accumulate system time while idle.
* This also insures that schedcpu() will move the old process to
* the correct queue if it happens to get called from the spllower()
* below and changes the priority. (See corresponding comment in
* userret()).
*/
xor r0, r0
mov.l X_L.curproc, r1
mov.l r0, @r1
#if defined(LOCKDEBUG)
/* Release the sched_lock before processing interrupts. */
mov.l _L.sched_unlock, r0
jsr @r0
nop
#endif
xor r0, r0
mov.l X_L.cpl, r1
mov.l r0, @r1 /* spl0() */
mov.l X_L.Xspllower, r0
jsr @r0
nop
switch_search:
/*
* First phase: find new process.
*
* Registers:
* r0 - queue head, scratch, then zero
* r13 - queue number
* r14 - cached value of whichqs
* r9 - next process in queue
* r12 - old process
* r8 - new process
*/
/* Lock the scheduler. */
__INTR_MASK_r0_r1
#if defined(LOCKDEBUG)
mov.l _L.sched_lock, r0
jsr @r0
nop
#endif
/* Wait for new process. */
mov.l _L.sched_whichqs, r0
mov.l @r0, r0
mov r0, r14
#define TESTANDSHIFT \
tst r1, r0 ; \
bf 1f ; \
shll r1 ; \
add #1, r2
sw1: mov #1, r1
xor r2, r2
TESTANDSHIFT /* bit 0 */
TESTANDSHIFT /* bit 1 */
TESTANDSHIFT /* bit 2 */
TESTANDSHIFT /* bit 3 */
TESTANDSHIFT /* bit 4 */
TESTANDSHIFT /* bit 5 */
TESTANDSHIFT /* bit 6 */
TESTANDSHIFT /* bit 7 */
TESTANDSHIFT /* bit 8 */
TESTANDSHIFT /* bit 9 */
TESTANDSHIFT /* bit 10 */
TESTANDSHIFT /* bit 11 */
TESTANDSHIFT /* bit 12 */
TESTANDSHIFT /* bit 13 */
TESTANDSHIFT /* bit 14 */
TESTANDSHIFT /* bit 15 */
TESTANDSHIFT /* bit 16 */
TESTANDSHIFT /* bit 17 */
TESTANDSHIFT /* bit 18 */
TESTANDSHIFT /* bit 19 */
TESTANDSHIFT /* bit 20 */
TESTANDSHIFT /* bit 21 */
TESTANDSHIFT /* bit 22 */
TESTANDSHIFT /* bit 23 */
TESTANDSHIFT /* bit 24 */
TESTANDSHIFT /* bit 25 */
TESTANDSHIFT /* bit 26 */
TESTANDSHIFT /* bit 27 */
TESTANDSHIFT /* bit 28 */
TESTANDSHIFT /* bit 29 */
TESTANDSHIFT /* bit 30 */
TESTANDSHIFT /* bit 31 */
bra _C_LABEL(idle) /* if none, idle */
nop
1: mov.l _L.sched_qs, r0
mov r2, r13
shll2 r2
shll r2
add r2, r0 /* r0 = &qs[i] */
mov r0, r2
mov #P_FORW, r1
add r1, r2
ldc r0, r0_bank /* save r0 = &qs[i] */
mov r2, r4
mov.l r1, @-r15
MOV (mmu_pt_kaddr, r0)
jsr @r0
nop
mov.l @r15+, r1
mov r0, r2
mov.l @r2, r8 /* r8 = qs[i].p_forw */
#ifdef DIAGNOSTIC
stc r0_bank, r0
cmp/eq r0, r8 /* linked to self (i.e. nothing queued)? */
bf 10f
mov.l _L._switch_error, r0
jmp @r0
nop
10:
#endif /* DIAGNOSTIC */
mov r8, r3
add r1, r3
mov r3, r4
mov.l r2, @-r15
MOV (mmu_pt_kaddr, r0)
jsr @r0
nop
mov.l @r15+, r2
mov r0, r3
mov.l @r3, r9 /* r9 = qs[i].p_forw->p_forw */
mov.l r9, @r2 /* qs[i].p_forw = qs[i].p_forw->p_forw */
mov r9, r4
mov #P_BACK, r2
add r2, r4
MOV (mmu_pt_kaddr, r0)
jsr @r0
nop
mov r0, r10
stc r0_bank, r0
mov.l r0, @r10 /* qs[i].p_forw->p_forw->p_back = &qs[i] */
mov r0, r11
sub r9, r11
tst r11, r11
bf 3f /* if r0 != r9 then goto 3f */
mov #1, r0
shld r13, r0
not r0, r0
and r0, r14
mov.l _L.sched_whichqs, r0
mov.l r14, @r0
#ifdef sh3_debug
mova 1f, r0
mov r0, r4
mov r13, r5
mov r14, r6
mov.l 2f, r0
jsr @r0
nop
bra 3f
nop
.align 2
1: .asciz "switch[i=%d,whichqs=0x%0x]\n"
.align 2
2: .long _C_LABEL(printf)
#endif /* sh3_debug */
3:
xor r0, r0
mov.l _L.want_resched, r1
mov.l r0, @r1
#ifdef DIAGNOSTIC
mov r8, r4
add #P_WCHAN, r4
MOV (mmu_pt_kaddr, r0)
jsr @r0
nop
mov.l @r0, r0
tst r0, r0
bt 11f
mov r8, r4
add #P_STAT, r4
MOV (mmu_pt_kaddr, r0)
jsr @r0
nop
mov.b @r0, r0
extu.b r0, r0
mov #SRUN, r1
cmp/eq r0, r1
bt 11f
mov.l _L._switch_error, r0
jmp @r0
nop
.align 2
_L._switch_error:
.long switch_error
11:
#endif /* DIAGNOSTIC */
/* Isolate process. XXX Is this necessary? */
mov r8, r4
mov #P_BACK, r2
add r2, r4
MOV (mmu_pt_kaddr, r0)
jsr @r0
nop
mov r0, r1
xor r0, r0
mov.l r0, @r1 /* r8->p_back = 0 */
#if defined(LOCKDEBUG)
/*
* Unlock the sched_lock, but leave interrupts off, for now.
*/
mov.l _L.sched_unlock, r0
jsr @r0
nop
#endif
/* p->p_cpu initialized in fork1() for single-processor */
/* Process now running on a processor. */
mov #P_STAT, r0
mov #SONPROC, r1
mov.b r1, @(r0, r8) /* p->p_stat = SONPROC */
/* Record new process. */
mov.l _L.curproc, r0
mov.l r8, @r0
/* It's okay to take interrupts here. */
__INTR_UNMASK_r0_r1
/* Skip context switch if same process. */
mov r12, r0 /* r12 = oldCurproc */
sub r8, r0 /* r8 = qs[i]->p_forw */
tst r0, r0
bt switch_return
/* If old process exited, don't bother. */
tst r12, r12
bt switch_exited
/*
* Second phase: save old context.
*/
mov r12, r0
mov.l _L.P_ADDR, r1
add r1, r0
mov.l @r0, r12 /* r12 = oldCurproc->p_addr */
/* Save stack pointers. */
mov r12, r0
add #PCB_R15, r0
mov.l r15, @r0
switch_exited:
/*
* Third phase: restore saved context.
*
*/
/* No interrupts while loading new state. */
__INTR_MASK_r0_r1
mov r8, r4 /* r8 = qs[i]->p_forw */
mov.l _L.P_ADDR, r1
add r1, r4
MOV (mmu_pt_kaddr, r0)
jsr @r0
nop
mov.l @r0, r12
/* Restore stack pointers. */
mov r12, r4
add #PCB_R15, r4
MOV (mmu_pt_kaddr, r0)
jsr @r0
nop
mov.l @r0, r15
/* Store new kernel mode stack pointer */
mov r12, r4
add #PCB_KR15, r4
MOV (mmu_pt_kaddr, r0)
jsr @r0
nop
mov.l @r0, r0
ldc r0, r7_bank /* set kernel stack pointer */
/* Switch address space. */
mov r12, r4
add #PCB_PAGEDIRREG, r4
MOV (mmu_pt_kaddr, r0)
jsr @r0
nop
mov.l @r0, r0
MOV (TTB, r2)
mov.l r0, @r2
/* flush TLB */
MOV (tlb_invalidate_all, r0)
jsr @r0
nop
switch_restored:
/* Record new pcb. */
mov.l _L.curpcb, r0
mov.l r12, @r0
/* Interrupts are okay again. */
__INTR_UNMASK_r0_r1
switch_return:
/*
* Restore old cpl from stack. Note that this is always an increase,
* due to the spl0() on entry.
*/
mov.l @r15+, r0
mov.l _L.cpl, r1
mov.l r0, @r1
mov r8, r0 /* return (p); */
mov.l @r15+, r14
mov.l @r15+, r13
mov.l @r15+, r12
mov.l @r15+, r11
mov.l @r15+, r10
mov.l @r15+, r9
mov.l @r15+, r8
lds.l @r15+, pr
rts
nop
.align 2
X_L.cpl: .long _C_LABEL(cpl)
X_L.curproc: .long _C_LABEL(curproc)
X_L.Xspllower: .long _C_LABEL(Xspllower)
_L.sched_qs: .long _C_LABEL(sched_qs)
_L.sched_whichqs: .long _C_LABEL(sched_whichqs)
_L.want_resched: .long _C_LABEL(want_resched)
#if defined(SH3) && defined(SH4)
_L.mmu_pt_kaddr: .long _C_LABEL(__sh_mmu_pt_kaddr)
#elif defined(SH3)
_L.mmu_pt_kaddr: .long _C_LABEL(sh3_mmu_pt_p1addr)
#elif defined(SH4)
_L.mmu_pt_kaddr: .long _C_LABEL(sh4_mmu_pt_p2addr)
#endif
#if defined(LOCKDEBUG)
_L.sched_lock: .long _C_LABEL(sched_lock_idle)
_L.sched_unlock: .long _C_LABEL(sched_unlock_idle)
#endif
/*
* switch_exit(struct proc *p);
* Switch to proc0's saved context and deallocate the address space and kernel
* stack for p. Then jump into cpu_switch(), as if we were in proc0 all along.
*/
ENTRY(switch_exit)
mov r4, r8 /* old process */
mov.l _L.proc0, r9
/* In case we fault... */
xor r0, r0
mov.l _L.curproc, r1
mov.l r0, @r1
/* Restore proc0's context. */
__INTR_MASK_r0_r1
mov r9, r0
mov.l _L.P_ADDR, r1
add r1, r0
mov.l @r0, r10
/* Restore stack pointers. */
mov r10, r0
mov #PCB_R15, r1
add r1, r0
mov.l @r0, r15
/* Switch address space. */
mov r10, r0
add #PCB_PAGEDIRREG, r0
mov.l @r0, r2
MOV (TTB, r1)
mov.l r2, @r1
/* flush TLB */
MOV (tlb_invalidate_all, r0)
jsr @r0
nop
/* Record new pcb. */
mov.l _L.curpcb, r0
mov.l r10, @r0
/* Interrupts are okay again. */
__INTR_UNMASK_r0_r1
mov r8, r4
mov.l _L.exit2, r0
jsr @r0 /* exit2(p) */
nop
/* Jump into cpu_switch() with the right state. */
mov r9, r12
xor r0, r0
mov.l _L.curproc, r1
mov.l r0, @r1
bra switch_search
nop
.align 2
_L.P_ADDR: .long P_ADDR
_L.exit2: .long _C_LABEL(exit2)
_L.curpcb: .long _C_LABEL(curpcb)
_L.curproc: .long _C_LABEL(curproc)
_L.cpl: .long _C_LABEL(cpl)
_L.proc0: .long _C_LABEL(proc0)
REG_SYMBOL(TTB)
FUNC_SYMBOL(tlb_invalidate_all)
/*
* void savectx(struct pcb *pcb);
* Update pcb, saving current processor state.
*/
ENTRY(savectx)
mov.l r14, @-r15
sts.l pr, @-r15
mov r15, r14
add #PCB_R15, r4
mov.l r15, @r4
mov r14, r15
lds.l @r15+, pr
rts
mov.l @r15+, r14
/*
* void ast(struct trapframe *frame):
* Check AST on exit from kernel to user mode.
*/
NENTRY(ast)
mov.l r8, @-r15
sts.l pr, @-r15
mov r4, r8
1:
__INTR_MASK_r0_r1
mov.l _L.astpending, r0
mov.l @r0, r0
tst r0, r0
bt 2f
/* If trap occurred in kernel , skip AST proc */
mov.l @(TF_SSR, r8), r1
mov #0x40, r0
swap.b r0, r0
swap.w r0, r0 /* r0 = 0x40000000 */
and r1, r0
tst r0, r0 /* if (SSR.MD == 0) T = 1 */
bf/s 2f
xor r0, r0
mov.l _L.astpending, r1
mov.l r0, @r1 /* clear astpending */
__INTR_UNMASK_r0_r1
mov.l _L.T_ASTFLT, r1
mov.l r1, @(TF_TRAPNO, r8) /* trapframe->tf_trapno = T_ASTFLT */
mov.l _L.trap, r0
jsr @r0
mov r8, r4
bra 1b
nop
2:
lds.l @r15+, pr
rts
mov.l @r15+, r8
.align 2
_L.trap: .long _C_LABEL(trap)
_L.astpending: .long _C_LABEL(astpending)
_L.T_ASTFLT: .long T_ASTFLT

32
sys/arch/sh3/sh3/sh3_machdep.c
View File

@ -1,4 +1,4 @@
/* $NetBSD: sh3_machdep.c,v 1.25 2002/02/22 19:44:05 uch Exp $ */
/* $NetBSD: sh3_machdep.c,v 1.26 2002/02/24 18:19:43 uch Exp $ */
/*-
* Copyright (c) 1996, 1997, 1998 The NetBSD Foundation, Inc.
@ -76,6 +76,7 @@
*/
#include "opt_kgdb.h"
#include "opt_memsize.h"
#include "opt_compat_netbsd.h"
#include <sys/param.h>
@ -118,10 +119,21 @@ struct vm_map *phys_map = NULL;
extern int physmem;
#ifndef IOM_RAM_BEGIN
#error "define IOM_RAM_BEGIN"
#endif
#define VBR (u_int8_t *)IOM_RAM_BEGIN
vaddr_t ram_start = IOM_RAM_BEGIN;
/* exception handler holder (sh3/sh3/exception_vector.S) */
extern char sh_vector_generic[], sh_vector_generic_end[];
extern char sh_vector_interrupt[], sh_vector_interrupt_end[];
extern char sh_vector_tlbmiss[], sh_vector_tlbmiss_end[];
u_int32_t __sh_BBRA; //XXX
void
sh_cpu_init(int arch, int product)
{
/* CPU type */
cpu_arch = arch;
cpu_product = product;
@ -134,6 +146,18 @@ sh_cpu_init(int arch, int product)
/* Hardclock, RTC initialize. */
machine_clock_init();
/* Exception vector. */
memcpy(VBR + 0x100, sh_vector_generic,
sh_vector_generic_end - sh_vector_generic);
memcpy(VBR + 0x400, sh_vector_tlbmiss,
sh_vector_tlbmiss_end - sh_vector_tlbmiss);
memcpy(VBR + 0x600, sh_vector_interrupt,
sh_vector_interrupt_end - sh_vector_interrupt);
__asm__ __volatile__ ("ldc %0, vbr" :: "r"(VBR));
__sh_BBRA = CPU_IS_SH3 ? 0xffffffb8 : 0xff200008; //XXX
}
void
@ -150,6 +174,10 @@ sh3_startup()
printf(version);
/* Check exception vector size here. */
KDASSERT(sh_vector_generic_end - sh_vector_generic < 0x300);
KDASSERT(sh_vector_tlbmiss_end - sh_vector_tlbmiss < 0x200);
#define MHZ(x) ((x) / 1000000), (((x) % 1000000) / 1000)
sprintf(cpu_model, "HITACHI SH%d %d.%02dMHz PCLOCK %d.%02d MHz",
CPU_IS_SH3 ? 3 : 4, MHZ(sh_clock_get_cpuclock()),

138
sys/arch/sh3/sh3/trap.c
View File

@ -1,4 +1,4 @@
/* $NetBSD: trap.c,v 1.33 2002/02/19 17:21:18 uch Exp $ */
/* $NetBSD: trap.c,v 1.34 2002/02/24 18:19:43 uch Exp $ */
/*-
* Copyright (c) 1995 Charles M. Hannum. All rights reserved.
@ -106,7 +106,7 @@ extern int cpu_debug_mode;
int trapdebug = 1;
static __inline void userret(struct proc *, int, u_quad_t);
void trap(int, int, int, int /* dummy 4 param*/, struct trapframe);
void trap(struct trapframe *);
int trapwrite(unsigned);
void syscall(struct trapframe *);
void tlb_handler(int, int, int, int /* dummy 4 param */, struct trapframe);
@ -155,10 +155,10 @@ userret(struct proc *p, int pc, u_quad_t oticks)
*/
/*ARGSUSED*/
void
trap(int p1, int p2, int p3, int p4,/* dummy param */ struct trapframe frame)
trap(struct trapframe *tf)
{
register struct proc *p = curproc;
int type = frame.tf_trapno;
int type = tf->tf_trapno;
u_quad_t sticks;
struct pcb *pcb = NULL;
int resume;
@ -171,15 +171,15 @@ trap(int p1, int p2, int p3, int p4,/* dummy param */ struct trapframe frame)
#ifdef TRAPDEBUG
if (trapdebug) {
printf("trap %x spc %x ssr %x \n",
frame.tf_trapno, frame.tf_spc, frame.tf_ssr);
tf->tf_trapno, tf->tf_spc, tf->tf_ssr);
printf("curproc %p\n", curproc);
}
#endif
if (!KERNELMODE(frame.tf_r15, frame.tf_ssr)) {
if (!KERNELMODE(tf->tf_r15, tf->tf_ssr)) {
type |= T_USER;
sticks = p->p_sticks;
p->p_md.md_regs = &frame;
p->p_md.md_regs = tf;
}
else
sticks = 0;
@ -189,16 +189,16 @@ trap(int p1, int p2, int p3, int p4,/* dummy param */ struct trapframe frame)
default:
we_re_toast:
#ifdef DDB
if (kdb_trap(type, 0, &frame))
if (kdb_trap(type, 0, tf))
return;
#endif
if (frame.tf_trapno >> 5 < trap_types)
printf("fatal %s", trap_type[frame.tf_trapno >> 5]);
if (tf->tf_trapno >> 5 < trap_types)
printf("fatal %s", trap_type[tf->tf_trapno >> 5]);
else
printf("unknown trap %x", frame.tf_trapno);
printf("unknown trap %x", tf->tf_trapno);
printf(" in %s mode\n", (type & T_USER) ? "user" : "supervisor");
printf("trap type %x spc %x ssr %x \n",
type, frame.tf_spc, frame.tf_ssr);
type, tf->tf_spc, tf->tf_ssr);
panic("trap");
/*NOTREACHED*/
@ -208,7 +208,7 @@ trap(int p1, int p2, int p3, int p4,/* dummy param */ struct trapframe frame)
trapsignal(p, SIGTRAP, type &~ T_USER);
break;
} else {
syscall(&frame);
syscall(tf);
return;
}
@ -227,11 +227,8 @@ trap(int p1, int p2, int p3, int p4,/* dummy param */ struct trapframe frame)
/* Check for copyin/copyout fault. */
pcb = &p->p_addr->u_pcb;
if (pcb->pcb_onfault != 0) {
#ifdef TODO
copyfault:
#endif
printf("copyin/copyout fault\n");
frame.tf_spc = (int)pcb->pcb_onfault;
tf->tf_spc = (int)pcb->pcb_onfault;
return;
}
@ -250,24 +247,18 @@ trap(int p1, int p2, int p3, int p4,/* dummy param */ struct trapframe frame)
* at this point is the same as on exit from a `slow'
* interrupt.
*/
switch (*(u_char *)frame.tf_spc) {
#ifdef TODO
case 0xcf: /* iret */
vframe = (void *)((int)&frame.tf_esp - 44);
resume = (int)resume_iret;
break;
#endif
switch (*(u_char *)tf->tf_spc) {
default:
goto we_re_toast;
}
frame.tf_spc = resume;
tf->tf_spc = resume;
return;
case T_ADDRESSERRR|T_USER: /* protection fault */
case T_ADDRESSERRW|T_USER:
case T_INVALIDSLOT|T_USER:
printf("trap type %x spc %x ssr %x (%s)\n",
type, frame.tf_spc, frame.tf_ssr, p->p_comm);
type, tf->tf_spc, tf->tf_ssr, p->p_comm);
trapsignal(p, SIGBUS, type &~ T_USER);
goto out;
@ -287,99 +278,6 @@ trap(int p1, int p2, int p3, int p4,/* dummy param */ struct trapframe frame)
ADDUPROF(p);
}
goto out;
#ifdef TODO
case T_PAGEFLT: /* allow page faults in kernel mode */
if (p == 0)
goto we_re_toast;
pcb = &p->p_addr->u_pcb;
/*
* fusubail is used by [fs]uswintr() to prevent page faulting
* from inside the profiling interrupt.
*/
if (pcb->pcb_onfault == fusubail)
goto copyfault;
#if 0
/* XXX - check only applies to 386's and 486's with WP off */
if (frame.tf_err & PGEX_P)
goto we_re_toast;
#endif
/* FALLTHROUGH */
case T_PAGEFLT|T_USER: { /* page fault */
register vaddrt_t va;
register struct vmspace *vm = p->p_vmspace;
register struct vm_map *map;
int rv;
vm_prot_t ftype;
extern struct vm_map *kernel_map;
unsigned nss, v;
va = trunc_page((vaddr_t)rcr2());
/*
* It is only a kernel address space fault iff:
* 1. (type & T_USER) == 0 and
* 2. pcb_onfault not set or
* 3. pcb_onfault set but supervisor space fault
* The last can occur during an exec() copyin where the
* argument space is lazy-allocated.
*/
if (type == T_PAGEFLT && va >= KERNBASE)
map = kernel_map;
else
map = &vm->vm_map;
if (frame.tf_err & PGEX_W)
ftype = VM_PROT_WRITE;
else
ftype = VM_PROT_READ;
#ifdef DIAGNOSTIC
if (map == kernel_map && va == 0) {
printf("trap: bad kernel access at %lx\n", va);
goto we_re_toast;
}
#endif
nss = 0;
if ((caddr_t)va >= vm->vm_maxsaddr
&& (caddr_t)va < (caddr_t)VM_MAXUSER_ADDRESS
&& map != kernel_map) {
nss = btoc(USRSTACK-(unsigned)va);
if (nss > btoc(p->p_rlimit[RLIMIT_STACK].rlim_cur)) {
nss = 0;
}
}
/* Fault the original page in. */
rv = uvm_fault(map, va, 0, ftype);
if (rv == 0) {
if (nss > vm->vm_ssize)
vm->vm_ssize = nss;
if (type == T_PAGEFLT)
return;
goto out;
}
nogo:
if (type == T_PAGEFLT) {
if (pcb->pcb_onfault != 0)
goto copyfault;
printf("uvm_fault(%p, 0x%lx, 0, %d) -> %x\n",
map, va, ftype, rv);
goto we_re_toast;
}
if (rv == ENOMEM) {
printf("UVM: pid %d (%s), uid %d killed: out of swap\n",
p->p_pid, p->p_comm,
p->p_cred && p->p_ucred ?
p->p_ucred->cr_uid : -1);
trapsignal(p, SIGKILL, T_PAGEFLT);
} else
trapsignal(p, SIGSEGV, T_PAGEFLT);
break;
}
#endif /* TODO */
case T_USERBREAK|T_USER: /* bpt instruction fault */
trapsignal(p, SIGTRAP, type &~ T_USER);
@ -389,7 +287,7 @@ trap(int p1, int p2, int p3, int p4,/* dummy param */ struct trapframe frame)
if ((type & T_USER) == 0)
return;
out:
userret(p, frame.tf_spc, sticks);
userret(p, tf->tf_spc, sticks);
}
/*