Drop support for 586 PMCs; the detection is broken, and I'm not sure the
code even works. No one has ever cared about this anyway, and we won't maintain it. While here, fix the mask on the counter - K7 and F10H have 48bit counters.
This commit is contained in:
maxv
parent
de23205eb7
commit
68bac86bd0
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@ -1,4 +1,4 @@
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/* $NetBSD: pmc.c,v 1.3 2017/03/11 14:13:39 maxv Exp $ */
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/* $NetBSD: pmc.c,v 1.4 2017/03/24 18:30:44 maxv Exp $ */
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/*
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* Copyright (c) 2017 The NetBSD Foundation, Inc.
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@ -67,7 +67,7 @@
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*/
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#include <sys/cdefs.h>
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__KERNEL_RCSID(0, "$NetBSD: pmc.c,v 1.3 2017/03/11 14:13:39 maxv Exp $");
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__KERNEL_RCSID(0, "$NetBSD: pmc.c,v 1.4 2017/03/24 18:30:44 maxv Exp $");
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#include <sys/param.h>
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#include <sys/systm.h>
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@ -89,6 +89,8 @@ typedef struct {
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uint64_t evtval; /* event selector value */
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uint32_t ctrmsr; /* counter MSR */
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uint64_t ctrval; /* initial counter value */
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uint64_t ctrmaxval; /* maximal counter value */
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uint64_t ctrmask;
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} pmc_state_t;
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static x86_pmc_cpuval_t pmc_val_cpus[MAXCPUS] __aligned(CACHE_LINE_SIZE);
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@ -104,9 +106,7 @@ pmc_read_cpu(void *arg1, void *arg2)
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pmc_state_t *pmc = (pmc_state_t *)arg1;
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struct cpu_info *ci = curcpu();
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pmc_val_cpus[cpu_index(ci)].ctrval =
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rdmsr(pmc->ctrmsr) & 0xffffffffffULL;
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pmc_val_cpus[cpu_index(ci)].overfl = 0;
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pmc_val_cpus[cpu_index(ci)].ctrval = rdmsr(pmc->ctrmsr) & pmc->ctrmask;
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}
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static void
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@ -126,11 +126,6 @@ pmc_apply_cpu(void *arg1, void *arg2)
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wrmsr(pmc->ctrmsr, pmc->ctrval);
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switch (pmc_type) {
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case PMC_TYPE_I586:
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wrmsr(MSR_CESR, pmc_state[0].evtval |
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(pmc_state[1].evtval << 16));
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break;
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case PMC_TYPE_I686:
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case PMC_TYPE_K7:
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case PMC_TYPE_F10H:
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@ -167,13 +162,6 @@ pmc_start(pmc_state_t *pmc, struct x86_pmc_startstop_args *args)
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* Initialize the event MSR.
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*/
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switch (pmc_type) {
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case PMC_TYPE_I586:
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pmc->evtval = args->event |
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((args->flags & PMC_SETUP_KERNEL) ? PMC5_CESR_OS : 0) |
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((args->flags & PMC_SETUP_USER) ? PMC5_CESR_USR : 0) |
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((args->flags & PMC_SETUP_EDGE) ? PMC5_CESR_E : 0);
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break;
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case PMC_TYPE_I686:
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pmc->evtval = args->event | PMC6_EVTSEL_EN |
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(args->unit << PMC6_EVTSEL_UNIT_SHIFT) |
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@ -233,61 +221,52 @@ pmc_init(void)
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{
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const char *cpu_vendorstr;
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struct cpu_info *ci;
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size_t i;
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pmc_type = PMC_TYPE_NONE;
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if (cpu_class != CPUCLASS_686)
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return;
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ci = curcpu();
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cpu_vendorstr = (char *)ci->ci_vendor;
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switch (cpu_class) {
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case CPUCLASS_586:
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if (strncmp(cpu_vendorstr, "GenuineIntel", 12) == 0) {
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pmc_type = PMC_TYPE_I586;
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pmc_ncounters = 2;
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pmc_state[0].ctrmsr = MSR_CTR0;
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pmc_state[1].ctrmsr = MSR_CTR1;
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break;
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if (strncmp(cpu_vendorstr, "GenuineIntel", 12) == 0) {
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/* Right now we're missing Pentium 4 support. */
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if (cpuid_level == -1 ||
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CPUID_TO_FAMILY(ci->ci_signature) == CPU_FAMILY_P4)
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return;
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pmc_type = PMC_TYPE_I686;
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pmc_ncounters = 2;
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for (i = 0; i < pmc_ncounters; i++) {
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pmc_state[i].evtmsr = MSR_EVNTSEL0 + i;
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pmc_state[i].ctrmsr = MSR_PERFCTR0 + i;
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pmc_state[i].ctrmaxval = (UINT64_C(1) << 40) - 1;
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pmc_state[i].ctrmask = 0xFFFFFFFFFFULL;
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}
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case CPUCLASS_686:
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if (strncmp(cpu_vendorstr, "GenuineIntel", 12) == 0) {
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/* Right now we're missing Pentium 4 support. */
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if (cpuid_level == -1 ||
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CPUID_TO_FAMILY(ci->ci_signature) == CPU_FAMILY_P4)
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break;
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pmc_type = PMC_TYPE_I686;
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pmc_ncounters = 2;
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pmc_state[0].evtmsr = MSR_EVNTSEL0;
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pmc_state[0].ctrmsr = MSR_PERFCTR0;
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pmc_state[1].evtmsr = MSR_EVNTSEL1;
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pmc_state[1].ctrmsr = MSR_PERFCTR1;
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} else if (strncmp(cpu_vendorstr, "AuthenticAMD", 12) == 0) {
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if (CPUID_TO_FAMILY(ci->ci_signature) == 0x10) {
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pmc_type = PMC_TYPE_F10H;
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pmc_ncounters = 4;
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pmc_state[0].evtmsr = MSR_F10H_EVNTSEL0;
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pmc_state[0].ctrmsr = MSR_F10H_PERFCTR0;
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pmc_state[1].evtmsr = MSR_F10H_EVNTSEL1;
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pmc_state[1].ctrmsr = MSR_F10H_PERFCTR1;
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pmc_state[2].evtmsr = MSR_F10H_EVNTSEL2;
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pmc_state[2].ctrmsr = MSR_F10H_PERFCTR2;
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pmc_state[3].evtmsr = MSR_F10H_EVNTSEL3;
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pmc_state[3].ctrmsr = MSR_F10H_PERFCTR3;
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} else {
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/* XXX: make sure it is at least K7 */
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pmc_type = PMC_TYPE_K7;
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pmc_ncounters = 4;
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pmc_state[0].evtmsr = MSR_K7_EVNTSEL0;
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pmc_state[0].ctrmsr = MSR_K7_PERFCTR0;
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pmc_state[1].evtmsr = MSR_K7_EVNTSEL1;
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pmc_state[1].ctrmsr = MSR_K7_PERFCTR1;
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pmc_state[2].evtmsr = MSR_K7_EVNTSEL2;
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pmc_state[2].ctrmsr = MSR_K7_PERFCTR2;
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pmc_state[3].evtmsr = MSR_K7_EVNTSEL3;
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pmc_state[3].ctrmsr = MSR_K7_PERFCTR3;
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} else if (strncmp(cpu_vendorstr, "AuthenticAMD", 12) == 0) {
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if (CPUID_TO_FAMILY(ci->ci_signature) == 0x10) {
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pmc_type = PMC_TYPE_F10H;
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pmc_ncounters = 4;
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for (i = 0; i < pmc_ncounters; i++) {
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pmc_state[i].evtmsr = MSR_F10H_EVNTSEL0 + i;
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pmc_state[i].ctrmsr = MSR_F10H_PERFCTR0 + i;
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pmc_state[i].ctrmaxval =
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(UINT64_C(1) << 48) - 1;
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pmc_state[i].ctrmask = 0xFFFFFFFFFFFFULL;
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}
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} else {
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/* XXX: make sure it is at least K7 */
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pmc_type = PMC_TYPE_K7;
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pmc_ncounters = 4;
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for (i = 0; i < pmc_ncounters; i++) {
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pmc_state[i].evtmsr = MSR_K7_EVNTSEL0 + i;
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pmc_state[i].ctrmsr = MSR_K7_PERFCTR0 + i;
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pmc_state[i].ctrmaxval =
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(UINT64_C(1) << 48) - 1;
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pmc_state[i].ctrmask = 0xFFFFFFFFFFFFULL;
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}
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}
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break;
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}
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mutex_init(&pmc_lock, MUTEX_DEFAULT, IPL_NONE);
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@ -1,4 +1,4 @@
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/* $NetBSD: pmc.c,v 1.22 2017/03/11 10:33:46 maxv Exp $ */
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/* $NetBSD: pmc.c,v 1.23 2017/03/24 18:30:44 maxv Exp $ */
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/*
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* Copyright (c) 2017 The NetBSD Foundation, Inc.
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@ -66,7 +66,7 @@
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#include <sys/cdefs.h>
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#ifndef lint
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__RCSID("$NetBSD: pmc.c,v 1.22 2017/03/11 10:33:46 maxv Exp $");
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__RCSID("$NetBSD: pmc.c,v 1.23 2017/03/24 18:30:44 maxv Exp $");
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#endif
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#include <inttypes.h>
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@ -106,47 +106,6 @@ typedef struct {
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size_t size;
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} pmc_name2val_cpu_t;
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static const pmc_name2val_t i586_names[] = {
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{ "tlb-data-miss", PMC5_DATA_TLB_MISS, 0 },
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{ "tlb-ins-miss", PMC5_INST_TLB_MISS, 0 },
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{ "l1cache-ins-miss", PMC5_INST_CACHE_MISS, 0 },
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{ "l1cache-data-miss", PMC5_DATA_RW_MISS, 0 },
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{ "l1cache-data-miss-read", PMC5_DATA_READ_MISS, 0 },
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{ "l1cache-data-miss-write", PMC5_DATA_WRITE_MISS, 0 },
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{ "l1cache-writeback", PMC5_DATA_LINES_WBACK, 0 },
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{ "l1cache-writeback-hit", PMC5_WRITE_M_E, 0 },
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{ "l2cache-data-snoop", PMC5_DATA_CACHE_SNOOP, 0 },
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{ "l2cache-data-snoop-hit", PMC5_DATA_CACHE_SNOOP_HIT, 0 },
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{ "mem-read", PMC5_DATA_READ, 0 },
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{ "mem-write", PMC5_DATA_WRITE, 0 },
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{ "mem-access", PMC5_DATA_RW, 0 },
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{ "mem-access-both-pipes", PMC5_MEM_ACCESS_BOTH_PIPES, 0 },
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{ "mem-bank-conflicts", PMC5_BANK_CONFLICTS, 0 },
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{ "mem-misalign-ref", PMC5_MISALIGNED_DATA, 0 },
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{ "mem-uncached-read", PMC5_NONCACHE_MEM_READ, 0 },
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{ "seg-load-any", PMC5_SEGMENT_REG_LOAD, 0 },
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{ "branch", PMC5_BRANCHES, 0 },
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{ "branch-btb-hit", PMC5_BTB_HITS, 0 },
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{ "branch-taken", PMC5_BRANCH_TAKEN, 0 },
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{ "ins-read", PMC5_INST_READ, 0 },
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{ "ins-pipeline-flush", PMC5_PIPELINE_FLUSH, 0 },
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{ "ins-executed", PMC5_INST_EXECUTED, 0 },
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{ "ins-executed-vpipe", PMC5_INST_EXECUTED_V_PIPE, 0 },
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{ "ins-stall-agi", PMC5_AGI_STALL, 0 },
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{ "ins-stall-write", PMC5_WRITE_BACKUP_STALL, 0 },
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{ "ins-stall-data", PMC5_DATA_READ_STALL, 0 },
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{ "ins-stall-writeline", PMC5_WRITE_E_M_STALL, 0 },
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{ "bus-utilization", PMC5_BUS_UTILIZATION, 0 },
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{ "bus-locked", PMC5_LOCKED_BUS, 0 },
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{ "bus-io-cycle", PMC5_IO_CYCLE, 0 },
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{ "fpu-flops", PMC5_FLOPS, 0 },
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{ "int-hw", PMC5_HARDWARE_INTR, 0 },
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{ "break-match0", PMC5_BP0_MATCH, 0 },
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{ "break-match1", PMC5_BP1_MATCH, 0 },
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{ "break-match2", PMC5_BP2_MATCH, 0 },
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{ "break-match3", PMC5_BP3_MATCH, 0 },
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};
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static const pmc_name2val_t i686_names[] = {
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{ "mem-refs", PMC6_DATA_MEM_REFS, 0 },
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{ "l1cache-lines", PMC6_DCU_LINES_IN, 0 },
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@ -395,8 +354,6 @@ static const pmc_name2val_t f10h_names[] = {
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};
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static const pmc_name2val_cpu_t pmc_cpus[] = {
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{ PMC_TYPE_I586, i586_names,
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sizeof(i586_names) / sizeof(pmc_name2val_t) },
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{ PMC_TYPE_I686, i686_names,
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sizeof(i686_names) / sizeof(pmc_name2val_t) },
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{ PMC_TYPE_K7, k7_names,
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