More PG_TYPE checks/optimizations suggested by Theo.
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6d511104e2
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@ -1,4 +1,4 @@
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/* $NetBSD: pmap.c,v 1.34 1995/02/10 20:40:47 pk Exp $ */
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/* $NetBSD: pmap.c,v 1.35 1995/02/17 20:33:15 pk Exp $ */
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/*
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* Copyright (c) 1992, 1993
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@ -601,16 +601,6 @@ pmap_page_index(pa)
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}
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#endif /* MACHINE_NONCONTIG */
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#if 0
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/*
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* Pages are physically contiguous, and hardware PFN == software PFN.
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*
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* XXX assumes PAGE_SIZE == NBPG (???)
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*/
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#define HWTOSW(pg) (pg)
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#define SWTOHW(pg) (pg)
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#endif
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/* update pv_flags given a valid pte */
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#define MR(pte) (((pte) >> PG_M_SHIFT) & (PV_MOD | PV_REF))
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@ -1791,8 +1781,10 @@ pmap_reference(pm)
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}
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}
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static int pmap_rmk(struct pmap *, vm_offset_t, vm_offset_t, int, int, int);
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static int pmap_rmu(struct pmap *, vm_offset_t, vm_offset_t, int, int, int);
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static int pmap_rmk __P((struct pmap *, vm_offset_t, vm_offset_t,
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int, int, int));
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static int pmap_rmu __P((struct pmap *, vm_offset_t, vm_offset_t,
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int, int, int));
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/*
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* Remove the given range of mapping entries.
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@ -1905,13 +1897,10 @@ pmap_rmk(pm, va, endva, vseg, nleft, pmeg)
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va += PAGE_SIZE;
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continue;
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}
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pv = NULL;
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/* if cacheable, flush page as needed */
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if ((tpte & PG_NC) == 0) {
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if (perpage)
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cache_flush_page(va);
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}
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if ((tpte & PG_TYPE) == PG_OBMEM) {
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/* if cacheable, flush page as needed */
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if (perpage && (tpte & PG_NC) == 0)
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cache_flush_page(va);
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i = ptoa(HWTOSW(tpte & PG_PFNUM));
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if (managed(i)) {
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pv = pvhead(i);
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@ -2015,13 +2004,10 @@ pmap_rmu(pm, va, endva, vseg, nleft, pmeg)
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tpte = getpte(pteva);
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if ((tpte & PG_V) == 0)
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continue;
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pv = NULL;
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/* if cacheable, flush page as needed */
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if ((tpte & PG_NC) == 0) {
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if (perpage)
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cache_flush_page(va);
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}
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if ((tpte & PG_TYPE) == PG_OBMEM) {
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/* if cacheable, flush page as needed */
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if (perpage && (tpte & PG_NC) == 0)
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cache_flush_page(va);
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i = ptoa(HWTOSW(tpte & PG_PFNUM));
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if (managed(i)) {
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pv = pvhead(i);
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@ -2240,7 +2226,8 @@ if (nva == 0) panic("pmap_protect: last segment"); /* cannot happen */
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for (; va < nva; va += NBPG) {
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tpte = getpte(va);
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pmap_stats.ps_npg_prot_all++;
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if (tpte & PG_W) {
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if ((tpte & (PG_W|PG_TYPE)) ==
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(PG_W|PG_OBMEM)) {
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pmap_stats.ps_npg_prot_actual++;
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if (vactype != VAC_NONE)
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cache_flush_page(va);
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@ -2318,7 +2305,7 @@ pmap_changeprot(pm, va, prot, wired)
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goto useless;
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}
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if (vactype == VAC_WRITEBACK &&
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(tpte & (PG_U | PG_NC)) == PG_U)
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(tpte & (PG_U|PG_NC|PG_TYPE)) == (PG_U|PG_OBMEM))
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cache_flush_page((int)va);
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} else {
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setcontext(0);
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@ -2431,8 +2418,6 @@ pmap_enk(pm, va, prot, wired, pv, pteproto)
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* Switcheroo: changing pa for this va.
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* If old pa was managed, remove from pvlist.
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* If old page was cached, flush cache.
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* We are assuming that non-OBMEM addresses are
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* not cached.
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*/
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addr = ptoa(HWTOSW(tpte & PG_PFNUM));
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if (managed(addr))
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@ -2590,8 +2575,6 @@ printf("pmap_enter: pte filled during sleep\n"); /* can this happen? */
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* Switcheroo: changing pa for this va.
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* If old pa was managed, remove from pvlist.
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* If old page was cached, flush cache.
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* We are assuming that non-OBMEM addresses are
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* not cached.
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*/
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/*printf("%s[%d]: pmap_enu: changing existing va(%x)=>pa entry\n",
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curproc->p_comm, curproc->p_pid, va);*/
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@ -2943,7 +2926,7 @@ kvm_uncache(va, npages)
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panic("kvm_uncache !pg_v");
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pte |= PG_NC;
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setpte(va, pte);
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if (vactype != VAC_NONE)
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if (vactype != VAC_NONE && (pte & PG_TYPE) == PG_OBMEM)
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cache_flush_page((int)va);
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}
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}
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