Hide the debug output unless either TEGRA_XUSB_DEBUG is defined or
tegra_xusb_debug is set to 1.
This commit is contained in:
jmcneill
parent
383e9d7b62
commit
67b89dbe58
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@ -1,4 +1,4 @@
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# $NetBSD: files.tegra,v 1.33 2017/04/23 12:31:38 jmcneill Exp $
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# $NetBSD: files.tegra,v 1.34 2017/04/28 09:46:49 jmcneill Exp $
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#
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# Configuration info for NVIDIA Tegra ARM Peripherals
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#
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@ -99,6 +99,7 @@ file arch/arm/nvidia/tegra_ehci.c tegra_ehci
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# XUSB (USB 3.0)
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attach xhci at fdt with tegra_xusb
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file arch/arm/nvidia/tegra_xusb.c tegra_xusb
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defflag opt_tegra.h TEGRA_XUSB_DEBUG
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# SDMMC
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attach sdhc at fdt with tegra_sdhc
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@ -1,4 +1,4 @@
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/* $NetBSD: tegra_xusb.c,v 1.5 2017/04/16 12:28:21 jmcneill Exp $ */
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/* $NetBSD: tegra_xusb.c,v 1.6 2017/04/28 09:46:49 jmcneill Exp $ */
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/*
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* Copyright (c) 2016 Jonathan A. Kollasch
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@ -30,7 +30,7 @@
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#include "opt_tegra.h"
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#include <sys/cdefs.h>
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__KERNEL_RCSID(0, "$NetBSD: tegra_xusb.c,v 1.5 2017/04/16 12:28:21 jmcneill Exp $");
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__KERNEL_RCSID(0, "$NetBSD: tegra_xusb.c,v 1.6 2017/04/28 09:46:49 jmcneill Exp $");
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#include <sys/param.h>
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#include <sys/bus.h>
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@ -57,6 +57,14 @@ __KERNEL_RCSID(0, "$NetBSD: tegra_xusb.c,v 1.5 2017/04/16 12:28:21 jmcneill Exp
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#include <dev/usb/xhcireg.h>
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#include <dev/usb/xhcivar.h>
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#ifdef TEGRA_XUSB_DEBUG
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int tegra_xusb_debug = 1;
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#else
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int tegra_xusb_debug = 0;
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#endif
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#define DPRINTF(...) if (tegra_xusb_debug) device_printf(__VA_ARGS__)
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static int tegra_xusb_match(device_t, cfdata_t, void *);
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static void tegra_xusb_attach(device_t, device_t, void *);
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static void tegra_xusb_mountroot(device_t);
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@ -126,10 +134,10 @@ tegra_xusb_attach(device_t parent, device_t self, void *aux)
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char intrstr[128];
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bus_addr_t addr;
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bus_size_t size;
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int error;
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struct fdtbus_reset *rst;
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struct clk *clk;
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uint32_t rate;
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struct fdtbus_reset *rst;
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int error;
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aprint_naive("\n");
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aprint_normal(": XUSB\n");
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@ -149,7 +157,7 @@ tegra_xusb_attach(device_t parent, device_t self, void *aux)
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aprint_error(": couldn't map %#llx: %d", (uint64_t)addr, error);
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return;
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}
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printf("mapped %#llx\n", (uint64_t)addr);
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DPRINTF(sc->sc_dev, "mapped %#llx\n", (uint64_t)addr);
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if (fdtbus_get_reg(faa->faa_phandle, 1, &addr, &size) != 0) {
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aprint_error(": couldn't get registers\n");
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@ -160,7 +168,7 @@ tegra_xusb_attach(device_t parent, device_t self, void *aux)
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aprint_error(": couldn't map %#llx: %d", (uint64_t)addr, error);
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return;
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}
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printf("mapped %#llx\n", (uint64_t)addr);
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DPRINTF(sc->sc_dev, "mapped %#llx\n", (uint64_t)addr);
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if (fdtbus_get_reg(faa->faa_phandle, 2, &addr, &size) != 0) {
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aprint_error(": couldn't get registers\n");
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@ -171,7 +179,7 @@ tegra_xusb_attach(device_t parent, device_t self, void *aux)
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aprint_error(": couldn't map %#llx: %d", (uint64_t)addr, error);
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return;
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}
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printf("mapped %#llx\n", (uint64_t)addr);
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DPRINTF(sc->sc_dev, "mapped %#llx\n", (uint64_t)addr);
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if (!fdtbus_intr_str(faa->faa_phandle, 0, intrstr, sizeof(intrstr))) {
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aprint_error_dev(self, "failed to decode interrupt\n");
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@ -204,40 +212,40 @@ tegra_xusb_attach(device_t parent, device_t self, void *aux)
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clk = fdtbus_clock_get(faa->faa_phandle, "pll_e");
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rate = clk_get_rate(clk);
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error = clk_enable(clk); /* XXX set frequency */
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device_printf(sc->sc_dev, "rate %u error %d\n", rate, error);
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DPRINTF(sc->sc_dev, "rate %u error %d\n", rate, error);
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tegra_xusb_attach_check(sc, error, "failed to enable pll_e clock");
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clk = fdtbus_clock_get(faa->faa_phandle, "xusb_host_src");
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rate = clk_get_rate(clk);
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device_printf(sc->sc_dev, "rate %u error %d\n", rate, error);
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DPRINTF(sc->sc_dev, "rate %u error %d\n", rate, error);
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error = clk_set_rate(clk, 102000000);
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tegra_xusb_attach_check(sc, error, "failed to set xusb_host_src clock rate");
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rate = clk_get_rate(clk);
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error = clk_enable(clk); /* XXX set frequency */
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device_printf(sc->sc_dev, "rate %u error %d\n", rate, error);
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DPRINTF(sc->sc_dev, "rate %u error %d\n", rate, error);
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tegra_xusb_attach_check(sc, error, "failed to enable xusb_host_src clock");
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clk = fdtbus_clock_get(faa->faa_phandle, "xusb_falcon_src");
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rate = clk_get_rate(clk);
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device_printf(sc->sc_dev, "rate %u error %d\n", rate, error);
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DPRINTF(sc->sc_dev, "rate %u error %d\n", rate, error);
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error = clk_set_rate(clk, 204000000);
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tegra_xusb_attach_check(sc, error, "failed to set xusb_falcon_src clock rate");
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rate = clk_get_rate(clk);
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error = clk_enable(clk);
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device_printf(sc->sc_dev, "rate %u error %d\n", rate, error);
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DPRINTF(sc->sc_dev, "rate %u error %d\n", rate, error);
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tegra_xusb_attach_check(sc, error, "failed to enable xusb_falcon_src clock");
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clk = fdtbus_clock_get(faa->faa_phandle, "xusb_host");
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rate = clk_get_rate(clk);
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error = clk_enable(clk); /* XXX set frequency */
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device_printf(sc->sc_dev, "rate %u error %d\n", rate, error);
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DPRINTF(sc->sc_dev, "rate %u error %d\n", rate, error);
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clk = fdtbus_clock_get(faa->faa_phandle, "xusb_ss");
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rate = clk_get_rate(clk);
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error = clk_enable(clk); /* XXX set frequency */
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device_printf(sc->sc_dev, "xusb_ss rate %u error %d\n", rate, error);
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DPRINTF(sc->sc_dev, "xusb_ss rate %u error %d\n", rate, error);
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tegra_xusb_attach_check(sc, error, "failed to enable xusb_ss clock");
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psc->sc_clk_ss_src = fdtbus_clock_get(faa->faa_phandle, "xusb_ss_src");
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"failed to get xusb_ss_src clock");
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rate = clk_get_rate(psc->sc_clk_ss_src);
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device_printf(sc->sc_dev, "xusb_ss_src rate %u\n", rate);
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DPRINTF(sc->sc_dev, "xusb_ss_src rate %u\n", rate);
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error = clk_set_rate(psc->sc_clk_ss_src, 2000000);
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rate = clk_get_rate(psc->sc_clk_ss_src);
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device_printf(sc->sc_dev, "xusb_ss_src rate %u error %d\n", rate,
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error);
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DPRINTF(sc->sc_dev, "xusb_ss_src rate %u error %d\n", rate, error);
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tegra_xusb_attach_check(sc, error, "failed to get xusb_ss_src clock rate");
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rate = clk_get_rate(psc->sc_clk_ss_src);
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device_printf(sc->sc_dev, "ss_src rate %u\n", rate);
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DPRINTF(sc->sc_dev, "ss_src rate %u\n", rate);
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tegra_xusb_attach_check(sc, error, "failed to set xusb_ss_src clock rate");
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error = clk_set_rate(psc->sc_clk_ss_src, 120000000);
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rate = clk_get_rate(psc->sc_clk_ss_src);
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device_printf(sc->sc_dev, "ss_src rate %u error %d\n", rate, error);
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DPRINTF(sc->sc_dev, "ss_src rate %u error %d\n", rate, error);
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tegra_xusb_attach_check(sc, error, "failed to get xusb_ss_src clock rate");
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error = clk_enable(psc->sc_clk_ss_src);
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device_printf(sc->sc_dev, "ss_src rate %u error %d\n", rate, error);
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DPRINTF(sc->sc_dev, "ss_src rate %u error %d\n", rate, error);
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tegra_xusb_attach_check(sc, error, "failed to enable xusb_ss_src clock");
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#if 0
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clk = fdtbus_clock_get(faa->faa_phandle, "xusb_hs_src");
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error = 0;
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rate = clk_get_rate(clk);
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device_printf(sc->sc_dev, "rate %u error %d\n", rate, error);
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DPRINTF(sc->sc_dev, "rate %u error %d\n", rate, error);
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#endif
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clk = fdtbus_clock_get(faa->faa_phandle, "xusb_fs_src");
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rate = clk_get_rate(clk);
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error = clk_enable(clk); /* XXX set frequency */
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device_printf(sc->sc_dev, "rate %u error %d\n", rate, error);
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DPRINTF(sc->sc_dev, "rate %u error %d\n", rate, error);
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tegra_xusb_attach_check(sc, error, "failed to enable xusb_fs_src clock");
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rst = fdtbus_reset_get(faa->faa_phandle, "xusb_host");
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@ -311,29 +318,29 @@ tegra_xusb_mountroot(device_t self)
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uint32_t val;
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int error;
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device_printf(sc->sc_dev, "%s()\n", __func__);
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DPRINTF(sc->sc_dev, "%s()\n", __func__);
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val = bus_space_read_4(bst, ipfsh, 0x0);
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device_printf(sc->sc_dev, "%s ipfs 0x0 = 0x%x\n", __func__, val);
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DPRINTF(sc->sc_dev, "%s ipfs 0x0 = 0x%x\n", __func__, val);
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if (tegra_xusb_load_fw(psc) != 0)
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return;
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device_printf(sc->sc_dev, "post fw\n");
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DPRINTF(sc->sc_dev, "post fw\n");
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tegra_xusbpad_xhci_enable();
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clk = fdtbus_clock_get(psc->sc_phandle, "xusb_falcon_src");
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rate = clk_get_rate(clk);
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error = clk_enable(clk);
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device_printf(sc->sc_dev, "rate %u error %d\n", rate, error);
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DPRINTF(sc->sc_dev, "rate %u error %d\n", rate, error);
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clk = fdtbus_clock_get(psc->sc_phandle, "xusb_host_src");
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rate = clk_get_rate(clk);
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error = clk_enable(clk);
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device_printf(sc->sc_dev, "rate %u error %d\n", rate, error);
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DPRINTF(sc->sc_dev, "rate %u error %d\n", rate, error);
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val = bus_space_read_4(bst, ipfsh, 0x0);
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device_printf(sc->sc_dev, "%s ipfs 0x0 = 0x%x\n", __func__, val);
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DPRINTF(sc->sc_dev, "%s ipfs 0x0 = 0x%x\n", __func__, val);
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rst = fdtbus_reset_get(psc->sc_phandle, "xusb_host");
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fdtbus_reset_deassert(rst);
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@ -345,7 +352,7 @@ tegra_xusb_mountroot(device_t self)
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fdtbus_reset_deassert(rst);
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val = csb_read_4(psc, XUSB_CSB_FALCON_CPUCTL_REG);
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device_printf(sc->sc_dev, "XUSB_FALC_CPUCTL 0x%x\n", val);
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DPRINTF(sc->sc_dev, "XUSB_FALC_CPUCTL 0x%x\n", val);
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error = xhci_init(sc);
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@ -376,20 +383,20 @@ tegra_xusb_intr_mbox(void *v)
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uint32_t msg;
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int error;
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device_printf(sc->sc_dev, "%s()\n", __func__);
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DPRINTF(sc->sc_dev, "%s()\n", __func__);
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irv = bus_space_read_4(bst, fpcih, T_XUSB_CFG_ARU_SMI_INTR_REG);
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device_printf(sc->sc_dev, "XUSB_CFG_ARU_SMI_INTR 0x%x\n", irv);
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DPRINTF(sc->sc_dev, "XUSB_CFG_ARU_SMI_INTR 0x%x\n", irv);
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bus_space_write_4(bst, fpcih, T_XUSB_CFG_ARU_SMI_INTR_REG, irv);
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if (irv & T_XUSB_CFG_ARU_SMI_INTR_FW_HANG)
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device_printf(sc->sc_dev, "firmware hang\n");
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aprint_error_dev(sc->sc_dev, "firmware hang\n");
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msg = bus_space_read_4(bst, fpcih, T_XUSB_CFG_ARU_MAILBOX_DATA_OUT_REG);
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device_printf(sc->sc_dev, "XUSB_CFG_ARU_MBOX_DATA_OUT 0x%x\n", msg);
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DPRINTF(sc->sc_dev, "XUSB_CFG_ARU_MBOX_DATA_OUT 0x%x\n", msg);
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val = bus_space_read_4(bst, fpcih, T_XUSB_CFG_ARU_MAILBOX_CMD_REG);
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device_printf(sc->sc_dev, "XUSB_CFG_ARU_MBOX_CMD 0x%x\n", val);
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DPRINTF(sc->sc_dev, "XUSB_CFG_ARU_MBOX_CMD 0x%x\n", val);
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val &= ~T_XUSB_CFG_ARU_MAILBOX_CMD_DEST_SMI;
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bus_space_write_4(bst, fpcih, T_XUSB_CFG_ARU_MAILBOX_CMD_REG, val);
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@ -402,19 +409,19 @@ tegra_xusb_intr_mbox(void *v)
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switch (type) {
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case 2:
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case 3:
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device_printf(sc->sc_dev, "FALC_CLOCK %u\n", data * 1000);
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DPRINTF(sc->sc_dev, "FALC_CLOCK %u\n", data * 1000);
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break;
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case 4:
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case 5:
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device_printf(sc->sc_dev, "SSPI_CLOCK %u\n", data * 1000);
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DPRINTF(sc->sc_dev, "SSPI_CLOCK %u\n", data * 1000);
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rate = clk_get_rate(psc->sc_clk_ss_src);
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device_printf(sc->sc_dev, "rate of psc->sc_clk_ss_src %u\n",
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DPRINTF(sc->sc_dev, "rate of psc->sc_clk_ss_src %u\n",
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rate);
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error = clk_set_rate(psc->sc_clk_ss_src, data * 1000);
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if (error != 0)
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goto clk_fail;
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rate = clk_get_rate(psc->sc_clk_ss_src);
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device_printf(sc->sc_dev,
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DPRINTF(sc->sc_dev,
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"rate of psc->sc_clk_ss_src %u after\n", rate);
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if (data == (rate / 1000)) {
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msg = __SHIFTIN(128, MAILBOX_DATA_TYPE) |
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@ -455,52 +462,52 @@ tegra_xusb_init(struct tegra_xusb_softc * const psc)
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const bus_space_handle_t ipfsh = psc->sc_bsh_ipfs;
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const bus_space_handle_t fpcih = psc->sc_bsh_fpci;
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device_printf(sc->sc_dev, "%s()\n", __func__);
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DPRINTF(sc->sc_dev, "%s()\n", __func__);
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device_printf(sc->sc_dev, "%s ipfs 0x0 = 0x%x\n", __func__,
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DPRINTF(sc->sc_dev, "%s ipfs 0x0 = 0x%x\n", __func__,
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bus_space_read_4(bst, ipfsh, 0x0));
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device_printf(sc->sc_dev, "%s ipfs 0x40 = 0x%x\n", __func__,
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DPRINTF(sc->sc_dev, "%s ipfs 0x40 = 0x%x\n", __func__,
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bus_space_read_4(bst, ipfsh, 0x40));
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device_printf(sc->sc_dev, "%s ipfs 0x80 = 0x%x\n", __func__,
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DPRINTF(sc->sc_dev, "%s ipfs 0x80 = 0x%x\n", __func__,
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bus_space_read_4(bst, ipfsh, 0x80));
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/* FPCI_BAR0_START and FPCI_BAR0_ACCESS_TYPE */
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bus_space_write_4(bst, ipfsh, 0x80, 0x00100000);
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device_printf(sc->sc_dev, "%s ipfs 0x80 = 0x%x\n", __func__,
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DPRINTF(sc->sc_dev, "%s ipfs 0x80 = 0x%x\n", __func__,
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bus_space_read_4(bst, ipfsh, 0x80));
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device_printf(sc->sc_dev, "%s ipfs 0x180 = 0x%x\n", __func__,
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DPRINTF(sc->sc_dev, "%s ipfs 0x180 = 0x%x\n", __func__,
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bus_space_read_4(bst, ipfsh, 0x180));
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/* EN_FPCI */
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tegra_reg_set_clear(bst, ipfsh, 0x180, 1, 0);
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device_printf(sc->sc_dev, "%s ipfs 0x180 = 0x%x\n", __func__,
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DPRINTF(sc->sc_dev, "%s ipfs 0x180 = 0x%x\n", __func__,
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bus_space_read_4(bst, ipfsh, 0x180));
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device_printf(sc->sc_dev, "%s fpci PCI_COMMAND_STATUS_REG = 0x%x\n",
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DPRINTF(sc->sc_dev, "%s fpci PCI_COMMAND_STATUS_REG = 0x%x\n",
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__func__, bus_space_read_4(bst, fpcih, PCI_COMMAND_STATUS_REG));
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tegra_reg_set_clear(bst, fpcih, PCI_COMMAND_STATUS_REG,
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PCI_COMMAND_MASTER_ENABLE|PCI_COMMAND_MEM_ENABLE, 0x0);
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device_printf(sc->sc_dev, "%s fpci PCI_COMMAND_STATUS_REG = 0x%x\n",
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DPRINTF(sc->sc_dev, "%s fpci PCI_COMMAND_STATUS_REG = 0x%x\n",
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__func__, bus_space_read_4(bst, fpcih, PCI_COMMAND_STATUS_REG));
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device_printf(sc->sc_dev, "%s fpci PCI_BAR0 = 0x%x\n", __func__,
|
||||
DPRINTF(sc->sc_dev, "%s fpci PCI_BAR0 = 0x%x\n", __func__,
|
||||
bus_space_read_4(bst, fpcih, PCI_BAR0));
|
||||
/* match FPCI BAR0 to above */
|
||||
bus_space_write_4(bst, fpcih, PCI_BAR0, 0x10000000);
|
||||
device_printf(sc->sc_dev, "%s fpci PCI_BAR0 = 0x%x\n", __func__,
|
||||
DPRINTF(sc->sc_dev, "%s fpci PCI_BAR0 = 0x%x\n", __func__,
|
||||
bus_space_read_4(bst, fpcih, PCI_BAR0));
|
||||
|
||||
device_printf(sc->sc_dev, "%s ipfs 0x188 = 0x%x\n", __func__,
|
||||
DPRINTF(sc->sc_dev, "%s ipfs 0x188 = 0x%x\n", __func__,
|
||||
bus_space_read_4(bst, ipfsh, 0x188));
|
||||
tegra_reg_set_clear(bst, ipfsh, 0x188, __BIT(16), 0);
|
||||
device_printf(sc->sc_dev, "%s ipfs 0x188 = 0x%x\n", __func__,
|
||||
DPRINTF(sc->sc_dev, "%s ipfs 0x188 = 0x%x\n", __func__,
|
||||
bus_space_read_4(bst, ipfsh, 0x188));
|
||||
|
||||
device_printf(sc->sc_dev, "%s fpci 0x1bc = 0x%x\n", __func__,
|
||||
DPRINTF(sc->sc_dev, "%s fpci 0x1bc = 0x%x\n", __func__,
|
||||
bus_space_read_4(bst, fpcih, 0x1bc));
|
||||
bus_space_write_4(bst, fpcih, 0x1bc, 0x80);
|
||||
device_printf(sc->sc_dev, "%s fpci 0x1bc = 0x%x\n", __func__,
|
||||
DPRINTF(sc->sc_dev, "%s fpci 0x1bc = 0x%x\n", __func__,
|
||||
bus_space_read_4(bst, fpcih, 0x1bc));
|
||||
}
|
||||
|
||||
|
|
@ -593,7 +600,7 @@ tegra_xusb_load_fw(struct tegra_xusb_softc * const psc)
|
|||
}
|
||||
|
||||
firmware_image = psc->sc_fw_dma.addr;
|
||||
device_printf(sc->sc_dev, "blob %p len %zu\n", firmware_image,
|
||||
DPRINTF(sc->sc_dev, "blob %p len %zu\n", firmware_image,
|
||||
firmware_size);
|
||||
|
||||
#if defined(TEGRA124_XUSB_BIN_STATIC)
|
||||
|
|
@ -615,22 +622,22 @@ tegra_xusb_load_fw(struct tegra_xusb_softc * const psc)
|
|||
const uint32_t boot_codesize = le32dec(&header[FWHEADER_BOOT_CODESIZE]);
|
||||
|
||||
if (fwimg_len != firmware_size)
|
||||
device_printf(sc->sc_dev, "fwimg_len mismatch %u != %zu\n",
|
||||
aprint_error_dev(sc->sc_dev, "fwimg_len mismatch %u != %zu\n",
|
||||
fwimg_len, firmware_size);
|
||||
|
||||
bus_dmamap_sync(sc->sc_bus.ub_dmatag, psc->sc_fw_dma.map, 0,
|
||||
firmware_size, BUS_DMASYNC_PREWRITE);
|
||||
|
||||
device_printf(sc->sc_dev, "XUSB_FALC_CPUCTL 0x%x\n",
|
||||
DPRINTF(sc->sc_dev, "XUSB_FALC_CPUCTL 0x%x\n",
|
||||
csb_read_4(psc, XUSB_CSB_FALCON_CPUCTL_REG));
|
||||
device_printf(sc->sc_dev, "XUSB_CSB_MP_ILOAD_BASE_LO 0x%x\n",
|
||||
DPRINTF(sc->sc_dev, "XUSB_CSB_MP_ILOAD_BASE_LO 0x%x\n",
|
||||
csb_read_4(psc, XUSB_CSB_MEMPOOL_ILOAD_BASE_LO_REG));
|
||||
|
||||
device_printf(sc->sc_dev, "XUSB_CSB_MP_ILOAD_ATTR 0x%x\n",
|
||||
DPRINTF(sc->sc_dev, "XUSB_CSB_MP_ILOAD_ATTR 0x%x\n",
|
||||
csb_read_4(psc, XUSB_CSB_MEMPOOL_ILOAD_ATTR_REG));
|
||||
csb_write_4(psc, XUSB_CSB_MEMPOOL_ILOAD_ATTR_REG,
|
||||
fwimg_len);
|
||||
device_printf(sc->sc_dev, "XUSB_CSB_MP_ILOAD_ATTR 0x%x\n",
|
||||
DPRINTF(sc->sc_dev, "XUSB_CSB_MP_ILOAD_ATTR 0x%x\n",
|
||||
csb_read_4(psc, XUSB_CSB_MEMPOOL_ILOAD_ATTR_REG));
|
||||
|
||||
const uint64_t fwbase = psc->sc_fw_dma.map->dm_segs[0].ds_addr +
|
||||
|
|
@ -638,24 +645,24 @@ tegra_xusb_load_fw(struct tegra_xusb_softc * const psc)
|
|||
|
||||
csb_write_4(psc, XUSB_CSB_MEMPOOL_ILOAD_BASE_HI_REG, fwbase >> 32);
|
||||
csb_write_4(psc, XUSB_CSB_MEMPOOL_ILOAD_BASE_LO_REG, fwbase);
|
||||
device_printf(sc->sc_dev, "XUSB_CSB_MP_ILOAD_BASE_LO 0x%x\n",
|
||||
DPRINTF(sc->sc_dev, "XUSB_CSB_MP_ILOAD_BASE_LO 0x%x\n",
|
||||
csb_read_4(psc, XUSB_CSB_MEMPOOL_ILOAD_BASE_LO_REG));
|
||||
device_printf(sc->sc_dev, "XUSB_CSB_MP_ILOAD_BASE_HI 0x%x\n",
|
||||
DPRINTF(sc->sc_dev, "XUSB_CSB_MP_ILOAD_BASE_HI 0x%x\n",
|
||||
csb_read_4(psc, XUSB_CSB_MEMPOOL_ILOAD_BASE_HI_REG));
|
||||
|
||||
device_printf(sc->sc_dev, "XUSB_CSB_MP_APMAP 0x%x\n",
|
||||
DPRINTF(sc->sc_dev, "XUSB_CSB_MP_APMAP 0x%x\n",
|
||||
csb_read_4(psc, XUSB_CSB_MEMPOOL_APMAP_REG));
|
||||
csb_write_4(psc, XUSB_CSB_MEMPOOL_APMAP_REG,
|
||||
XUSB_CSB_MEMPOOL_APMAP_BOOTPATH);
|
||||
device_printf(sc->sc_dev, "XUSB_CSB_MP_APMAP 0x%x\n",
|
||||
DPRINTF(sc->sc_dev, "XUSB_CSB_MP_APMAP 0x%x\n",
|
||||
csb_read_4(psc, XUSB_CSB_MEMPOOL_APMAP_REG));
|
||||
|
||||
device_printf(sc->sc_dev, "XUSB_CSB_MP_L2IMEMOP_TRIG 0x%x\n",
|
||||
DPRINTF(sc->sc_dev, "XUSB_CSB_MP_L2IMEMOP_TRIG 0x%x\n",
|
||||
csb_read_4(psc, XUSB_CSB_MEMPOOL_L2IMEMOP_TRIG_REG));
|
||||
csb_write_4(psc, XUSB_CSB_MEMPOOL_L2IMEMOP_TRIG_REG,
|
||||
__SHIFTIN(ACTION_L2IMEM_INVALIDATE_ALL,
|
||||
XUSB_CSB_MEMPOOL_L2IMEMOP_TRIG_ACTION));
|
||||
device_printf(sc->sc_dev, "XUSB_CSB_MP_L2IMEMOP_TRIG 0x%x\n",
|
||||
DPRINTF(sc->sc_dev, "XUSB_CSB_MP_L2IMEMOP_TRIG 0x%x\n",
|
||||
csb_read_4(psc, XUSB_CSB_MEMPOOL_L2IMEMOP_TRIG_REG));
|
||||
|
||||
const u_int code_tag_blocks =
|
||||
|
|
@ -664,56 +671,56 @@ tegra_xusb_load_fw(struct tegra_xusb_softc * const psc)
|
|||
howmany(boot_codesize, IMEM_BLOCK_SIZE);
|
||||
const u_int code_blocks = code_tag_blocks + code_size_blocks;
|
||||
|
||||
device_printf(sc->sc_dev, "XUSB_CSB_MP_L2IMEMOP_SIZE 0x%x\n",
|
||||
DPRINTF(sc->sc_dev, "XUSB_CSB_MP_L2IMEMOP_SIZE 0x%x\n",
|
||||
csb_read_4(psc, XUSB_CSB_MEMPOOL_L2IMEMOP_SIZE_REG));
|
||||
csb_write_4(psc, XUSB_CSB_MEMPOOL_L2IMEMOP_SIZE_REG,
|
||||
__SHIFTIN(code_tag_blocks,
|
||||
XUSB_CSB_MEMPOOL_L2IMEMOP_SIZE_SRC_OFFSET) |
|
||||
__SHIFTIN(code_size_blocks,
|
||||
XUSB_CSB_MEMPOOL_L2IMEMOP_SIZE_SRC_COUNT));
|
||||
device_printf(sc->sc_dev, "XUSB_CSB_MP_L2IMEMOP_SIZE 0x%x\n",
|
||||
DPRINTF(sc->sc_dev, "XUSB_CSB_MP_L2IMEMOP_SIZE 0x%x\n",
|
||||
csb_read_4(psc, XUSB_CSB_MEMPOOL_L2IMEMOP_SIZE_REG));
|
||||
|
||||
device_printf(sc->sc_dev, "XUSB_CSB_MP_L2IMEMOP_TRIG 0x%x\n",
|
||||
DPRINTF(sc->sc_dev, "XUSB_CSB_MP_L2IMEMOP_TRIG 0x%x\n",
|
||||
csb_read_4(psc, XUSB_CSB_MEMPOOL_L2IMEMOP_TRIG_REG));
|
||||
csb_write_4(psc, XUSB_CSB_MEMPOOL_L2IMEMOP_TRIG_REG,
|
||||
__SHIFTIN(ACTION_L2IMEM_LOAD_LOCKED_RESULT,
|
||||
XUSB_CSB_MEMPOOL_L2IMEMOP_TRIG_ACTION));
|
||||
device_printf(sc->sc_dev, "XUSB_CSB_MP_L2IMEMOP_TRIG 0x%x\n",
|
||||
DPRINTF(sc->sc_dev, "XUSB_CSB_MP_L2IMEMOP_TRIG 0x%x\n",
|
||||
csb_read_4(psc, XUSB_CSB_MEMPOOL_L2IMEMOP_TRIG_REG));
|
||||
|
||||
device_printf(sc->sc_dev, "XUSB_FALC_IMFILLCTL 0x%x\n",
|
||||
DPRINTF(sc->sc_dev, "XUSB_FALC_IMFILLCTL 0x%x\n",
|
||||
csb_read_4(psc, XUSB_CSB_FALCON_IMFILLCTL_REG));
|
||||
csb_write_4(psc, XUSB_CSB_FALCON_IMFILLCTL_REG, code_size_blocks);
|
||||
device_printf(sc->sc_dev, "XUSB_FALC_IMFILLCTL 0x%x\n",
|
||||
DPRINTF(sc->sc_dev, "XUSB_FALC_IMFILLCTL 0x%x\n",
|
||||
csb_read_4(psc, XUSB_CSB_FALCON_IMFILLCTL_REG));
|
||||
|
||||
device_printf(sc->sc_dev, "XUSB_FALC_IMFILLRNG1 0x%x\n",
|
||||
DPRINTF(sc->sc_dev, "XUSB_FALC_IMFILLRNG1 0x%x\n",
|
||||
csb_read_4(psc, XUSB_CSB_FALCON_IMFILLRNG1_REG));
|
||||
csb_write_4(psc, XUSB_CSB_FALCON_IMFILLRNG1_REG,
|
||||
__SHIFTIN(code_tag_blocks, XUSB_CSB_FALCON_IMFILLRNG1_TAG_LO) |
|
||||
__SHIFTIN(code_blocks, XUSB_CSB_FALCON_IMFILLRNG1_TAG_HI));
|
||||
device_printf(sc->sc_dev, "XUSB_FALC_IMFILLRNG1 0x%x\n",
|
||||
DPRINTF(sc->sc_dev, "XUSB_FALC_IMFILLRNG1 0x%x\n",
|
||||
csb_read_4(psc, XUSB_CSB_FALCON_IMFILLRNG1_REG));
|
||||
|
||||
device_printf(sc->sc_dev, "XUSB_FALC_DMACTL 0x%x\n",
|
||||
DPRINTF(sc->sc_dev, "XUSB_FALC_DMACTL 0x%x\n",
|
||||
csb_read_4(psc, XUSB_CSB_FALCON_DMACTL_REG));
|
||||
csb_write_4(psc, XUSB_CSB_FALCON_DMACTL_REG, 0);
|
||||
device_printf(sc->sc_dev, "XUSB_FALC_DMACTL 0x%x\n",
|
||||
DPRINTF(sc->sc_dev, "XUSB_FALC_DMACTL 0x%x\n",
|
||||
csb_read_4(psc, XUSB_CSB_FALCON_DMACTL_REG));
|
||||
|
||||
device_printf(sc->sc_dev, "XUSB_FALC_BOOTVEC 0x%x\n",
|
||||
DPRINTF(sc->sc_dev, "XUSB_FALC_BOOTVEC 0x%x\n",
|
||||
csb_read_4(psc, XUSB_CSB_FALCON_BOOTVEC_REG));
|
||||
csb_write_4(psc, XUSB_CSB_FALCON_BOOTVEC_REG,
|
||||
boot_codetag);
|
||||
device_printf(sc->sc_dev, "XUSB_FALC_BOOTVEC 0x%x\n",
|
||||
DPRINTF(sc->sc_dev, "XUSB_FALC_BOOTVEC 0x%x\n",
|
||||
csb_read_4(psc, XUSB_CSB_FALCON_BOOTVEC_REG));
|
||||
|
||||
device_printf(sc->sc_dev, "XUSB_FALC_CPUCTL 0x%x\n",
|
||||
DPRINTF(sc->sc_dev, "XUSB_FALC_CPUCTL 0x%x\n",
|
||||
csb_read_4(psc, XUSB_CSB_FALCON_CPUCTL_REG));
|
||||
csb_write_4(psc, XUSB_CSB_FALCON_CPUCTL_REG,
|
||||
XUSB_CSB_FALCON_CPUCTL_STARTCPU);
|
||||
device_printf(sc->sc_dev, "XUSB_FALC_CPUCTL 0x%x\n",
|
||||
DPRINTF(sc->sc_dev, "XUSB_FALC_CPUCTL 0x%x\n",
|
||||
csb_read_4(psc, XUSB_CSB_FALCON_CPUCTL_REG));
|
||||
|
||||
return 0;
|
||||
|
|
@ -758,7 +765,7 @@ xusb_mailbox_send(struct tegra_xusb_softc * const psc, uint32_t msg)
|
|||
if (!(type == 128 || type == 129)) {
|
||||
val = bus_space_read_4(bst, fpcih,
|
||||
T_XUSB_CFG_ARU_MAILBOX_OWNER_REG);
|
||||
device_printf(sc->sc_dev, "XUSB_CFG_ARU_MBOX_OWNER 0x%x\n",
|
||||
DPRINTF(sc->sc_dev, "XUSB_CFG_ARU_MBOX_OWNER 0x%x\n",
|
||||
val);
|
||||
if (val != MAILBOX_OWNER_NONE) {
|
||||
return EBUSY;
|
||||
|
|
@ -769,7 +776,7 @@ xusb_mailbox_send(struct tegra_xusb_softc * const psc, uint32_t msg)
|
|||
|
||||
val = bus_space_read_4(bst, fpcih,
|
||||
T_XUSB_CFG_ARU_MAILBOX_OWNER_REG);
|
||||
device_printf(sc->sc_dev, "XUSB_CFG_ARU_MBOX_OWNER 0x%x\n",
|
||||
DPRINTF(sc->sc_dev, "XUSB_CFG_ARU_MBOX_OWNER 0x%x\n",
|
||||
val);
|
||||
if (val != MAILBOX_OWNER_SW) {
|
||||
return EBUSY;
|
||||
|
|
@ -789,7 +796,7 @@ xusb_mailbox_send(struct tegra_xusb_softc * const psc, uint32_t msg)
|
|||
for (u_int i = 0; i < 2500; i++) {
|
||||
val = bus_space_read_4(bst, fpcih,
|
||||
T_XUSB_CFG_ARU_MAILBOX_OWNER_REG);
|
||||
device_printf(sc->sc_dev,
|
||||
DPRINTF(sc->sc_dev,
|
||||
"XUSB_CFG_ARU_MBOX_OWNER 0x%x\n", val);
|
||||
if (val == MAILBOX_OWNER_NONE) {
|
||||
break;
|
||||
|
|
@ -799,10 +806,10 @@ xusb_mailbox_send(struct tegra_xusb_softc * const psc, uint32_t msg)
|
|||
|
||||
val = bus_space_read_4(bst, fpcih,
|
||||
T_XUSB_CFG_ARU_MAILBOX_OWNER_REG);
|
||||
device_printf(sc->sc_dev,
|
||||
DPRINTF(sc->sc_dev,
|
||||
"XUSB_CFG_ARU_MBOX_OWNER 0x%x\n", val);
|
||||
if (val != MAILBOX_OWNER_NONE) {
|
||||
device_printf(sc->sc_dev,
|
||||
aprint_error_dev(sc->sc_dev,
|
||||
"timeout, XUSB_CFG_ARU_MBOX_OWNER 0x%x\n", val);
|
||||
}
|
||||
}
|
||||
|
|
|
|||
Loading…
Reference in New Issue