Memory map and system registers for the Firepower ES, MX, LX, and TX
systems.
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thorpej
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/* $NetBSD: firepowerreg.h,v 1.1 2001/10/24 20:36:44 thorpej Exp $ */
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/*
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* Copyright 2001 Wasabi Systems, Inc.
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* All rights reserved.
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*
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* Written by Jason R. Thorpe for Wasabi Systems, Inc.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* 3. All advertising materials mentioning features or use of this software
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* must display the following acknowledgement:
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* This product includes software developed for the NetBSD Project by
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* Wasabi Systems, Inc.
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* 4. The name of Wasabi Systems, Inc. may not be used to endorse
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* or promote products derived from this software without specific prior
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* written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY WASABI SYSTEMS, INC. ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
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* TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
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* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL WASABI SYSTEMS, INC
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* BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*/
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/*
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* Register definitions and memory map for the Firepower ES, MX, LX, and TX
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* systems.
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*/
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/*****************************************************************************
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* SYSTEM MEMORY MAP
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*****************************************************************************/
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/*
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* Note: This pretty much corresponds to the PReP Contiguous Memory Map.
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*/
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#define FP_MAP_SYSMEM_BASE 0x00000000 /* system memory base */
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#define FP_MAP_SYSMEM_SIZE 0x80000000 /* system memory size */
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#define FP_MAP_ISAIO_BASE 0x80000000 /* ISA I/O base */
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#define FP_MAP_ISAIO_SIZE 0x00010000 /* ISA I/O size */
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#define FP_MAP_PCICFG_BASE 0x80800000 /* PCI config base */
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#define FP_MAP_PCICFG_SIZE 0x00a00000 /* PCI config size */
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#define FP_MAP_PCIIO_BASE 0x81200000 /* PCI I/O base */
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#define FP_MAP_PCIIO_SIZE 0x3e800000 /* PCI I/O size */
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#define FP_MAP_PCIMEM_BASE 0xc0000000 /* PCI memory base */
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#define FP_MAP_PCIMEM_SIZE 0x3f000000 /* PCI memory size */
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/*****************************************************************************
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* SYSTEM REGISTERS
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*****************************************************************************/
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#define FPR_INTR_REQUEST 0xff000000 /* Interrupt Request */
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#define FPR_INTR_REQUEST_SET 0xff000008 /* Interrupt Request Set */
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#define FPR_INTR_MASK0 0xff000100 /* Interrupt Mask0 */
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#define FPR_INTR_MASK1 0xff000108 /* Interrupt Mask1 */
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#define FPR_INTR_MASK2 0xff000110 /* Interrupt Mask2 */
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#define FPR_INTR_MASK3 0xff000118 /* Interrupt Mask3 */
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#define FPR_INTR_PENDING0 0xff000200 /* Interrupt Pending0 */
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#define FPR_INTR_PENDING1 0xff000208 /* Interrupt Pending1 */
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#define FPR_INTR_PENDING2 0xff000210 /* Interrupt Pending2 */
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#define FPR_INTR_PENDING3 0xff000218 /* Interrupt Pending3 */
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#define INTR_ISA_IRQ(x) (1U << (x)) /* ISA IRQs 0-15 */
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#define INTR_SOFT(x) (1U << ((x) + 16))/* 4 software interrupts */
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#define INTR_PCI0 (1U << 22) /* PCI slot 0 */
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#define INTR_PCI1 (1U << 23) /* PCI slot 1 */
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#define INTR_SCSI (1U << 25) /* SCSI */
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#define INTR_ETHERNET (1U << 26) /* Ethernet */
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#define INTR_SIO_NMI (1U << 27) /* SIO NMI */
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#define INTR_CPU_ERR (1U << 28) /* CPU Bus Error */
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#define INTR_PCI_ERR (1U << 29) /* PCI Bus Error */
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#define INTR_MEM_ERR (1U << 30) /* Memory Error/Video Intr */
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#define INTR_CPU_MSG (1U << 31) /* CPU message */
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#define FPR_CPU_MSG_INTR 0xff000300 /* CPU Message Interrupt */
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#define FPR_CPU_MSG_INTR_SET 0xff000308 /* CPU Message Interrupt Set */
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#define CPU_MSG_INTR(x) (1U << (x)) /* interrupt CPU #x */
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#define FPR_PCI_ERR_CAUSE 0xff000400 /* PCI Error Cause */
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#define FPR_PCI_ERR_CAUSE_SET 0xff000408 /* PCI Error Cause Set */
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#define PCI_ERR_CAUSE_ADDRPAR (1U << 0) /* address parity error */
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#define PCI_ERR_CAUSE_DATAPAR (1U << 1) /* data parity error */
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#define PCI_ERR_CAUSE_DEVTOUT (1U << 2) /* device timeout */
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#define PCI_ERR_CAUSE_TABORT (1U << 3) /* target abort */
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#define FPR_PCI_ERR_ADDR 0xff000410 /* PCI Error Address */
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#define FPR_CPU_ERR_CAUSE 0xff000800 /* CPU Error Cause */
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#define FPR_CPU_ERR_CAUSE_SET 0xff000808 /* CPU Error Cause Set */
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#define CPU_ERR_CAUSE_ILLISA (1U << 0) /* illegal ISA access */
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#define CPU_ERR_CAUSE_ADDRPAR (1U << 1) /* address parity error */
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#define CPU_ERR_CAUSE_DISISA (1U << 2) /* discontig ISA error */
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#define FPR_CPU_ERR_ADDR 0xff000810 /* CPU Error Address */
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#define FPR_ERROR_STATUS0 0xff001000 /* errorStatus0 */
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#define FPR_ERROR_STATUS0_SET 0xff001008 /* errorStatus0 Set */
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#define FPR_ERROR_MASK0 0xff001010 /* errorMask0 */
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#define ERROR_STATUS_ECC_CORR (1U << 1) /* ECC error corrected */
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#define ERROR_STATUS_ECC_FAILED (1U << 2) /* ECC error uncorrected */
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#define ERROR_STATUS_DPE (1U << 4) /* data parity error */
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#define ERROR_STATUS_MEMPAR (1U << 5) /* memory parity error */
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#define ERROR_STATUS_INVXACT (1U << 6) /* invalid transaction */
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#define FPR_ERROR_ADDR0 0xff001120 /* errorAddr0 (MSB) */
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#define FPR_ERROR_ADDR1 0xff001128 /* errorAddr1 */
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#define FPR_ERROR_ADDR2 0xff001130 /* errorAddr2 */
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#define FPR_ERROR_ADDR3 0xff001138 /* errorAddr3 (LSB) */
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#define FPR_VID_INT 0xff001140 /* Video Interrupt */
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#define FPR_VID_INT_SET 0xff001148 /* Video Interrupt Set */
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#define FPR_VID_INT_MASK 0xff001150 /* Video Interrupt Mask */
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#define VID_INT_VIDINT (1U << 0) /* frame completed */
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#define VID_INT_VRAM_OFLO (1U << 1) /* frame data overflow */
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#define FPR_TSC_CONTROL 0xff100000 /* tscControl */
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#define TSC_CONTROL_L2_PRESENT (1U << 0) /* L2 cache present */
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#define TSC_CONTROL_MP_CONFIG (1U << 2) /* multiprocessor system */
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#define TSC_CONTROL_ECC_ENABLE (1U << 3) /* ECC enable */
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#define TSC_CONTROL_LITTLE_END (1U << 4) /* system is little-endian */
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#define TSC_CONTROL_BRIDGE_MODE (1U << 5) /* PCI-PCI bridge present */
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#define FPR_FB_CONTROL 0xff100008 /* fbControl */
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#define FPR_ESCC_CONTROL 0xff100010 /* esccControl */
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#define ESCC_CONTROL_L2DIS_L (1U << 0) /* 0 = disable L2 cache opt. */
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#define ESCC_CONTROL_L2MISIN_L (1U << 1) /* 0 = inhibit L2 upd.on miss */
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#define ESCC_CONTROL_MRMPAR_EN (1U << 3) /* memory parity enable */
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#define ESCC_CONTROL_LITTLE_END (1U << 4) /* system is little-endian */
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#define ESCC_CONTROL_LDBADPAR (1U << 5) /* load bad parity */
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#define FPR_ESCC_L2_FLUSH 0xff100018 /* esccL2Flush */
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#define FPR_SCRATCH_PAD0 0xff100020 /* scratchPad0 */
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#define FPR_SCRATCH_PAD1 0xff100028 /* scratchPad1 */
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#define FPR_SCRATCH_PAD2 0xff100030 /* scratchPad2 */
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#define FPR_SCRATCH_PAD3 0xff100038 /* scartchPad3 */
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#define FPR_LOW_POWER_CONTROL 0xff100080 /* lowPowerControl */
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#define LOW_POWER_CONTROL_QACK_L (1U << 0) /* cpuQack_L signal */
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#define LOW_POWER_CONTROL_QREQ_L (1U << 1) /* cpuQreq_L signal */
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#define FPR_ROM_CONTROL 0xff100100 /* romControl */
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#define ROM_CONTROL_CS_L (1U << 0) /* # chip select */
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#define ROM_CONTROL_WE_L (1U << 1) /* # write enable */
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#define ROM_CONTROL_WR_CMPL (1U << 2) /* terminate ROM write cycle */
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#define FPR_TSC_STATUS0 0xff100200 /* tscControl */
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#define TSC_STATUS0_ROMBSY (1U << 0) /* ROM busy */
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#define TSC_STATUS0_WRQFULL (1U << 1) /* write queue full */
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#define TSC_STATUS0_L2QFULL (1U << 2) /* read queue full */
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#define TSC_STATUS0_WRQEMPTY (1U << 3) /* write queue empty */
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#define TSC_STATUS0_L2QEMPTY (1U << 4) /* read queue empty */
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#define TSC_STATUS0_CPU(x) ((x) >> 6) /* which CPU is reading it */
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#define FPR_TSC_REVISION 0xff100300 /* tscRevision */
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#define FPR_MEM_BANK0_CONFIG 0xff100400 /* memBank0Config */
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#define FPR_MEM_BANK1_CONFIG 0xff100408 /* memBank1Config */
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#define FPR_MEM_BANK2_CONFIG 0xff100410 /* memBank2Config */
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#define FPR_MEM_BANK3_CONFIG 0xff100418 /* memBank3Config */
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#define FPR_MEM_BANK4_CONFIG 0xff100420 /* memBank4Config */
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#define FPR_MEM_BANK5_CONFIG 0xff100428 /* memBank5Config */
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#define FPR_MEM_BANK6_CONFIG 0xff100430 /* memBank6Config */
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#define FPR_MEM_BANK7_CONFIG 0xff100438 /* memBank7Config */
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#define FPR_MEM_DRAM_TIMING 0xff100500 /* memDramTiming */
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#define FPR_MEM_VRAM_TIMING 0xff100508 /* memVramTiming */
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#define FPR_MEM_REFRESH 0xff100510 /* memRefresh */
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#define FPR_VID_CONTROL 0xff100518 /* vidControl */
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#define FPR_VID_PIX_LINE_LO 0xff100520 /* vidPixelsPerLineLo */
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#define FPR_VID_PIX_LINE_HI 0xff100528 /* vidPixelsPerLineHi */
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#define FPR_IO_CONTROL 0xff101000 /* ioControl */
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#define IO_CONTROL_LE_ADDR (1U << 0) /* little-endian addresses */
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#define IO_CONTROL_LE_DATA (1U << 1) /* little-endian data */
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#define IO_CONTROL_CONTIG_ISA (1U << 2) /* contig memory map */
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#define IO_CONTROL_EXT_PCI_INTS (1U << 3) /* PCI interrupt grouping */
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#define FPR_PCI_CONFIG_TYPE 0xff101100 /* PCI Config Type */
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#define PCI_CONFIG_TYPE_0 0
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#define PCI_CONFIG_TYPE_1 1
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#define FPR_PIO_PENDING_CNT 0xff101200 /* PIO pending count */
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#define PIO_PENDING_CNT(x) ((x) & 0x7f)
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#define PIO_PENDING_CNT_BRIDGE (1U << 7) /* enable PCI-PCI bridges */
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#define FPR_DMA_PENDING_CNT 0xff101300 /* DMA pending count */
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#define DMA_PENDING_CNT(x) ((x) & 0xff)
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#deifne FPR_PCI_VENDOR_ID 0xff400100 /* PCI vendor ID */
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#define FPR_PCI_DEVICE_ID 0xff400108 /* PCI device ID */
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#define FPR_PCI_COMMAND 0xff400110 /* PCI command */
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#define FPR_PCI_STATUS 0xff400118 /* PCI status */
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#define FPR_PCI_REVISION 0xff400120 /* PCI revision */
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#define FPR_PCI_CLASS 0xff400128 /* PCI class */
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#define FPR_PCI_HEADERTYPE 0xff400140 /* PCI header type */
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