Add microSPARC-IIep support. Move sun4m bootstrap into separate
functions (for normal 4m and for IIep).
This commit is contained in:
uwe
parent
0a2b7fe7d7
commit
6767457cab
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@ -1,4 +1,4 @@
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/* $NetBSD: autoconf.c,v 1.158 2001/12/04 00:05:05 darrenr Exp $ */
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/* $NetBSD: autoconf.c,v 1.159 2001/12/11 04:21:39 uwe Exp $ */
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/*
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* Copyright (c) 1996
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@ -53,6 +53,7 @@
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#include <sys/param.h>
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#include <sys/systm.h>
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#include <sys/endian.h>
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#include <sys/proc.h>
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#include <sys/map.h>
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#include <sys/buf.h>
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@ -90,10 +91,16 @@
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#include <sparc/sparc/cpuvar.h>
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#include <sparc/sparc/timerreg.h>
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#include <dev/pci/pcireg.h>
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#include <dev/pci/pcidevs.h>
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#include <dev/pci/pcivar.h>
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#include <sparc/sparc/msiiepreg.h>
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#ifdef DDB
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#include <machine/db_machdep.h>
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#include <ddb/db_sym.h>
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#include <ddb/db_extern.h>
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#include <ddb/ddbvar.h>
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#endif
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@ -199,6 +206,15 @@ str2hex(str, vp)
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return (str);
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}
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#if defined(SUN4M)
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#if !defined(MSIIEP)
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static void bootstrap4m(void);
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#else
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static void bootstrapIIep(void);
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#endif
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#endif /* SUN4M */
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/*
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* locore.s code calls bootstrap() just before calling main(), after double
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* mapping the kernel to high memory and setting up the trap base register.
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@ -255,89 +271,21 @@ bootstrap()
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}
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#endif
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/*
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* On sun4ms we have to do some nasty stuff here. We need to map
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* in the interrupt registers (since we need to find out where
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* they are from the PROM, since they aren't in a fixed place), and
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* disable all interrupts. We can't do this easily from locore
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* since the PROM is ugly to use from assembly. We also need to map
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* in the counter registers because we can't disable the level 14
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* (statclock) interrupt, so we need a handler early on (ugh).
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*
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* NOTE: We *demand* the psl to stay at splhigh() at least until
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* we get here. The system _cannot_ take interrupts until we map
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* the interrupt registers.
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*/
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#if defined(SUN4M)
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/* First we'll do the interrupt registers */
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/*
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* sun4m bootstrap is complex and is totally different for "normal" 4m
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* and for microSPARC-IIep - so it's split into separate functions.
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*/
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if (CPU_ISSUN4M) {
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int node;
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int nvaddrs, *vaddrs, vstore[10];
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u_int pte;
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int i;
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extern void setpte4m __P((u_int, u_int));
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if ((node = prom_opennode("/obio/interrupt")) == 0 &&
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(node = prom_finddevice("/obio/interrupt")) == 0)
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panic("bootstrap: could not get interrupt "
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"node from prom");
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vaddrs = vstore;
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nvaddrs = sizeof(vstore)/sizeof(vstore[0]);
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if (PROM_getprop(node, "address", sizeof(int),
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&nvaddrs, (void **)&vaddrs) != 0) {
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printf("bootstrap: could not get interrupt properties");
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prom_halt();
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}
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if (nvaddrs < 2 || nvaddrs > 5) {
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printf("bootstrap: cannot handle %d interrupt regs\n",
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nvaddrs);
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prom_halt();
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}
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for (i = 0; i < nvaddrs - 1; i++) {
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pte = getpte4m((u_int)vaddrs[i]);
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if ((pte & SRMMU_TETYPE) != SRMMU_TEPTE) {
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panic("bootstrap: PROM has invalid mapping for "
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"processor interrupt register %d",i);
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prom_halt();
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}
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pte |= PPROT_S;
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/* Duplicate existing mapping */
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setpte4m(PI_INTR_VA + (_MAXNBPG * i), pte);
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}
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cpuinfo.intreg_4m = (struct icr_pi *)(PI_INTR_VA);
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/*
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* That was the processor register...now get system register;
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* it is the last returned by the PROM
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*/
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pte = getpte4m((u_int)vaddrs[i]);
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if ((pte & SRMMU_TETYPE) != SRMMU_TEPTE)
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panic("bootstrap: PROM has invalid mapping for system "
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"interrupt register");
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pte |= PPROT_S;
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setpte4m(SI_INTR_VA, pte);
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/* Now disable interrupts */
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ienab_bis(SINTR_MA);
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/* Send all interrupts to primary processor */
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*((u_int *)ICR_ITR) = 0;
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#ifdef DEBUG
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/* printf("SINTR: mask: 0x%x, pend: 0x%x\n", *(int*)ICR_SI_MASK,
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*(int*)ICR_SI_PEND);
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*/
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#if !defined(MSIIEP)
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bootstrap4m();
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#else
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bootstrapIIep();
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#endif
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}
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#endif /* SUN4M */
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#if defined(SUN4) || defined(SUN4C)
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if (CPU_ISSUN4OR4C) {
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/* Map Interrupt Enable Register */
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pmap_kenter_pa(INTRREG_VA,
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@ -347,8 +295,139 @@ bootstrap()
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/* Disable all interrupts */
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*((unsigned char *)INTRREG_VA) = 0;
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}
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#endif /* SUN4 || SUN4C */
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}
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#if defined(SUN4M) && !defined(MSIIEP)
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/*
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* On sun4ms we have to do some nasty stuff here. We need to map
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* in the interrupt registers (since we need to find out where
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* they are from the PROM, since they aren't in a fixed place), and
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* disable all interrupts. We can't do this easily from locore
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* since the PROM is ugly to use from assembly. We also need to map
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* in the counter registers because we can't disable the level 14
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* (statclock) interrupt, so we need a handler early on (ugh).
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*
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* NOTE: We *demand* the psl to stay at splhigh() at least until
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* we get here. The system _cannot_ take interrupts until we map
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* the interrupt registers.
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*/
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static void
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bootstrap4m()
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{
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int node;
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int nvaddrs, *vaddrs, vstore[10];
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u_int pte;
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int i;
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extern void setpte4m __P((u_int, u_int));
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if ((node = prom_opennode("/obio/interrupt")) == 0
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&& (node = prom_finddevice("/obio/interrupt")) == 0)
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panic("bootstrap: could not get interrupt "
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"node from prom");
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vaddrs = vstore;
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nvaddrs = sizeof(vstore)/sizeof(vstore[0]);
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if (PROM_getprop(node, "address", sizeof(int),
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&nvaddrs, (void **)&vaddrs) != 0) {
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printf("bootstrap: could not get interrupt properties");
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prom_halt();
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}
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if (nvaddrs < 2 || nvaddrs > 5) {
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printf("bootstrap: cannot handle %d interrupt regs\n",
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nvaddrs);
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prom_halt();
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}
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for (i = 0; i < nvaddrs - 1; i++) {
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pte = getpte4m((u_int)vaddrs[i]);
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if ((pte & SRMMU_TETYPE) != SRMMU_TEPTE) {
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panic("bootstrap: PROM has invalid mapping for "
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"processor interrupt register %d",i);
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prom_halt();
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}
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pte |= PPROT_S;
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/* Duplicate existing mapping */
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setpte4m(PI_INTR_VA + (_MAXNBPG * i), pte);
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}
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cpuinfo.intreg_4m = (struct icr_pi *)(PI_INTR_VA);
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/*
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* That was the processor register...now get system register;
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* it is the last returned by the PROM
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*/
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pte = getpte4m((u_int)vaddrs[i]);
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if ((pte & SRMMU_TETYPE) != SRMMU_TEPTE)
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panic("bootstrap: PROM has invalid mapping for system "
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"interrupt register");
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pte |= PPROT_S;
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setpte4m(SI_INTR_VA, pte);
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/* Now disable interrupts */
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ienab_bis(SINTR_MA);
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/* Send all interrupts to primary processor */
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*((u_int *)ICR_ITR) = 0;
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#ifdef DEBUG
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/* printf("SINTR: mask: 0x%x, pend: 0x%x\n", *(int*)ICR_SI_MASK,
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*(int*)ICR_SI_PEND);
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*/
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#endif
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}
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#endif /* SUN4M && !MSIIEP */
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#if defined(SUN4M) && defined(MSIIEP)
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#define msiiep ((volatile struct msiiep_pcic_reg *)MSIIEP_PCIC_VA)
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/*
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* On ms-IIep all the interrupt registers, counters etc
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* are PCIC registers, so we need to map it early.
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*/
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static void
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bootstrapIIep()
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{
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extern struct sparc_bus_space_tag mainbus_space_tag;
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int node;
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bus_space_handle_t bh;
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pcireg_t id;
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if ((node = prom_opennode("/pci")) == 0
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&& (node = prom_finddevice("/pci")) == 0)
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panic("bootstrap: could not get pci "
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"node from prom");
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if (bus_space_map2(&mainbus_space_tag,
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(bus_type_t)0, (bus_addr_t)MSIIEP_PCIC_PA,
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(bus_size_t)sizeof(struct msiiep_pcic_reg),
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BUS_SPACE_MAP_LINEAR,
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MSIIEP_PCIC_VA, &bh) != 0)
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panic("bootstrap: unable to map ms-IIep pcic registers");
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/* verify that it's PCIC (it's still little-endian at this point) */
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id = le32toh(msiiep->pcic_id);
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if (PCI_VENDOR(id) != PCI_VENDOR_SUN
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&& PCI_PRODUCT(id) != PCI_PRODUCT_SUN_MS_IIep)
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panic("bootstrap: PCI id %08x", id);
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/* turn on automagic endian-swapping for PCI accesses */
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msiiep_swap_endian(1);
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/* sanity check (it's big-endian now!) */
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id = msiiep->pcic_id;
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if (PCI_VENDOR(id) != PCI_VENDOR_SUN
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&& PCI_PRODUCT(id) != PCI_PRODUCT_SUN_MS_IIep)
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panic("bootstrap: PCI id %08x (big-endian mode)", id);
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}
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#undef msiiep
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#endif /* SUN4M && MSIIEP */
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/*
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* bootpath_build: build a bootpath. Used when booting a generic
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* kernel to find our root device. Newer proms give us a bootpath,
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@ -424,7 +503,7 @@ bootpath_build()
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++nbootpath;
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bp = &bootpath[2];
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continue;
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} else
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} else
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bp = &bootpath[1];
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}
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#endif /* SUN4M */
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@ -830,9 +909,15 @@ cpu_configure()
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/* Enable device interrupts */
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#if defined(SUN4M)
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#if !defined(MSIIEP)
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if (CPU_ISSUN4M)
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ienab_bic(SINTR_MA);
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#endif
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#else
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if (CPU_ISSUN4M)
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/* nothing for ms-IIep so far */;
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#endif /* MSIIEP */
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#endif /* SUN4M */
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#if defined(SUN4) || defined(SUN4C)
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if (CPU_ISSUN4OR4C)
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ienab_bis(IE_ALLIE);
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@ -876,6 +961,10 @@ void
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sync_crash()
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{
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#if defined(MSIIEP)
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/* we are back from prom */
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msiiep_swap_endian(1);
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#endif
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panic("PROM sync command");
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}
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@ -985,7 +1074,11 @@ extern struct sparc_bus_space_tag mainbus_space_tag;
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#if defined(SUN4M)
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static const char *const openboot_special4m[] = {
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/* find these first */
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#if !defined(MSIIEP)
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"obio", /* smart enough to get eeprom/etc mapped */
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#else
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"pci", /* ms-IIep */
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#endif
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"",
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/* ignore these (end with NULL) */
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@ -1001,6 +1094,7 @@ extern struct sparc_bus_space_tag mainbus_space_tag;
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"openprom",
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"options",
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"packages",
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"udp", /* OFW in Krups */
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/* we also skip any nodes with device_type == "cpu" */
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NULL
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};
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@ -1488,6 +1582,8 @@ getdevunit(name, unit)
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#define BUSCLASS_XDC 6
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#define BUSCLASS_XYC 7
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#define BUSCLASS_FDC 8
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#define BUSCLASS_PCIC 9
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#define BUSCLASS_PCI 10
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static int bus_class __P((struct device *));
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static char *bus_compatible __P((char *));
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@ -1515,6 +1611,8 @@ static struct {
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{ "xdc", BUSCLASS_XDC },
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{ "xyc", BUSCLASS_XYC },
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{ "fdc", BUSCLASS_FDC },
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{ "msiiep", BUSCLASS_PCIC },
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{ "pci", BUSCLASS_PCI },
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};
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/*
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@ -1531,6 +1629,7 @@ static struct {
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{ "PTI,isp", "isp" },
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{ "ptisp", "isp" },
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{ "SUNW,fdtwo", "fdc" },
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{ "network", "hme" }, /* Krups */
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};
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static char *
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@ -1582,6 +1681,8 @@ instance_match(dev, aux, bp)
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struct mainbus_attach_args *ma;
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struct sbus_attach_args *sa;
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struct iommu_attach_args *iom;
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struct pcibus_attach_args *pba;
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struct pci_attach_args *pa;
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/*
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* Several devices are represented on bootpaths in one of
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@ -1642,6 +1743,24 @@ instance_match(dev, aux, bp)
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}
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break;
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case BUSCLASS_PCIC:
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pba = aux;
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DPRINTF(ACDB_BOOTDEV, ("instance_match: pci bus "
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"want bus %d pa %#x have bus %d pa %#x\n",
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bp->val[0], bp->val[1], pba->pba_bus, MSIIEP_PCIC_PA));
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if ((int)bp->val[0] == pba->pba_bus
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&& (bus_addr_t)bp->val[1] == MSIIEP_PCIC_PA)
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return (1);
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break;
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case BUSCLASS_PCI:
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pa = aux;
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DPRINTF(ACDB_BOOTDEV, ("instance_match: pci device "
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"want dev %d function %d have dev %d function %d\n",
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bp->val[0], bp->val[1], pa->pa_device, pa->pa_function));
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if ((u_int)bp->val[0] == pa->pa_device
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&& (u_int)bp->val[1] == pa->pa_function)
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return (1);
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break;
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default:
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break;
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}
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