+ enable nested interrupts. This change stopped silo overflow messages
at 115200bps. + disable all hard interrupts by default. + rewrite s3c2xx0_(un)mask_interrupt() to make them faster.
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@ -1,4 +1,4 @@
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/* $NetBSD: s3c2800_intr.c,v 1.5 2003/07/15 00:24:48 lukem Exp $ */
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/* $NetBSD: s3c2800_intr.c,v 1.6 2003/07/30 18:25:50 bsh Exp $ */
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/*
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* Copyright (c) 2002 Fujitsu Component Limited
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@ -38,7 +38,7 @@
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*/
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#include <sys/cdefs.h>
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__KERNEL_RCSID(0, "$NetBSD: s3c2800_intr.c,v 1.5 2003/07/15 00:24:48 lukem Exp $");
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__KERNEL_RCSID(0, "$NetBSD: s3c2800_intr.c,v 1.6 2003/07/30 18:25:50 bsh Exp $");
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#include <sys/param.h>
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#include <sys/systm.h>
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@ -60,7 +60,8 @@ struct s3c2xx0_intr_dispatch handler[ICU_LEN];
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__volatile int softint_pending;
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__volatile int current_spl_level;
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__volatile int intr_mask;
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__volatile int intr_mask; /* XXX: does this need to be volatile? */
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__volatile int global_intr_mask = 0; /* mask some interrupts at all spl level */
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/* interrupt masks for each level */
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int s3c2xx0_imask[NIPL];
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@ -101,36 +102,38 @@ s3c2800_irq_handler(struct clockframe *frame)
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saved_spl_level = current_spl_level;
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/* get pending IRQs */
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irqbits = icreg(INTCTL_IRQPND) & ICU_INT_HWMASK;
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while ((irqbits = icreg(INTCTL_IRQPND) & ICU_INT_HWMASK) != 0) {
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for (irqno = ICU_LEN-1; irqno >= 0; --irqno)
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if (irqbits & (1<<irqno))
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break;
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if (irqno < 0)
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break;
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for (irqno = 0; irqbits; ++irqno) {
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if ((irqbits & (1 << irqno)) == 0)
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continue;
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/* raise spl to stop interrupts of lower priorities */
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if (saved_spl_level < handler[irqno].level)
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s3c2xx0_setipl(handler[irqno].level);
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/* clear pending bit */
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icreg(INTCTL_SRCPND) = PENDING_CLEAR_MASK & (1 << irqno);
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#ifdef notyet
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/* Enable interrupt */
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#endif
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enable_interrupts(I32_bit); /* allow nested interrupts */
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(*handler[irqno].func) (
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handler[irqno].cookie == 0
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? frame : handler[irqno].cookie);
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#ifdef notyet
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/* Disable interrupt */
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#endif
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irqbits &= ~(1 << irqno);
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}
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disable_interrupts(I32_bit);
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/* restore spl to that was when this interrupt happen */
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s3c2xx0_setipl(saved_spl_level);
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}
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if (softint_pending & intr_mask)
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s3c2xx0_do_pending();
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s3c2xx0_do_pending(1);
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}
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static const u_char s3c2800_ist[] = {
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@ -181,8 +184,7 @@ s3c2800_intr_establish(int irqno, int level, int type,
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GPIO_EXTINTR, reg);
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}
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intr_mask = s3c2xx0_imask[current_spl_level];
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*s3c2xx0_intr_mask_reg = intr_mask;
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s3c2xx0_setipl(current_spl_level);
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restore_interrupts(save);
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@ -1,8 +1,8 @@
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/* $NetBSD: s3c2xx0_intr.c,v 1.4 2003/07/15 00:24:49 lukem Exp $ */
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/* $NetBSD: s3c2xx0_intr.c,v 1.5 2003/07/30 18:25:50 bsh Exp $ */
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/*
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* Copyright (c) 2002 Fujitsu Component Limited
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* Copyright (c) 2002 Genetec Corporation
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* Copyright (c) 2002, 2003 Fujitsu Component Limited
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* Copyright (c) 2002, 2003 Genetec Corporation
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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@ -73,7 +73,7 @@
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*/
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#include <sys/cdefs.h>
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__KERNEL_RCSID(0, "$NetBSD: s3c2xx0_intr.c,v 1.4 2003/07/15 00:24:49 lukem Exp $");
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__KERNEL_RCSID(0, "$NetBSD: s3c2xx0_intr.c,v 1.5 2003/07/30 18:25:50 bsh Exp $");
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#include <sys/param.h>
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#include <sys/systm.h>
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@ -160,95 +160,60 @@ static void
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init_interrupt_masks(void)
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{
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int i;
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s3c2xx0_imask[IPL_NONE] = 0xffffffff;
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for (i = IPL_BIO; i < IPL_SOFTSERIAL; ++i)
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s3c2xx0_imask[i] = SI_TO_IRQBIT(SI_SOFTSERIAL);
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for (; i < NIPL; ++i)
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s3c2xx0_imask[i] = 0;
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s3c2xx0_imask[IPL_NONE] = SI_TO_IRQBIT(SI_SOFTSERIAL) |
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SI_TO_IRQBIT(SI_SOFTNET) | SI_TO_IRQBIT(SI_SOFTCLOCK) |
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SI_TO_IRQBIT(SI_SOFT);
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/*
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* Initialize the soft interrupt masks to block themselves.
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*/
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s3c2xx0_imask[IPL_SOFT] = ~SI_TO_IRQBIT(SI_SOFT);
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s3c2xx0_imask[IPL_SOFTCLOCK] = ~SI_TO_IRQBIT(SI_SOFTCLOCK);
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s3c2xx0_imask[IPL_SOFTNET] = ~SI_TO_IRQBIT(SI_SOFTNET);
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s3c2xx0_imask[IPL_SOFT] = SI_TO_IRQBIT(SI_SOFTSERIAL) |
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SI_TO_IRQBIT(SI_SOFTNET) | SI_TO_IRQBIT(SI_SOFTCLOCK);
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/*
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* splsoftclock() is the only interface that users of the
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* generic software interrupt facility have to block their
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* soft intrs, so splsoftclock() must also block IPL_SOFT.
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*/
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s3c2xx0_imask[IPL_SOFTCLOCK] &= s3c2xx0_imask[IPL_SOFT];
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s3c2xx0_imask[IPL_SOFTCLOCK] = SI_TO_IRQBIT(SI_SOFTSERIAL) |
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SI_TO_IRQBIT(SI_SOFTNET);
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/*
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* splsoftnet() must also block splsoftclock(), since we don't
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* want timer-driven network events to occur while we're
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* processing incoming packets.
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*/
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s3c2xx0_imask[IPL_SOFTNET] &= s3c2xx0_imask[IPL_SOFTCLOCK];
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s3c2xx0_imask[IPL_SOFTNET] = SI_TO_IRQBIT(SI_SOFTSERIAL);
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for (i = IPL_BIO; i < IPL_SOFTSERIAL; ++i)
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s3c2xx0_imask[i] = SI_TO_IRQBIT(SI_SOFTSERIAL);
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for (; i < NIPL; ++i)
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s3c2xx0_imask[i] = 0;
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}
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/*
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* Disable/enable interrupts.
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* This is for S3C2XX0's intergrated UART, which can't disable tx/rx
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* interrupts without disabling tx/rx by means of UART regsiters.
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*/
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void
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s3c2xx0_mask_interrupts(int mask)
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{
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int save = disable_interrupts(I32_bit);
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int i;
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for (i = 0; i < NIPL - 1; ++i)
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s3c2xx0_imask[i] &= ~mask;
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intr_mask = s3c2xx0_imask[current_spl_level];
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*s3c2xx0_intr_mask_reg = intr_mask;
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restore_interrupts(save);
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}
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void
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s3c2xx0_unmask_interrupts(int mask)
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{
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int save = disable_interrupts(I32_bit);
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int i;
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for (i = 0; i < ICU_LEN; ++i) {
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if ((mask & (1 << i)) == 0)
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continue;
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s3c2xx0_update_intr_masks(i, s3c2xx0_ilevel[i]);
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}
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intr_mask = s3c2xx0_imask[current_spl_level];
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*s3c2xx0_intr_mask_reg = intr_mask;
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restore_interrupts(save);
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}
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void
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s3c2xx0_do_pending(void)
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s3c2xx0_do_pending(int enable_int)
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{
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static __cpu_simple_lock_t processing = __SIMPLELOCK_UNLOCKED;
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int oldirqstate, spl_save;
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int oldirqstate, irqstate, spl_save;
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if (__cpu_simple_lock_try(&processing) == 0)
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return;
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spl_save = current_spl_level;
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oldirqstate = disable_interrupts(I32_bit);
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oldirqstate = irqstate = disable_interrupts(I32_bit);
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if (enable_int)
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irqstate &= ~I32_bit;
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#define DO_SOFTINT(si,ipl) \
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if ((softint_pending & intr_mask) & SI_TO_IRQBIT(si)) { \
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softint_pending &= ~SI_TO_IRQBIT(si); \
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__raise(ipl); \
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restore_interrupts(oldirqstate); \
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restore_interrupts(irqstate); \
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softintr_dispatch(si); \
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oldirqstate = disable_interrupts(I32_bit); \
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disable_interrupts(I32_bit); \
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s3c2xx0_setipl(spl_save); \
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}
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@ -297,24 +262,28 @@ s3c2xx0_intr_init(struct s3c2xx0_intr_dispatch * dispatch_table, int icu_len)
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_splraise(IPL_SERIAL);
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enable_interrupts(I32_bit);
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}
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#undef splx
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void
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splx(int ipl)
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{
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s3c2xx0_splx(ipl);
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}
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#undef _splraise
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int
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_splraise(int ipl)
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{
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return s3c2xx0_splraise(ipl);
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}
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#undef _spllower
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int
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_spllower(int ipl)
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{
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return s3c2xx0_spllower(ipl);
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}
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#undef _setsoftintr
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void
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_setsoftintr(int si)
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@ -1,8 +1,8 @@
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/* $NetBSD: s3c2xx0_intr.h,v 1.2 2003/01/02 23:37:59 thorpej Exp $ */
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/* $NetBSD: s3c2xx0_intr.h,v 1.3 2003/07/30 18:25:50 bsh Exp $ */
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/*
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* Copyright (c) 2002 Fujitsu Component Limited
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* Copyright (c) 2002 Genetec Corporation
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* Copyright (c) 2002, 2003 Fujitsu Component Limited
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* Copyright (c) 2002, 2003 Genetec Corporation
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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@ -87,21 +87,38 @@ extern volatile uint32_t *s3c2xx0_intr_mask_reg;
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extern __volatile int current_spl_level;
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extern __volatile int intr_mask;
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extern __volatile int global_intr_mask;
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extern __volatile int softint_pending;
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extern int s3c2xx0_imask[];
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extern int s3c2xx0_ilevel[];
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void s3c2xx0_do_pending(void);
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void s3c2xx0_do_pending(int);
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void s3c2xx0_update_intr_masks( int, int );
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void s3c2xx0_mask_interrupts(int);
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void s3c2xx0_unmask_interrupts(int);
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static __inline void
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s3c2xx0_mask_interrupts(int mask)
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{
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int save = disable_interrupts(I32_bit);
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global_intr_mask |= mask;
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*s3c2xx0_intr_mask_reg = intr_mask & ~global_intr_mask;
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restore_interrupts(save);
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}
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static __inline void
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s3c2xx0_unmask_interrupts(int mask)
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{
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int save = disable_interrupts(I32_bit);
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global_intr_mask &= ~mask;
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*s3c2xx0_intr_mask_reg = intr_mask & ~global_intr_mask;
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restore_interrupts(save);
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}
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static __inline void
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s3c2xx0_setipl(int new)
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{
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current_spl_level = new;
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intr_mask = s3c2xx0_imask[current_spl_level];
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*s3c2xx0_intr_mask_reg = intr_mask;
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*s3c2xx0_intr_mask_reg = intr_mask & ~global_intr_mask;
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}
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@ -116,7 +133,7 @@ s3c2xx0_splx(int new)
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/* If there are software interrupts to process, do it. */
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if (softint_pending & intr_mask)
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s3c2xx0_do_pending();
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s3c2xx0_do_pending(0);
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}
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@ -152,7 +169,7 @@ s3c2xx0_setsoftintr(int si)
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/* Process unmasked pending soft interrupts. */
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if ( softint_pending & intr_mask )
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s3c2xx0_do_pending();
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s3c2xx0_do_pending(0);
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}
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