Support Plathome OpenMicroServer (OMS-AL400).
http://www.plathome.co.jp/products/oms400/index.html (sorry japanese only).
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shige
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/* $NetBSD: omsal400.c,v 1.1 2006/02/23 17:14:01 shige Exp $ */
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/*-
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* Copyright (c) 2006 Shigeyuki Fukushima.
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* All rights reserved.
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*
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* Written by Shigeyuki Fukushima.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above
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* copyright notice, this list of conditions and the following
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* disclaimer in the documentation and/or other materials provided
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* with the distribution.
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* 3. The name of the author may not be used to endorse or promote
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* products derived from this software without specific prior
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* written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS
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* OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
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* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY
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* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE
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* GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
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* WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
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* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
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* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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#include <sys/cdefs.h>
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__KERNEL_RCSID(0, "$NetBSD: omsal400.c,v 1.1 2006/02/23 17:14:01 shige Exp $");
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#include <sys/param.h>
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#include <machine/bus.h>
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#include <machine/locore.h>
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#include <evbmips/alchemy/obiovar.h>
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#include <evbmips/alchemy/board.h>
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#include <evbmips/alchemy/omsal400reg.h>
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#define GET16(x) \
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(*((volatile uint16_t *)MIPS_PHYS_TO_KSEG1(x)))
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#define PUT16(x, v) \
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(*((volatile uint16_t *)MIPS_PHYS_TO_KSEG1(x)) = (v))
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static void omsal400_init(void);
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static int omsal400_pci_intr_map(struct pci_attach_args *,
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pci_intr_handle_t *);
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static void omsal400_poweroff(void);
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static void omsal400_reboot(void);
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static const struct obiodev omsal400_devices[] = {
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{ NULL },
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};
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static struct alchemy_board omsal400_info = {
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"Plathome Open Micro Sever AL400/AMD Alchemy Au1550",
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omsal400_devices,
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omsal400_init,
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omsal400_pci_intr_map,
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omsal400_reboot,
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omsal400_poweroff,
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};
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const struct alchemy_board *
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board_info(void)
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{
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return &omsal400_info;
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}
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void
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omsal400_init(void)
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{
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/* uint16_t whoami; */
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if (MIPS_PRID_COPTS(cpu_id) != MIPS_AU1550)
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panic("omsal400: CPU not Au1550");
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#if 0 /* XXX: TODO borad identification */
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/* check the whoami register for a match */
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whoami = GET16(DBAU1550_WHOAMI);
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if (DBAU1550_WHOAMI_BOARD(whoami) != DBAU1550_WHOAMI_DBAU1550_REV1)
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panic("dbau1550: WHOAMI (%x) not DBAu1550!", whoami);
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printf("DBAu1550 (cabernet), CPLDv%d, ",
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DBAU1550_WHOAMI_CPLD(whoami));
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if (DBAU1550_WHOAMI_DAUGHTER(whoami) != 0xf)
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printf("daughtercard 0x%x\n",
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DBAU1550_WHOAMI_DAUGHTER(whoami));
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else
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printf("no daughtercard\n");
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#endif
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/* leave console and clocks alone -- YAMON should have got it right! */
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}
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int
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omsal400_pci_intr_map(struct pci_attach_args *pa, pci_intr_handle_t *ihp)
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{
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/*
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* This platform has 4 PCI devices:
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* dev 1 (PCI_INTD): PCI Connector
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* dev 2 (PCI_INTC): NEC USB 2.0 uPD720101
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* dev 3 (PCI_INTB): Intel GB Ether 82541PI
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* dev 4 (PCI_INTA): Intel GB Ether 82541PI
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*/
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static const int irqmap[5/*device*/][4/*pin*/] = {
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{ 6, -1, -1, -1 }, /* 1: PCI Connecter (not used) */
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{ 5, 5, 5, -1 }, /* 2: NEC USB 2.0 */
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{ 2, -1, -1, -1 }, /* 3: Intel GbE */
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{ 1, -1, -1, -1 }, /* 4: Intel GbE */
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};
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int pin, dev, irq;
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/* if interrupt pin not used... */
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if ((pin = pa->pa_intrpin) == 0)
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return 1;
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if (pin > 4) {
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printf("pci: bad interrupt pin %d\n", pin);
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return 1;
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}
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pci_decompose_tag(pa->pa_pc, pa->pa_intrtag, NULL, &dev, NULL);
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if ((dev < 1) || (dev > 4)) {
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printf("pci: bad device %d\n", dev);
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return 1;
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}
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if ((irq = irqmap[dev - 1][pin - 1]) == -1) {
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printf("pci: no IRQ routing for device %d pin %d\n", dev, pin);
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return 1;
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}
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*ihp = irq;
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return 0;
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}
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void
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omsal400_reboot(void)
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{
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/* XXX */
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}
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void
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omsal400_poweroff(void)
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{
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printf("\n- poweroff -\n");
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/* XXX */
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}
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@ -0,0 +1,53 @@
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/* $NetBSD: omsal400reg.h,v 1.1 2006/02/23 17:14:01 shige Exp $ */
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/*-
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* Copyright (c) 2006 Shigeyuki Fukushima.
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* All rights reserved.
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*
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* Written by Shigeyuki Fukushima.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above
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* copyright notice, this list of conditions and the following
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* disclaimer in the documentation and/or other materials provided
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* with the distribution.
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* 3. The name of the author may not be used to endorse or promote
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* products derived from this software without specific prior
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* written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS
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* OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
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* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY
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* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE
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* GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
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* WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
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* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
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* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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/*
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* Board-specific registers for OMS-AL400.
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*/
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/*
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* OMSAL400_WHOAMI
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*/
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/*
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* OMSAL400_BCSR
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*/
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/*
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* OMSAL400_BOARD_SPECIFIC
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*/
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/*
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* OMSAL400_SOFTWARE_RESET
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*/
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@ -0,0 +1,47 @@
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# $NetBSD: OMSAL400,v 1.1 2006/02/23 17:14:01 shige Exp $
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#
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# Kernel config for the Open Micro Server AL400.
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include "arch/evbmips/conf/ALCHEMY"
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no options ALCHEMY_AU1000
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no options ALCHEMY_AU1100
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no options ALCHEMY_AU1500
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no options ALCHEMY_AU1550
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no options ALCHEMY_GENERIC
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# configure out local board support
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makeoptions TEXTADDR="0x80100000"
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options ALCHEMY_AU1550
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options ALCHEMY_OMSAL400
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options PCI_NETBSD_CONFIGURE
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aupci* at aubus? addr ?
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pci* at aupci?
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# Note that this is just fairly random selection of PCI devices.
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# Only the hptide controller is actually on-board.
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# PCI devices
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wm* at pci? dev ? function ? # Intel 8254x gigabit
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ehci* at pci? dev ? function ? # Enhanced Host Controller
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ohci* at pci? dev ? function ? # Open Host Controller
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hptide* at pci? dev ? function ? # Triones/HighPoint IDE
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# MII
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lxtphy* at mii? phy ? # Level One LXT-970 PHYs
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igphy* at mii? phy ? # Intel IGP01E1000
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# USB
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usb* at ohci?
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usb* at ehci?
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# ATA
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atabus* at ata?
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wd* at atabus? drive ? flags 0x0000
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atapibus* at atabus?
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cd* at atapibus? drive ? flags 0x0000 # ATAPI CD-ROM drives
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sd* at atapibus? drive ? flags 0x0000 # ATAPI disk drives
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uk* at atapibus? drive ? flags 0x0000 # ATAPI unknown
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@ -1,10 +1,11 @@
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# $NetBSD: files.alchemy,v 1.4 2006/02/23 04:40:53 gdamore Exp $
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# $NetBSD: files.alchemy,v 1.5 2006/02/23 17:14:01 shige Exp $
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# Platform support - select just one, please
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defflag opt_alchemy.h ALCHEMY_GENERIC
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ALCHEMY_DBAU1550
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ALCHEMY_DBAU1500
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ALCHEMY_MTX1
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ALCHEMY_OMSAL400
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file arch/evbmips/alchemy/mach_intr.c
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@ -15,6 +16,7 @@ file arch/evbmips/alchemy/genericbd.c alchemy_generic
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file arch/evbmips/alchemy/dbau1500.c alchemy_dbau1500
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file arch/evbmips/alchemy/dbau1550.c alchemy_dbau1550
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file arch/evbmips/alchemy/mtx-1.c alchemy_mtx1
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file arch/evbmips/alchemy/omsal400.c alchemy_omsal400
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file arch/evbmips/alchemy/pciide_machdep.c pciide_common
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file arch/mips/mips/bus_dma.c
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