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Replace Fastlane and Blizzard SCSI driver frontends, using the machine 

independent ncr53c9x driver.  Add 12x0-IV support to the 1230 driver, and
add Cyberstorm SCSI I and II drivers.
This commit is contained in:
mhitch 1997-10-04 04:01:17 +00:00
parent 3d83dee874
commit 66e9e9018c
12 changed files with 2712 additions and 1035 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

8
sys/arch/amiga/conf/GENERIC
View File

@ -1,4 +1,4 @@
# $NetBSD: GENERIC,v 1.88 1997/09/27 22:44:33 is Exp $
# $NetBSD: GENERIC,v 1.89 1997/10/04 04:02:05 mhitch Exp $
#
# GENERIC AMIGA
@ -230,8 +230,10 @@ wesc0 at zbus0 # Warp Engine scsi
afsc0 at zbus0 # A4091 scsi
aftsc0 at mainbus0 # A4000T scsi
flsc0 at zbus0 # FastlaneZ3 scsi
bzsc0 at zbus0 # Blizzard 1230 I,II scsi
bzsc0 at zbus0 # Blizzard 1230 I,II, IV scsi
bztzsc0 at zbus0 # Blizzard 2060 scsi
cbsc0 at zbus0 # CyberSCSI I
cbiisc0 at zbus0 # CyberSCSI II
empsc0 at zbus0 # Emplant scsi
idesc0 at mainbus0 # A4000 & A1200 IDE
drsc0 at mainbus0 # DraCo scsi
@ -251,6 +253,8 @@ scsibus* at aftsc0
scsibus* at flsc0
scsibus* at bzsc0
scsibus* at bztzsc0
scsibus* at cbsc0
scsibus* at cbiisc0
scsibus* at empsc0
scsibus* at idesc0
scsibus* at drsc0

22
sys/arch/amiga/conf/files.amiga
View File

@ -1,4 +1,4 @@
# $NetBSD: files.amiga,v 1.64 1997/09/28 20:50:00 is Exp $
# $NetBSD: files.amiga,v 1.65 1997/10/04 04:02:03 mhitch Exp $
# maxpartitions must be first item in files.${ARCH}.newconf
maxpartitions 16 # NOTE THAT AMIGA IS SPECIAL!
@ -272,24 +272,32 @@ attach aftsc at mainbus
file arch/amiga/dev/afsc.c afsc | aftsc needs-flag
# Emulex ESP216 & FAS216 controllers
define sfas
file arch/amiga/dev/sfas.c sfas
# FastlaneZ3
device flsc: scsi, sfas
device flsc: scsi, ncr53c9x
attach flsc at zbus
file arch/amiga/dev/flsc.c flsc needs-flag
# Blizzard1230-I,II
device bzsc: scsi, sfas
# Blizzard12x0-I,II and IV
device bzsc: scsi, ncr53c9x
attach bzsc at zbus
file arch/amiga/dev/bzsc.c bzsc needs-flag
# Blizzard2060 scsi
device bztzsc: scsi, sfas
device bztzsc: scsi, ncr53c9x
attach bztzsc at zbus
file arch/amiga/dev/bztzsc.c bztzsc needs-flag
# CyberSCSI [I] scsi
device cbsc: scsi, ncr53c9x
attach cbsc at zbus
file arch/amiga/dev/cbsc.c cbsc needs-flag
# CyberSCSI MKII scsi
device cbiisc: scsi, ncr53c9x
attach cbiisc at zbus
file arch/amiga/dev/cbiisc.c cbiisc needs-flag
# EMPLANT
device empsc: scsi, sci
attach empsc at zbus

761
sys/arch/amiga/dev/bzsc.c
View File

@ -1,6 +1,7 @@
/* $NetBSD: bzsc.c,v 1.16 1997/08/27 11:23:04 bouyer Exp $ */
/* $NetBSD: bzsc.c,v 1.17 1997/10/04 04:01:17 mhitch Exp $ */
/*
* Copyright (c) 1997 Michael L. Hitch
* Copyright (c) 1995 Daniel Widenfalk
* Copyright (c) 1994 Christian E. Hopps
* Copyright (c) 1982, 1990 The Regents of the University of California.
@ -16,8 +17,8 @@
* documentation and/or other materials provided with the distribution.
* 3. All advertising materials mentioning features or use of this software
* must display the following acknowledgement:
* This product includes software developed by the University of
* California, Berkeley and its contributors.
* This product includes software developed by Daniel Widenfalk
* and Michael L. Hitch.
* 4. Neither the name of the University nor the names of its contributors
* may be used to endorse or promote products derived from this software
* without specific prior written permission.
@ -33,372 +34,512 @@
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
* SUCH DAMAGE.
*
* @(#)dma.c
*/
/*
* Initial amiga Blizzard 1230-II driver by Daniel Widenfalk. Conversion to
* 53c9x MI driver and Blizzard IV by Michael L. Hitch (mhitch@montana.edu).
*/
#include <sys/types.h>
#include <sys/param.h>
#include <sys/systm.h>
#include <sys/kernel.h>
#include <sys/errno.h>
#include <sys/ioctl.h>
#include <sys/device.h>
#include <sys/buf.h>
#include <sys/proc.h>
#include <sys/user.h>
#include <sys/queue.h>
#include <dev/scsipi/scsi_all.h>
#include <dev/scsipi/scsipi_all.h>
#include <dev/scsipi/scsiconf.h>
#include <vm/vm.h>
#include <vm/vm_kern.h>
#include <vm/vm_page.h>
#include <machine/pmap.h>
#include <amiga/amiga/custom.h>
#include <amiga/amiga/cc.h>
#include <amiga/amiga/device.h>
#include <dev/scsipi/scsi_message.h>
#include <machine/cpu.h>
#include <machine/param.h>
#include <dev/ic/ncr53c9xreg.h>
#include <dev/ic/ncr53c9xvar.h>
#include <amiga/amiga/isr.h>
#include <amiga/dev/sfasreg.h>
#include <amiga/dev/sfasvar.h>
#include <amiga/dev/zbusvar.h>
#include <amiga/dev/bzscreg.h>
#include <amiga/dev/bzscvar.h>
#include <amiga/dev/zbusvar.h>
void bzscattach __P((struct device *, struct device *, void *));
int bzscmatch __P((struct device *, struct cfdata *, void *));
struct scsipi_adapter bzsc_scsiswitch = {
sfas_scsicmd,
sfas_minphys,
0, /* no lun support */
0, /* no lun support */
};
struct scsipi_device bzsc_scsidev = {
NULL, /* use default error handler */
NULL, /* do not have a start functio */
NULL, /* have no async handler */
NULL, /* Use default done routine */
};
void bzscattach __P((struct device *, struct device *, void *));
int bzscmatch __P((struct device *, struct cfdata *, void *));
/* Linkup to the rest of the kernel */
struct cfattach bzsc_ca = {
sizeof(struct bzsc_softc), bzscmatch, bzscattach
};
struct cfdriver bzsc_cd = {
NULL, "bzsc", DV_DULL, NULL, 0
NULL, "bzsc", DV_DULL
};
int bzsc_intr __P((void *));
void bzsc_set_dma_adr __P((struct sfas_softc *sc, vm_offset_t ptr, int mode));
void bzsc_set_dma_tc __P((struct sfas_softc *sc, unsigned int len));
int bzsc_setup_dma __P((struct sfas_softc *sc, vm_offset_t ptr, int len,
int mode));
int bzsc_build_dma_chain __P((struct sfas_softc *sc,
struct sfas_dma_chain *chain, void *p, int l));
int bzsc_need_bump __P((struct sfas_softc *sc, vm_offset_t ptr, int len));
void bzsc_led_dummy __P((struct sfas_softc *sc, int mode));
struct scsipi_adapter bzsc_switch = {
ncr53c9x_scsi_cmd,
minphys, /* no max at this level; handled by DMA code */
NULL,
NULL,
};
struct scsipi_device bzsc_dev = {
NULL, /* Use default error handler */
NULL, /* have a queue, served by this */
NULL, /* have no async handler */
NULL, /* Use default 'done' routine */
};
/*
* if we are an Advanced Systems & Software FastlaneZ3
* Functions and the switch for the MI code.
*/
u_char bzsc_read_reg __P((struct ncr53c9x_softc *, int));
void bzsc_write_reg __P((struct ncr53c9x_softc *, int, u_char));
int bzsc_dma_isintr __P((struct ncr53c9x_softc *));
void bzsc_dma_reset __P((struct ncr53c9x_softc *));
int bzsc_dma_intr __P((struct ncr53c9x_softc *));
int bzsc_dma_setup __P((struct ncr53c9x_softc *, caddr_t *,
size_t *, int, size_t *));
void bzsc_dma_go __P((struct ncr53c9x_softc *));
void bzsc_dma_stop __P((struct ncr53c9x_softc *));
int bzsc_dma_isactive __P((struct ncr53c9x_softc *));
struct ncr53c9x_glue bzsc_glue = {
bzsc_read_reg,
bzsc_write_reg,
bzsc_dma_isintr,
bzsc_dma_reset,
bzsc_dma_intr,
bzsc_dma_setup,
bzsc_dma_go,
bzsc_dma_stop,
bzsc_dma_isactive,
0,
};
/* Maximum DMA transfer length to reduce impact on high-speed serial input */
u_long bzsc_max_dma = 1024;
extern int ser_open_speed;
u_long bzsc_cnt_pio = 0; /* number of PIO transfers */
u_long bzsc_cnt_dma = 0; /* number of DMA transfers */
u_long bzsc_cnt_dma2 = 0; /* number of DMA transfers broken up */
u_long bzsc_cnt_dma3 = 0; /* number of pages combined */
#ifdef DEBUG
struct {
u_char hardbits;
u_char status;
u_char xx;
u_char yy;
} bzsc_trace[128];
int bzsc_trace_ptr = 0;
int bzsc_trace_enable = 1;
void bzsc_dump __P((void));
#endif
/*
* if we are a Phase5 Blizzard 12x0 II or IV
*/
int
bzscmatch(pdp, cfp, auxp)
struct device *pdp;
struct cfdata *cfp;
void *auxp;
bzscmatch(parent, cf, aux)
struct device *parent;
struct cfdata *cf;
void *aux;
{
struct zbus_args *zap;
vu_char *ta;
volatile u_char *regs;
zap = aux;
if (zap->manid != 0x2140)
return(0); /* It's not Phase 5 */
if (zap->prodid != 11 && zap->prodid != 17)
return(0); /* Not Blizzard 12x0 */
if (!is_a1200())
return(0); /* And not A1200 */
regs = &((volatile u_char *)zap->va)[0x8000];
if (zap->prodid == 11) {
/*
* 12x0 II is product ID 11, but some IV may have the
* same product ID. Check for IV first, then II.
*/
if (!badaddr((caddr_t)regs)) {
regs[NCR_CFG1 * 4] = 0;
regs[NCR_CFG1 * 4] = NCRCFG1_PARENB | 7;
delay(5);
if (regs[NCR_CFG1 * 4] == (NCRCFG1_PARENB | 7))
return(1); /* 12x0 IV */
}
regs = &((volatile u_char *)zap->va)[0x10000];
}
if (badaddr((caddr_t)regs))
return(0);
zap = auxp;
if (zap->manid != 0x2140 || zap->prodid != 11)
regs[NCR_CFG1 * 4] = 0;
regs[NCR_CFG1 * 4] = NCRCFG1_PARENB | 7;
delay(5);
if (regs[NCR_CFG1 * 4] != (NCRCFG1_PARENB | 7))
return(0);
ta = (vu_char *)(((char *)zap->va)+0x10010);
if (badbaddr((caddr_t)ta))
return(0);
*ta = 0;
*ta = 1;
DELAY(5);
if (*ta != 1)
return(0);
return(1);
}
/*
* Attach this instance, and then all the sub-devices
*/
void
bzscattach(pdp, dp, auxp)
struct device *pdp;
struct device *dp;
void *auxp;
bzscattach(parent, self, aux)
struct device *parent, *self;
void *aux;
{
struct bzsc_softc *sc;
struct bzsc_softc *bsc = (void *)self;
struct ncr53c9x_softc *sc = &bsc->sc_ncr53c9x;
struct zbus_args *zap;
bzsc_regmap_p rp;
vu_char *fas;
extern u_long scsi_nosync;
extern int shift_nosync;
extern int ncr53c9x_debug;
volatile u_char *regs;
zap = auxp;
fas = (vu_char *)(((char *)zap->va)+0x10000);
/*
* Set up the glue for MI code early; we use some of it here.
*/
sc->sc_glue = &bzsc_glue;
sc = (struct bzsc_softc *)dp;
rp = &sc->sc_regmap;
rp->FAS216.sfas_tc_low = &fas[0x00];
rp->FAS216.sfas_tc_mid = &fas[0x02];
rp->FAS216.sfas_fifo = &fas[0x04];
rp->FAS216.sfas_command = &fas[0x06];
rp->FAS216.sfas_dest_id = &fas[0x08];
rp->FAS216.sfas_timeout = &fas[0x0A];
rp->FAS216.sfas_syncper = &fas[0x0C];
rp->FAS216.sfas_syncoff = &fas[0x0E];
rp->FAS216.sfas_config1 = &fas[0x10];
rp->FAS216.sfas_clkconv = &fas[0x12];
rp->FAS216.sfas_test = &fas[0x14];
rp->FAS216.sfas_config2 = &fas[0x16];
rp->FAS216.sfas_config3 = &fas[0x18];
rp->FAS216.sfas_tc_high = &fas[0x1C];
rp->FAS216.sfas_fifo_bot = &fas[0x1E];
rp->cclkaddr = &fas[0x21];
rp->epowaddr = &fas[0x31];
sc->sc_softc.sc_fas = (sfas_regmap_p)rp;
sc->sc_softc.sc_spec = 0;
sc->sc_softc.sc_led = bzsc_led_dummy;
sc->sc_softc.sc_setup_dma = bzsc_setup_dma;
sc->sc_softc.sc_build_dma_chain = bzsc_build_dma_chain;
sc->sc_softc.sc_need_bump = bzsc_need_bump;
sc->sc_softc.sc_clock_freq = 40; /* BlizzardII 1230 runs at 40MHz? */
sc->sc_softc.sc_timeout = 250; /* Set default timeout to 250ms */
sc->sc_softc.sc_config_flags = 0;
sc->sc_softc.sc_host_id = 7;
sc->sc_softc.sc_bump_sz = NBPG;
sc->sc_softc.sc_bump_pa = 0x0;
sfasinitialize((struct sfas_softc *)sc);
sc->sc_softc.sc_link.scsipi_scsi.channel = SCSI_CHANNEL_ONLY_ONE;
sc->sc_softc.sc_link.adapter_softc = sc;
sc->sc_softc.sc_link.scsipi_scsi.adapter_target = sc->sc_softc.sc_host_id;
sc->sc_softc.sc_link.adapter = &bzsc_scsiswitch;
sc->sc_softc.sc_link.device = &bzsc_scsidev;
sc->sc_softc.sc_link.openings = 1;
sc->sc_softc.sc_link.scsipi_scsi.max_target = 7;
sc->sc_softc.sc_link.type = BUS_SCSI;
printf("\n");
sc->sc_softc.sc_isr.isr_intr = bzsc_intr;
sc->sc_softc.sc_isr.isr_arg = &sc->sc_softc;
sc->sc_softc.sc_isr.isr_ipl = 2;
add_isr(&sc->sc_softc.sc_isr);
/* attach all scsi units on us */
config_found(dp, &sc->sc_softc.sc_link, scsiprint);
}
int
bzsc_intr(arg)
void *arg;
{
struct sfas_softc *dev = arg;
bzsc_regmap_p rp;
int quickints;
rp = (bzsc_regmap_p)dev->sc_fas;
if (!(*rp->FAS216.sfas_status & SFAS_STAT_INTERRUPT_PENDING))
return(0);
quickints = 16;
do {
dev->sc_status = *rp->FAS216.sfas_status;
dev->sc_interrupt = *rp->FAS216.sfas_interrupt;
if (dev->sc_interrupt & SFAS_INT_RESELECTED) {
dev->sc_resel[0] = *rp->FAS216.sfas_fifo;
dev->sc_resel[1] = *rp->FAS216.sfas_fifo;
/*
* Save the regs
*/
zap = aux;
regs = &((volatile u_char *)zap->va)[0x8000];
bsc->sc_dmabase = &regs[0x8000];
if (zap->prodid == 11) {
if (!badaddr((caddr_t)regs)) {
regs[NCR_CFG1 * 4] = 0;
regs[NCR_CFG1 * 4] = NCRCFG1_PARENB | 7;
delay(5);
if (regs[NCR_CFG1 * 4] != (NCRCFG1_PARENB | 7)) {
regs = &((volatile u_char *)zap->va)[0x10000];
bsc->sc_dmabase = &regs[0x21];
}
} else {
regs = &((volatile u_char *)zap->va)[0x10000];
bsc->sc_dmabase = &regs[0x21];
}
sfasintr(dev);
} while((*rp->FAS216.sfas_status & SFAS_STAT_INTERRUPT_PENDING) &&
--quickints);
return(1);
}
/* --------- */
void
bzsc_set_dma_adr(sc, ptr, mode)
struct sfas_softc *sc;
vm_offset_t ptr;
int mode;
{
bzsc_regmap_p rp;
unsigned long p;
rp = (bzsc_regmap_p)sc->sc_fas;
p = ((unsigned long)ptr)>>1;
if (mode == SFAS_DMA_WRITE)
p |= BZSC_DMA_WRITE;
else
p |= BZSC_DMA_READ;
*rp->epowaddr = (u_char)(p>>24) & 0xFF;
*rp->cclkaddr = (u_char)(p>>16) & 0xFF;
*rp->cclkaddr = (u_char)(p>> 8) & 0xFF;
*rp->cclkaddr = (u_char)(p ) & 0xFF;
}
/* Set DMA transfer counter */
void
bzsc_set_dma_tc(sc, len)
struct sfas_softc *sc;
unsigned int len;
{
*sc->sc_fas->sfas_tc_low = len; len >>= 8;
*sc->sc_fas->sfas_tc_mid = len; len >>= 8;
*sc->sc_fas->sfas_tc_high = len;
}
/* Initialize DMA for transfer */
int
bzsc_setup_dma(sc, ptr, len, mode)
struct sfas_softc *sc;
vm_offset_t ptr;
int len;
int mode;
{
int retval;
retval = 0;
switch(mode) {
case SFAS_DMA_READ:
case SFAS_DMA_WRITE:
bzsc_set_dma_adr(sc, ptr, mode);
bzsc_set_dma_tc(sc, len);
break;
case SFAS_DMA_CLEAR:
default:
retval = (*sc->sc_fas->sfas_tc_high << 16) |
(*sc->sc_fas->sfas_tc_mid << 8) |
*sc->sc_fas->sfas_tc_low;
bzsc_set_dma_tc(sc, 0);
break;
}
bsc->sc_reg = regs;
return(retval);
}
sc->sc_freq = 40; /* Clocked at 40Mhz */
/* Check if address and len is ok for DMA transfer */
int
bzsc_need_bump(sc, ptr, len)
struct sfas_softc *sc;
vm_offset_t ptr;
int len;
{
int p;
printf(": address %p", bsc->sc_reg);
p = (int)ptr & 0x03;
sc->sc_id = 7;
if (p) {
p = 4-p;
/*
* It is necessary to try to load the 2nd config register here,
* to find out what rev the FAS chip is, else the ncr53c9x_reset
* will not set up the defaults correctly.
*/
sc->sc_cfg1 = sc->sc_id | NCRCFG1_PARENB;
sc->sc_cfg2 = NCRCFG2_SCSI2 | NCRCFG2_FE;
sc->sc_cfg3 = 0x08 /*FCLK*/ | NCRESPCFG3_FSCSI | NCRESPCFG3_CDB;
sc->sc_rev = NCR_VARIANT_FAS216;
if (len < 256)
p = len;
}
/*
* This is the value used to start sync negotiations
* Note that the NCR register "SYNCTP" is programmed
* in "clocks per byte", and has a minimum value of 4.
* The SCSI period used in negotiation is one-fourth
* of the time (in nanoseconds) needed to transfer one byte.
* Since the chip's clock is given in MHz, we have the following
* formula: 4 * period = (1000 / freq) * 4
*/
sc->sc_minsync = 1000 / sc->sc_freq;
return(p);
}
/*
* get flags from -I argument and set cf_flags.
* NOTE: low 8 bits are to disable disconnect, and the next
* 8 bits are to disable sync.
*/
sc->sc_dev.dv_cfdata->cf_flags |= (scsi_nosync >> shift_nosync)
& 0xffff;
shift_nosync += 16;
/* Interrupt driven routines */
int
bzsc_build_dma_chain(sc, chain, p, l)
struct sfas_softc *sc;
struct sfas_dma_chain *chain;
void *p;
int l;
{
int n;
/* Use next 16 bits of -I argument to set ncr53c9x_debug flags */
ncr53c9x_debug |= (scsi_nosync >> shift_nosync) & 0xffff;
shift_nosync += 16;
if (!l)
return(0);
#define set_link(n, p, l, f)\
do { chain[n].ptr = (p); chain[n].len = (l); chain[n++].flg = (f); } while(0)
n = 0;
if (l < 512)
set_link(n, (vm_offset_t)p, l, SFAS_CHAIN_BUMP);
else if (
#if defined(M68040) || defined(M68060)
((mmutype == MMU_68040) && ((vm_offset_t)p >= 0xFFFC0000)) &&
#if 1
if (((scsi_nosync >> shift_nosync) & 0xff00) == 0xff00)
sc->sc_minsync = 0;
#endif
((vm_offset_t)p >= 0xFF000000)) {
int len;
while(l) {
len = ((l > sc->sc_bump_sz) ? sc->sc_bump_sz : l);
/* Really no limit, but since we want to fit into the TCR... */
sc->sc_maxxfer = 64 * 1024;
set_link(n, (vm_offset_t)p, len, SFAS_CHAIN_BUMP);
/*
* Configure interrupts.
*/
bsc->sc_isr.isr_intr = (int (*)(void *))ncr53c9x_intr;
bsc->sc_isr.isr_arg = sc;
bsc->sc_isr.isr_ipl = 2;
add_isr(&bsc->sc_isr);
p += len;
l -= len;
}
} else {
char *ptr;
vm_offset_t pa, lastpa;
int len, prelen, max_t;
/*
* Now try to attach all the sub-devices
*/
ncr53c9x_attach(sc, &bzsc_switch, &bzsc_dev);
}
ptr = p;
len = l;
/*
* Glue functions.
*/
pa = kvtop(ptr);
prelen = ((int)ptr & 0x03);
u_char
bzsc_read_reg(sc, reg)
struct ncr53c9x_softc *sc;
int reg;
{
struct bzsc_softc *bsc = (struct bzsc_softc *)sc;
if (prelen) {
prelen = 4-prelen;
set_link(n, (vm_offset_t)ptr, prelen, SFAS_CHAIN_BUMP);
ptr += prelen;
len -= prelen;
}
return bsc->sc_reg[reg * 2];
}
lastpa = 0;
while(len > 3) {
pa = kvtop(ptr);
max_t = NBPG - (pa & PGOFSET);
if (max_t > len)
max_t = len;
max_t &= ~3;
if (lastpa == pa)
sc->sc_chain[n-1].len += max_t;
else
set_link(n, pa, max_t, SFAS_CHAIN_DMA);
lastpa = pa+max_t;
ptr += max_t;
len -= max_t;
}
if (len)
set_link(n, (vm_offset_t)ptr, len, SFAS_CHAIN_BUMP);
void
bzsc_write_reg(sc, reg, val)
struct ncr53c9x_softc *sc;
int reg;
u_char val;
{
struct bzsc_softc *bsc = (struct bzsc_softc *)sc;
u_char v = val;
bsc->sc_reg[reg * 2] = v;
#ifdef DEBUG
if (bzsc_trace_enable/* && sc->sc_nexus && sc->sc_nexus->xs->flags & SCSI_POLL*/ &&
reg == NCR_CMD/* && bsc->sc_active*/) {
bzsc_trace[(bzsc_trace_ptr - 1) & 127].yy = v;
/* printf(" cmd %x", v);*/
}
#endif
}
int
bzsc_dma_isintr(sc)
struct ncr53c9x_softc *sc;
{
struct bzsc_softc *bsc = (struct bzsc_softc *)sc;
if ((bsc->sc_reg[NCR_STAT * 2] & NCRSTAT_INT) == 0)
return 0;
#ifdef DEBUG
if (/*sc->sc_nexus && sc->sc_nexus->xs->flags & SCSI_POLL &&*/ bzsc_trace_enable) {
bzsc_trace[bzsc_trace_ptr].status = bsc->sc_reg[NCR_STAT * 2];
bzsc_trace[bzsc_trace_ptr].xx = bsc->sc_reg[NCR_CMD * 2];
bzsc_trace[bzsc_trace_ptr].yy = bsc->sc_active;
bzsc_trace_ptr = (bzsc_trace_ptr + 1) & 127;
}
#endif
return 1;
}
void
bzsc_dma_reset(sc)
struct ncr53c9x_softc *sc;
{
struct bzsc_softc *bsc = (struct bzsc_softc *)sc;
bsc->sc_active = 0;
}
int
bzsc_dma_intr(sc)
struct ncr53c9x_softc *sc;
{
register struct bzsc_softc *bsc = (struct bzsc_softc *)sc;
register int cnt;
NCR_DMA(("bzsc_dma_intr: cnt %d int %x stat %x fifo %d ",
bsc->sc_dmasize, sc->sc_espintr, sc->sc_espstat,
bsc->sc_reg[NCR_FFLAG * 2] & NCRFIFO_FF));
if (bsc->sc_active == 0) {
printf("bzsc_intr--inactive DMA\n");
return -1;
}
return(n);
/* update sc_dmaaddr and sc_pdmalen */
cnt = bsc->sc_reg[NCR_TCL * 2];
cnt += bsc->sc_reg[NCR_TCM * 2] << 8;
cnt += bsc->sc_reg[NCR_TCH * 2] << 16;
if (!bsc->sc_datain) {
cnt += bsc->sc_reg[NCR_FFLAG * 2] & NCRFIFO_FF;
bsc->sc_reg[NCR_CMD * 2] = NCRCMD_FLUSH;
}
cnt = bsc->sc_dmasize - cnt; /* number of bytes transferred */
NCR_DMA(("DMA xferred %d\n", cnt));
if (bsc->sc_xfr_align) {
bcopy(bsc->sc_alignbuf, *bsc->sc_dmaaddr, cnt);
bsc->sc_xfr_align = 0;
}
*bsc->sc_dmaaddr += cnt;
*bsc->sc_pdmalen -= cnt;
bsc->sc_active = 0;
return 0;
}
/* Turn on led */
void bzsc_led_dummy(sc, mode)
struct sfas_softc *sc;
int mode;
int
bzsc_dma_setup(sc, addr, len, datain, dmasize)
struct ncr53c9x_softc *sc;
caddr_t *addr;
size_t *len;
int datain;
size_t *dmasize;
{
struct bzsc_softc *bsc = (struct bzsc_softc *)sc;
vm_offset_t pa;
u_char *ptr;
size_t xfer;
bsc->sc_dmaaddr = addr;
bsc->sc_pdmalen = len;
bsc->sc_datain = datain;
bsc->sc_dmasize = *dmasize;
/*
* DMA can be nasty for high-speed serial input, so limit the
* size of this DMA operation if the serial port is running at
* a high speed (higher than 19200 for now - should be adjusted
* based on cpu type and speed?).
* XXX - add serial speed check XXX
*/
if (ser_open_speed > 19200 && bzsc_max_dma != 0 &&
bsc->sc_dmasize > bzsc_max_dma)
bsc->sc_dmasize = bzsc_max_dma;
ptr = *addr; /* Kernel virtual address */
pa = kvtop(ptr); /* Physical address of DMA */
xfer = min(bsc->sc_dmasize, NBPG - (pa & (NBPG - 1)));
bsc->sc_xfr_align = 0;
/*
* If output and unaligned, stuff odd byte into FIFO
*/
if (datain == 0 && (int)ptr & 1) {
NCR_DMA(("bzsc_dma_setup: align byte written to fifo\n"));
pa++;
xfer--; /* XXXX CHECK THIS !!!! XXXX */
bsc->sc_reg[NCR_FIFO * 2] = *ptr++;
}
/*
* If unaligned address, read unaligned bytes into alignment buffer
*/
else if ((int)ptr & 1) {
pa = kvtop((caddr_t)&bsc->sc_alignbuf);
xfer = bsc->sc_dmasize = min(xfer, sizeof (bsc->sc_alignbuf));
NCR_DMA(("bzsc_dma_setup: align read by %d bytes\n", xfer));
bsc->sc_xfr_align = 1;
}
++bzsc_cnt_dma; /* number of DMA operations */
while (xfer < bsc->sc_dmasize) {
if ((pa + xfer) != kvtop(*addr + xfer))
break;
if ((bsc->sc_dmasize - xfer) < NBPG)
xfer = bsc->sc_dmasize;
else
xfer += NBPG;
++bzsc_cnt_dma3;
}
if (xfer != *len)
++bzsc_cnt_dma2;
bsc->sc_dmasize = xfer;
*dmasize = bsc->sc_dmasize;
bsc->sc_pa = pa;
#if defined(M68040) || defined(M68060)
if (mmutype == MMU_68040) {
if (bsc->sc_xfr_align) {
dma_cachectl(bsc->sc_alignbuf,
sizeof(bsc->sc_alignbuf));
}
else
dma_cachectl(*bsc->sc_dmaaddr, bsc->sc_dmasize);
}
#endif
pa = pa >> 1;
if (!bsc->sc_datain)
pa |= 0x80000000;
if ((u_long)bsc->sc_dmabase & 1)
bsc->sc_dmabase[0x10] = (u_int8_t)(pa >> 24);
else {
bsc->sc_dmabase[0x8000] = (u_int8_t)(pa >> 24);
bsc->sc_dmabase[0] = (u_int8_t)(pa >> 24);
}
bsc->sc_dmabase[0] = (u_int8_t)(pa >> 16);
bsc->sc_dmabase[0] = (u_int8_t)(pa >> 8);
bsc->sc_dmabase[0] = (u_int8_t)(pa);
bsc->sc_active = 1;
return 0;
}
void
bzsc_dma_go(sc)
struct ncr53c9x_softc *sc;
{
}
void
bzsc_dma_stop(sc)
struct ncr53c9x_softc *sc;
{
}
int
bzsc_dma_isactive(sc)
struct ncr53c9x_softc *sc;
{
struct bzsc_softc *bsc = (struct bzsc_softc *)sc;
return bsc->sc_active;
}
#ifdef DEBUG
void
bzsc_dump()
{
int i;
i = bzsc_trace_ptr;
printf("bzsc_trace dump: ptr %x\n", bzsc_trace_ptr);
do {
if (bzsc_trace[i].hardbits == 0) {
i = (i + 1) & 127;
continue;
}
printf("%02x%02x%02x%02x(", bzsc_trace[i].hardbits,
bzsc_trace[i].status, bzsc_trace[i].xx, bzsc_trace[i].yy);
if (bzsc_trace[i].status & NCRSTAT_INT)
printf("NCRINT/");
if (bzsc_trace[i].status & NCRSTAT_TC)
printf("NCRTC/");
switch(bzsc_trace[i].status & NCRSTAT_PHASE) {
case 0:
printf("dataout"); break;
case 1:
printf("datain"); break;
case 2:
printf("cmdout"); break;
case 3:
printf("status"); break;
case 6:
printf("msgout"); break;
case 7:
printf("msgin"); break;
default:
printf("phase%d?", bzsc_trace[i].status & NCRSTAT_PHASE);
}
printf(") ");
i = (i + 1) & 127;
} while (i != bzsc_trace_ptr);
printf("\n");
}
#endif

46
sys/arch/amiga/dev/bzscvar.h
View File

@ -1,7 +1,8 @@
/* $NetBSD: bzscvar.h,v 1.2 1996/04/21 21:10:55 veego Exp $ */
/* $NetBSD: bzscvar.h,v 1.3 1997/10/04 04:01:19 mhitch Exp $ */
/*
* Copyright (c) 1995 Daniel Widenfalk
* Copyright (c) 1997 Michael L. Hitch.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
@ -13,10 +14,10 @@
* documentation and/or other materials provided with the distribution.
* 3. All advertising materials mentioning features or use of this software
* must display the following acknowledgement:
* This product includes software developed by Daniel Widenfalk
* for the NetBSD Project.
* This product includes software developed for the NetBSD Project
* by Michael L. Hitch.
* 4. The name of the author may not be used to endorse or promote products
* derived from this software without specific prior written permission
* derived from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
@ -29,20 +30,29 @@
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
#ifndef _BZSCVAR_H_
#define _BZSCVAR_H_
#ifndef _SFASVAR_H_
#include <amiga/dev/sfasvar.h>
#endif
struct bzsc_softc {
struct ncr53c9x_softc sc_ncr53c9x; /* glue to MI code */
#ifndef _BZSCREG_H_
#include <amiga/dev/bzscreg.h>
#endif
struct isr sc_isr; /* Interrupt chain struct */
volatile u_char *sc_reg; /* the registers */
volatile u_char *sc_dmabase;
int sc_active; /* Pseudo-DMA state vars */
int sc_datain;
int sc_tc;
size_t sc_dmasize;
size_t sc_dmatrans;
char **sc_dmaaddr;
size_t *sc_pdmalen;
vm_offset_t sc_pa;
u_char sc_pad1[18]; /* XXX */
u_char sc_alignbuf[256];
u_char sc_pad2[16];
u_char sc_hardbits;
u_char sc_portbits;
u_char sc_xfr_align;
struct bzsc_softc {
struct sfas_softc sc_softc;
bzsc_regmap_t sc_regmap;
};
#endif /* _BZSCVAR_H_ */

747
sys/arch/amiga/dev/bztzsc.c
View File

@ -1,6 +1,7 @@
/* $NetBSD: bztzsc.c,v 1.4 1997/08/27 11:23:05 bouyer Exp $ */
/* $NetBSD: bztzsc.c,v 1.5 1997/10/04 04:01:21 mhitch Exp $ */
/*
* Copyright (c) 1997 Michael L. Hitch
* Copyright (c) 1996 Ignatios Souvatzis
* Copyright (c) 1982, 1990 The Regents of the University of California.
* All rights reserved.
@ -15,8 +16,8 @@
* documentation and/or other materials provided with the distribution.
* 3. All advertising materials mentioning features or use of this software
* must display the following acknowledgement:
* This product contains software written by Ignatios Souvatzis for
* the NetBSD project.
* This product contains software written by Ignatios Souvatzis and
* Michael L. Hitch for the NetBSD project.
* 4. Neither the name of the University nor the names of its contributors
* may be used to endorse or promote products derived from this software
* without specific prior written permission.
@ -35,384 +36,478 @@
*
*/
/*
* Initial amiga Blizzard 2060 driver by Ingatios Souvatzis. Conversion to
* 53c9x MI driver by Michael L. Hitch (mhitch@montana.edu).
*/
#include <sys/types.h>
#include <sys/param.h>
#include <sys/systm.h>
#include <sys/kernel.h>
#include <sys/errno.h>
#include <sys/ioctl.h>
#include <sys/device.h>
#include <sys/buf.h>
#include <sys/proc.h>
#include <sys/user.h>
#include <sys/queue.h>
#include <dev/scsipi/scsi_all.h>
#include <dev/scsipi/scsipi_all.h>
#include <dev/scsipi/scsiconf.h>
#include <vm/vm.h>
#include <vm/vm_kern.h>
#include <vm/vm_page.h>
#include <machine/pmap.h>
#include <amiga/amiga/custom.h>
#include <amiga/amiga/cc.h>
#include <amiga/amiga/device.h>
#include <dev/scsipi/scsi_message.h>
#include <machine/cpu.h>
#include <machine/param.h>
#include <dev/ic/ncr53c9xreg.h>
#include <dev/ic/ncr53c9xvar.h>
#include <amiga/amiga/isr.h>
#include <amiga/dev/sfasreg.h>
#include <amiga/dev/sfasvar.h>
#include <amiga/dev/zbusvar.h>
#include <amiga/dev/bztzscreg.h>
#include <amiga/dev/bztzscvar.h>
#include <amiga/dev/zbusvar.h>
void bztzscattach __P((struct device *, struct device *, void *));
int bztzscmatch __P((struct device *, struct cfdata *, void *));
struct scsipi_adapter bztzsc_scsiswitch = {
sfas_scsicmd,
sfas_minphys,
0, /* no lun support */
0, /* no lun support */
};
struct scsipi_device bztzsc_scsidev = {
NULL, /* use default error handler */
NULL, /* do not have a start functio */
NULL, /* have no async handler */
NULL, /* Use default done routine */
};
void bztzscattach __P((struct device *, struct device *, void *));
int bztzscmatch __P((struct device *, struct cfdata *, void *));
/* Linkup to the rest of the kernel */
struct cfattach bztzsc_ca = {
sizeof(struct bztzsc_softc), bztzscmatch, bztzscattach
};
struct cfdriver bztzsc_cd = {
NULL, "bztzsc", DV_DULL, NULL, 0
NULL, "bztzsc", DV_DULL
};
int bztzsc_intr __P((void *));
void bztzsc_set_dma_tc __P((struct sfas_softc *sc, unsigned int len));
int bztzsc_setup_dma __P((struct sfas_softc *sc, vm_offset_t ptr, int len,
int mode));
int bztzsc_build_dma_chain __P((struct sfas_softc *sc,
struct sfas_dma_chain *chain, void *p, int l));
int bztzsc_need_bump __P((struct sfas_softc *sc, vm_offset_t ptr, int len));
void bztzsc_led __P((struct sfas_softc *sc, int mode));
struct scsipi_adapter bztzsc_switch = {
ncr53c9x_scsi_cmd,
minphys, /* no max at this level; handled by DMA code */
NULL,
NULL,
};
struct scsipi_device bztzsc_dev = {
NULL, /* Use default error handler */
NULL, /* have a queue, served by this */
NULL, /* have no async handler */
NULL, /* Use default 'done' routine */
};
/*
* If we are an Phase 5 Devices Blizzard-2060 SCSI option:
* Functions and the switch for the MI code.
*/
u_char bztzsc_read_reg __P((struct ncr53c9x_softc *, int));
void bztzsc_write_reg __P((struct ncr53c9x_softc *, int, u_char));
int bztzsc_dma_isintr __P((struct ncr53c9x_softc *));
void bztzsc_dma_reset __P((struct ncr53c9x_softc *));
int bztzsc_dma_intr __P((struct ncr53c9x_softc *));
int bztzsc_dma_setup __P((struct ncr53c9x_softc *, caddr_t *,
size_t *, int, size_t *));
void bztzsc_dma_go __P((struct ncr53c9x_softc *));
void bztzsc_dma_stop __P((struct ncr53c9x_softc *));
int bztzsc_dma_isactive __P((struct ncr53c9x_softc *));
struct ncr53c9x_glue bztzsc_glue = {
bztzsc_read_reg,
bztzsc_write_reg,
bztzsc_dma_isintr,
bztzsc_dma_reset,
bztzsc_dma_intr,
bztzsc_dma_setup,
bztzsc_dma_go,
bztzsc_dma_stop,
bztzsc_dma_isactive,
0,
};
/* Maximum DMA transfer length to reduce impact on high-speed serial input */
u_long bztzsc_max_dma = 1024;
extern int ser_open_speed;
u_long bztzsc_cnt_pio = 0; /* number of PIO transfers */
u_long bztzsc_cnt_dma = 0; /* number of DMA transfers */
u_long bztzsc_cnt_dma2 = 0; /* number of DMA transfers broken up */
u_long bztzsc_cnt_dma3 = 0; /* number of pages combined */
#ifdef DEBUG
struct {
u_char hardbits;
u_char status;
u_char xx;
u_char yy;
} bztzsc_trace[128];
int bztzsc_trace_ptr = 0;
int bztzsc_trace_enable = 1;
void bztzsc_dump __P((void));
#endif
/*
* if we are a Phase5 Blizzard 2060 SCSI
*/
int
bztzscmatch(pdp, cfp, auxp)
struct device *pdp;
struct cfdata *cfp;
void *auxp;
bztzscmatch(parent, cf, aux)
struct device *parent;
struct cfdata *cf;
void *aux;
{
struct zbus_args *zap;
volatile u_int8_t *ta;
volatile u_char *regs;
zap = auxp;
if (zap->manid != 0x2140) /* Phase V ? */
zap = aux;
if (zap->manid != 0x2140 && zap->prodid != 24)
return(0);
if (zap->prodid != 24) /* is it B2060? */
return 0;
ta = (vu_char *)(((char *)zap->va) + 0x1ff00 + 0x20);
if (badbaddr((caddr_t)ta))
regs = &((volatile u_char *)zap->va)[0x1ff00];
if (badaddr((caddr_t)regs))
return(0);
*ta = 0;
*ta = 1;
DELAY(5);
if (*ta != 1)
regs[NCR_CFG1 * 4] = 0;
regs[NCR_CFG1 * 4] = NCRCFG1_PARENB | 7;
delay(5);
if (regs[NCR_CFG1 * 4] != (NCRCFG1_PARENB | 7))
return(0);
return(1);
}
u_int32_t bztzsc_flags = 0;
/*
* Attach this instance, and then all the sub-devices
*/
void
bztzscattach(pdp, dp, auxp)
struct device *pdp;
struct device *dp;
void *auxp;
bztzscattach(parent, self, aux)
struct device *parent, *self;
void *aux;
{
struct bztzsc_softc *sc;
struct bztzsc_softc *bsc = (void *)self;
struct ncr53c9x_softc *sc = &bsc->sc_ncr53c9x;
struct zbus_args *zap;
bztzsc_regmap_p rp;
vu_char *fas;
extern u_long scsi_nosync;
extern int shift_nosync;
extern int ncr53c9x_debug;
zap = auxp;
/*
* Set up the glue for MI code early; we use some of it here.
*/
sc->sc_glue = &bztzsc_glue;
fas = &((vu_char *)zap->va)[0x1ff00];
/*
* Save the regs
*/
zap = aux;
bsc->sc_reg = &((volatile u_char *)zap->va)[0x1ff00];
bsc->sc_dmabase = &bsc->sc_reg[0xf0];
sc = (struct bztzsc_softc *)dp;
rp = &sc->sc_regmap;
sc->sc_freq = 40; /* Clocked at 40Mhz */
rp->FAS216.sfas_tc_low = &fas[0x00];
rp->FAS216.sfas_tc_mid = &fas[0x04];
rp->FAS216.sfas_fifo = &fas[0x08];
rp->FAS216.sfas_command = &fas[0x0C];
rp->FAS216.sfas_dest_id = &fas[0x10];
rp->FAS216.sfas_timeout = &fas[0x14];
rp->FAS216.sfas_syncper = &fas[0x18];
rp->FAS216.sfas_syncoff = &fas[0x1C];
rp->FAS216.sfas_config1 = &fas[0x20];
rp->FAS216.sfas_clkconv = &fas[0x24];
rp->FAS216.sfas_test = &fas[0x28];
rp->FAS216.sfas_config2 = &fas[0x2C];
rp->FAS216.sfas_config3 = &fas[0x30];
rp->FAS216.sfas_tc_high = &fas[0x38];
rp->FAS216.sfas_fifo_bot = &fas[0x3C];
printf(": address %p", bsc->sc_reg);
rp->hardbits = &fas[0xe0];
rp->addrport = &fas[0xf0];
sc->sc_id = 7;
sc->sc_softc.sc_fas = (sfas_regmap_p)rp;
/*
* It is necessary to try to load the 2nd config register here,
* to find out what rev the FAS chip is, else the ncr53c9x_reset
* will not set up the defaults correctly.
*/
sc->sc_cfg1 = sc->sc_id | NCRCFG1_PARENB;
sc->sc_cfg2 = NCRCFG2_SCSI2 | NCRCFG2_FE;
sc->sc_cfg3 = 0x08 /*FCLK*/ | NCRESPCFG3_FSCSI | NCRESPCFG3_CDB;
sc->sc_rev = NCR_VARIANT_FAS216;
sc->sc_softc.sc_led = bztzsc_led;
/*
* This is the value used to start sync negotiations
* Note that the NCR register "SYNCTP" is programmed
* in "clocks per byte", and has a minimum value of 4.
* The SCSI period used in negotiation is one-fourth
* of the time (in nanoseconds) needed to transfer one byte.
* Since the chip's clock is given in MHz, we have the following
* formula: 4 * period = (1000 / freq) * 4
*/
sc->sc_minsync = 1000 / sc->sc_freq;
sc->sc_softc.sc_setup_dma = bztzsc_setup_dma;
sc->sc_softc.sc_build_dma_chain = bztzsc_build_dma_chain;
sc->sc_softc.sc_need_bump = bztzsc_need_bump;
/*
* get flags from -I argument and set cf_flags.
* NOTE: low 8 bits are to disable disconnect, and the next
* 8 bits are to disable sync.
*/
sc->sc_dev.dv_cfdata->cf_flags |= (scsi_nosync >> shift_nosync)
& 0xffff;
shift_nosync += 16;
sc->sc_softc.sc_clock_freq = 40; /* Phase5 SCSI all run at 40MHz */
sc->sc_softc.sc_timeout = 250; /* Set default timeout to 250ms */
/* Use next 16 bits of -I argument to set ncr53c9x_debug flags */
ncr53c9x_debug |= (scsi_nosync >> shift_nosync) & 0xffff;
shift_nosync += 16;
sc->sc_softc.sc_config_flags = bztzsc_flags; /* for the moment */
sc->sc_softc.sc_host_id = 7; /* Should check the jumpers */
sc->sc_softc.sc_bump_sz = NBPG; /* XXX should be the VM pagesize */
sc->sc_softc.sc_bump_pa = 0x0;
sfasinitialize((struct sfas_softc *)sc);
sc->sc_softc.sc_link.adapter_softc = sc;
sc->sc_softc.sc_link.scsipi_scsi.adapter_target = sc->sc_softc.sc_host_id;
sc->sc_softc.sc_link.adapter = &bztzsc_scsiswitch;
sc->sc_softc.sc_link.device = &bztzsc_scsidev;
sc->sc_softc.sc_link.openings = 1;
sc->sc_softc.sc_link.scsipi_scsi.max_target = 7;
sc->sc_softc.sc_link.type = BUS_SCSI;
sc->sc_softc.sc_isr.isr_intr = bztzsc_intr;
sc->sc_softc.sc_isr.isr_arg = &sc->sc_softc;
sc->sc_softc.sc_isr.isr_ipl = 2;
add_isr(&sc->sc_softc.sc_isr);
/* We don't want interrupt until we're initialized! */
printf("\n");
/* attach all scsi units on us */
config_found(dp, &sc->sc_softc.sc_link, scsiprint);
}
int
bztzsc_intr(arg)
void *arg;
{
struct sfas_softc *dev = arg;
bztzsc_regmap_p rp;
int quickints;
rp = (bztzsc_regmap_p)dev->sc_fas;
if (*rp->FAS216.sfas_status & SFAS_STAT_INTERRUPT_PENDING) {
quickints = 16;
do {
dev->sc_status = *rp->FAS216.sfas_status;
dev->sc_interrupt = *rp->FAS216.sfas_interrupt;
if (dev->sc_interrupt & SFAS_INT_RESELECTED) {
dev->sc_resel[0] = *rp->FAS216.sfas_fifo;
dev->sc_resel[1] = *rp->FAS216.sfas_fifo;
}
sfasintr(dev);
} while((*rp->FAS216.sfas_status & SFAS_STAT_INTERRUPT_PENDING)
&& --quickints);
return(1);
}
return(0);
}
/* Set DMA transfer counter */
void
bztzsc_set_dma_tc(sc, len)
struct sfas_softc *sc;
unsigned int len;
{
*sc->sc_fas->sfas_tc_low = len; len >>= 8;
*sc->sc_fas->sfas_tc_mid = len; len >>= 8;
*sc->sc_fas->sfas_tc_high = len;
}
/* Initialize DMA for transfer */
int
bztzsc_setup_dma(sc, ptr, len, mode)
struct sfas_softc *sc;
vm_offset_t ptr;
int len;
int mode;
{
int retval;
u_int32_t d;
bztzsc_regmap_p rp;
retval = 0;
switch(mode) {
case SFAS_DMA_READ:
case SFAS_DMA_WRITE:
rp = (bztzsc_regmap_p)sc->sc_fas;
d = (u_int32_t)ptr;
d >>= 1;
if (mode == SFAS_DMA_WRITE)
d |= (1L << 31);
rp->addrport[12] = (u_int8_t)d;
__asm __volatile("nop");
d >>= 8;
rp->addrport[8] = (u_int8_t)d;
__asm __volatile("nop");
d >>= 8;
rp->addrport[4] = (u_int8_t)d;
__asm __volatile("nop");
d >>= 8;
rp->addrport[0] = (u_int8_t)d;
__asm __volatile("nop");
bztzsc_set_dma_tc(sc, len);
break;
case SFAS_DMA_CLEAR:
default:
retval = (*sc->sc_fas->sfas_tc_high << 16) |
(*sc->sc_fas->sfas_tc_mid << 8) |
*sc->sc_fas->sfas_tc_low;
bztzsc_set_dma_tc(sc, 0);
break;
}
return(retval);
}
/* Check if address and len is ok for DMA transfer */
int
bztzsc_need_bump(sc, ptr, len)
struct sfas_softc *sc;
vm_offset_t ptr;
int len;
{
int p;
p = (int)ptr & 0x03;
if (p) {
p = 4-p;
if (len < 256)
p = len;
}
return(p);
}
/* Interrupt driven routines */
/* XXX some of this is voodoo might be remnants intended for the Fastlane. */
int
bztzsc_build_dma_chain(sc, chain, p, l)
struct sfas_softc *sc;
struct sfas_dma_chain *chain;
void *p;
int l;
{
vm_offset_t pa, lastpa;
char *ptr;
int len, prelen, max_t, n;
if (l == 0)
return(0);
#define set_link(n, p, l, f)\
do { chain[n].ptr = (p); chain[n].len = (l); chain[n++].flg = (f); } while(0)
n = 0;
if (l < 512)
set_link(n, (vm_offset_t)p, l, SFAS_CHAIN_BUMP);
else if ((p >= (void *)0xFF000000)
#if defined(M68040) || defined(M68060)
&& ((mmutype == MMU_68040) && (p >= (void *)0xFFFC0000))
#if 1
if (((scsi_nosync >> shift_nosync) & 0xff00) == 0xff00)
sc->sc_minsync = 0;
#endif
) {
while(l != 0) {
len = ((l > sc->sc_bump_sz) ? sc->sc_bump_sz : l);
set_link(n, (vm_offset_t)p, len, SFAS_CHAIN_BUMP);
p += len;
l -= len;
}
} else {
ptr = p;
len = l;
pa = kvtop(ptr);
prelen = ((int)ptr & 0x03);
/* Really no limit, but since we want to fit into the TCR... */
sc->sc_maxxfer = 64 * 1024;
if (prelen) {
prelen = 4-prelen;
set_link(n, (vm_offset_t)ptr, prelen, SFAS_CHAIN_BUMP);
ptr += prelen;
len -= prelen;
}
bsc->sc_reg[0xe0] = BZTZSC_PB_LED; /* Turn LED off */
lastpa = 0;
while(len > 3) {
pa = kvtop(ptr);
max_t = NBPG - (pa & PGOFSET);
if (max_t > len)
max_t = len;
/*
* Configure interrupts.
*/
bsc->sc_isr.isr_intr = (int (*)(void *))ncr53c9x_intr;
bsc->sc_isr.isr_arg = sc;
bsc->sc_isr.isr_ipl = 2;
add_isr(&bsc->sc_isr);
max_t &= ~3;
/*
* Now try to attach all the sub-devices
*/
ncr53c9x_attach(sc, &bztzsc_switch, &bztzsc_dev);
}
if (lastpa == pa)
sc->sc_chain[n-1].len += max_t;
else
set_link(n, pa, max_t, SFAS_CHAIN_DMA);
lastpa = pa+max_t;
ptr += max_t;
len -= max_t;
}
if (len)
set_link(n, (vm_offset_t)ptr, len, SFAS_CHAIN_BUMP);
/*
* Glue functions.
*/
u_char
bztzsc_read_reg(sc, reg)
struct ncr53c9x_softc *sc;
int reg;
{
struct bztzsc_softc *bsc = (struct bztzsc_softc *)sc;
return bsc->sc_reg[reg * 4];
}
void
bztzsc_write_reg(sc, reg, val)
struct ncr53c9x_softc *sc;
int reg;
u_char val;
{
struct bztzsc_softc *bsc = (struct bztzsc_softc *)sc;
u_char v = val;
bsc->sc_reg[reg * 4] = v;
#ifdef DEBUG
if (bztzsc_trace_enable/* && sc->sc_nexus && sc->sc_nexus->xs->flags & SCSI_POLL*/ &&
reg == NCR_CMD/* && bsc->sc_active*/) {
bztzsc_trace[(bztzsc_trace_ptr - 1) & 127].yy = v;
/* printf(" cmd %x", v);*/
}
#endif
}
int
bztzsc_dma_isintr(sc)
struct ncr53c9x_softc *sc;
{
struct bztzsc_softc *bsc = (struct bztzsc_softc *)sc;
if ((bsc->sc_reg[NCR_STAT * 4] & NCRSTAT_INT) == 0)
return 0;
if (sc->sc_state == NCR_CONNECTED)
bsc->sc_reg[0xe0] = 0; /* Turn LED on */
else
bsc->sc_reg[0xe0] = BZTZSC_PB_LED; /* Turn LED off */
#ifdef DEBUG
if (/*sc->sc_nexus && sc->sc_nexus->xs->flags & SCSI_POLL &&*/ bztzsc_trace_enable) {
bztzsc_trace[bztzsc_trace_ptr].status = bsc->sc_reg[NCR_STAT * 4];
bztzsc_trace[bztzsc_trace_ptr].xx = bsc->sc_reg[NCR_CMD * 4];
bztzsc_trace[bztzsc_trace_ptr].yy = bsc->sc_active;
bztzsc_trace_ptr = (bztzsc_trace_ptr + 1) & 127;
}
#endif
return 1;
}
void
bztzsc_dma_reset(sc)
struct ncr53c9x_softc *sc;
{
struct bztzsc_softc *bsc = (struct bztzsc_softc *)sc;
bsc->sc_active = 0;
}
int
bztzsc_dma_intr(sc)
struct ncr53c9x_softc *sc;
{
register struct bztzsc_softc *bsc = (struct bztzsc_softc *)sc;
register int cnt;
NCR_DMA(("bztzsc_dma_intr: cnt %d int %x stat %x fifo %d ",
bsc->sc_dmasize, sc->sc_espintr, sc->sc_espstat,
bsc->sc_reg[NCR_FFLAG * 4] & NCRFIFO_FF));
if (bsc->sc_active == 0) {
printf("bztzsc_intr--inactive DMA\n");
return -1;
}
return(n);
/* update sc_dmaaddr and sc_pdmalen */
cnt = bsc->sc_reg[NCR_TCL * 4];
cnt += bsc->sc_reg[NCR_TCM * 4] << 8;
cnt += bsc->sc_reg[NCR_TCH * 4] << 16;
if (!bsc->sc_datain) {
cnt += bsc->sc_reg[NCR_FFLAG * 4] & NCRFIFO_FF;
bsc->sc_reg[NCR_CMD * 4] = NCRCMD_FLUSH;
}
cnt = bsc->sc_dmasize - cnt; /* number of bytes transferred */
NCR_DMA(("DMA xferred %d\n", cnt));
if (bsc->sc_xfr_align) {
bcopy(bsc->sc_alignbuf, *bsc->sc_dmaaddr, cnt);
bsc->sc_xfr_align = 0;
}
*bsc->sc_dmaaddr += cnt;
*bsc->sc_pdmalen -= cnt;
bsc->sc_active = 0;
return 0;
}
/* real one for 2060 */
void
bztzsc_led(sc, mode)
struct sfas_softc *sc;
int mode;
int
bztzsc_dma_setup(sc, addr, len, datain, dmasize)
struct ncr53c9x_softc *sc;
caddr_t *addr;
size_t *len;
int datain;
size_t *dmasize;
{
bztzsc_regmap_p rp;
struct bztzsc_softc *bsc = (struct bztzsc_softc *)sc;
vm_offset_t pa;
u_char *ptr;
size_t xfer;
rp = (bztzsc_regmap_p)sc->sc_fas;
bsc->sc_dmaaddr = addr;
bsc->sc_pdmalen = len;
bsc->sc_datain = datain;
bsc->sc_dmasize = *dmasize;
/*
* DMA can be nasty for high-speed serial input, so limit the
* size of this DMA operation if the serial port is running at
* a high speed (higher than 19200 for now - should be adjusted
* based on cpu type and speed?).
* XXX - add serial speed check XXX
*/
if (ser_open_speed > 19200 && bztzsc_max_dma != 0 &&
bsc->sc_dmasize > bztzsc_max_dma)
bsc->sc_dmasize = bztzsc_max_dma;
ptr = *addr; /* Kernel virtual address */
pa = kvtop(ptr); /* Physical address of DMA */
xfer = min(bsc->sc_dmasize, NBPG - (pa & (NBPG - 1)));
bsc->sc_xfr_align = 0;
/*
* If output and unaligned, stuff odd byte into FIFO
*/
if (datain == 0 && (int)ptr & 1) {
NCR_DMA(("bztzsc_dma_setup: align byte written to fifo\n"));
pa++;
xfer--; /* XXXX CHECK THIS !!!! XXXX */
bsc->sc_reg[NCR_FIFO * 4] = *ptr++;
}
/*
* If unaligned address, read unaligned bytes into alignment buffer
*/
else if ((int)ptr & 1) {
pa = kvtop((caddr_t)&bsc->sc_alignbuf);
xfer = bsc->sc_dmasize = min(xfer, sizeof (bsc->sc_alignbuf));
NCR_DMA(("bztzsc_dma_setup: align read by %d bytes\n", xfer));
bsc->sc_xfr_align = 1;
}
++bztzsc_cnt_dma; /* number of DMA operations */
if (mode)
*rp->hardbits = 0x00; /* Led on, Int on */
else
*rp->hardbits = 0x02; /* Led off, Int on */
while (xfer < bsc->sc_dmasize) {
if ((pa + xfer) != kvtop(*addr + xfer))
break;
if ((bsc->sc_dmasize - xfer) < NBPG)
xfer = bsc->sc_dmasize;
else
xfer += NBPG;
++bztzsc_cnt_dma3;
}
if (xfer != *len)
++bztzsc_cnt_dma2;
bsc->sc_dmasize = xfer;
*dmasize = bsc->sc_dmasize;
bsc->sc_pa = pa;
#if defined(M68040) || defined(M68060)
if (mmutype == MMU_68040) {
if (bsc->sc_xfr_align) {
dma_cachectl(bsc->sc_alignbuf,
sizeof(bsc->sc_alignbuf));
}
else
dma_cachectl(*bsc->sc_dmaaddr, bsc->sc_dmasize);
}
#endif
pa >>= 1;
if (!bsc->sc_datain)
pa |= 0x80000000;
bsc->sc_dmabase[12] = (u_int8_t)(pa);
bsc->sc_dmabase[8] = (u_int8_t)(pa >> 8);
bsc->sc_dmabase[4] = (u_int8_t)(pa >> 16);
bsc->sc_dmabase[0] = (u_int8_t)(pa >> 24);
bsc->sc_active = 1;
return 0;
}
void
bztzsc_dma_go(sc)
struct ncr53c9x_softc *sc;
{
}
void
bztzsc_dma_stop(sc)
struct ncr53c9x_softc *sc;
{
}
int
bztzsc_dma_isactive(sc)
struct ncr53c9x_softc *sc;
{
struct bztzsc_softc *bsc = (struct bztzsc_softc *)sc;
return bsc->sc_active;
}
#ifdef DEBUG
void
bztzsc_dump()
{
int i;
i = bztzsc_trace_ptr;
printf("bztzsc_trace dump: ptr %x\n", bztzsc_trace_ptr);
do {
if (bztzsc_trace[i].hardbits == 0) {
i = (i + 1) & 127;
continue;
}
printf("%02x%02x%02x%02x(", bztzsc_trace[i].hardbits,
bztzsc_trace[i].status, bztzsc_trace[i].xx, bztzsc_trace[i].yy);
if (bztzsc_trace[i].status & NCRSTAT_INT)
printf("NCRINT/");
if (bztzsc_trace[i].status & NCRSTAT_TC)
printf("NCRTC/");
switch(bztzsc_trace[i].status & NCRSTAT_PHASE) {
case 0:
printf("dataout"); break;
case 1:
printf("datain"); break;
case 2:
printf("cmdout"); break;
case 3:
printf("status"); break;
case 6:
printf("msgout"); break;
case 7:
printf("msgin"); break;
default:
printf("phase%d?", bztzsc_trace[i].status & NCRSTAT_PHASE);
}
printf(") ");
i = (i + 1) & 127;
} while (i != bztzsc_trace_ptr);
printf("\n");
}
#endif

47
sys/arch/amiga/dev/bztzscvar.h
View File

@ -1,8 +1,8 @@
/* $NetBSD: bztzscvar.h,v 1.1 1996/12/16 16:17:30 is Exp $ */
/* $NetBSD: bztzscvar.h,v 1.2 1997/10/04 04:01:22 mhitch Exp $ */
/*
* Copyright (c) 1996 Ignatios Souvatzis
* Copyright (c) 1995 Daniel Widenfalk
* Copyright (c) 1997 Michael L. Hitch.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
@ -14,10 +14,10 @@
* documentation and/or other materials provided with the distribution.
* 3. All advertising materials mentioning features or use of this software
* must display the following acknowledgement:
* This product includes software developed by Daniel Widenfalk
* for the NetBSD Project.
* This product includes software developed for the NetBSD Project
* by Michael L. Hitch.
* 4. The name of the author may not be used to endorse or promote products
* derived from this software without specific prior written permission
* derived from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
@ -30,20 +30,31 @@
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
#ifndef _BZTZSCVAR_H_
#define _BZTZSCVAR_H_
#ifndef _SFASVAR_H_
#include <amiga/dev/sfasvar.h>
#endif
struct bztzsc_softc {
struct ncr53c9x_softc sc_ncr53c9x; /* glue to MI code */
#ifndef _BZTZSCREG_H_
#include <amiga/dev/bztzscreg.h>
#endif
struct isr sc_isr; /* Interrupt chain struct */
volatile u_char *sc_reg; /* the registers */
volatile u_char *sc_dmabase;
int sc_active; /* Pseudo-DMA state vars */
int sc_datain;
int sc_tc;
size_t sc_dmasize;
size_t sc_dmatrans;
char **sc_dmaaddr;
size_t *sc_pdmalen;
vm_offset_t sc_pa;
u_char sc_pad1[18]; /* XXX */
u_char sc_alignbuf[256];
u_char sc_pad2[16];
u_char sc_hardbits;
u_char sc_portbits;
u_char sc_xfr_align;
struct bztzsc_softc {
struct sfas_softc sc_softc;
bztzsc_regmap_t sc_regmap;
};
#endif /* _BZTZSCVAR_H_ */
#define BZTZSC_PB_LED 0x02 /* clear to turn LED on */

506
sys/arch/amiga/dev/cbiisc.c Normal file
View File

@ -0,0 +1,506 @@
/* $NetBSD: cbiisc.c,v 1.1 1997/10/04 04:01:26 mhitch Exp $ */
/*
* Copyright (c) 1997 Michael L. Hitch
* Copyright (c) 1982, 1990 The Regents of the University of California.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* 3. All advertising materials mentioning features or use of this software
* must display the following acknowledgement:
* This product contains software written by Michael L. Hitch for
* the NetBSD project.
* 4. Neither the name of the University nor the names of its contributors
* may be used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
* SUCH DAMAGE.
*
*/
#include <sys/types.h>
#include <sys/param.h>
#include <sys/systm.h>
#include <sys/kernel.h>
#include <sys/errno.h>
#include <sys/ioctl.h>
#include <sys/device.h>
#include <sys/buf.h>
#include <sys/proc.h>
#include <sys/user.h>
#include <sys/queue.h>
#include <dev/scsipi/scsi_all.h>
#include <dev/scsipi/scsipi_all.h>
#include <dev/scsipi/scsiconf.h>
#include <dev/scsipi/scsi_message.h>
#include <machine/cpu.h>
#include <machine/param.h>
#include <dev/ic/ncr53c9xreg.h>
#include <dev/ic/ncr53c9xvar.h>
#include <amiga/amiga/isr.h>
#include <amiga/dev/cbiiscvar.h>
#include <amiga/dev/zbusvar.h>
void cbiiscattach __P((struct device *, struct device *, void *));
int cbiiscmatch __P((struct device *, struct cfdata *, void *));
/* Linkup to the rest of the kernel */
struct cfattach cbiisc_ca = {
sizeof(struct cbiisc_softc), cbiiscmatch, cbiiscattach
};
struct cfdriver cbiisc_cd = {
NULL, "cbiisc", DV_DULL
};
struct scsipi_adapter cbiisc_switch = {
ncr53c9x_scsi_cmd,
minphys, /* no max at this level; handled by DMA code */
NULL,
NULL,
};
struct scsipi_device cbiisc_dev = {
NULL, /* Use default error handler */
NULL, /* have a queue, served by this */
NULL, /* have no async handler */
NULL, /* Use default 'done' routine */
};
/*
* Functions and the switch for the MI code.
*/
u_char cbiisc_read_reg __P((struct ncr53c9x_softc *, int));
void cbiisc_write_reg __P((struct ncr53c9x_softc *, int, u_char));
int cbiisc_dma_isintr __P((struct ncr53c9x_softc *));
void cbiisc_dma_reset __P((struct ncr53c9x_softc *));
int cbiisc_dma_intr __P((struct ncr53c9x_softc *));
int cbiisc_dma_setup __P((struct ncr53c9x_softc *, caddr_t *,
size_t *, int, size_t *));
void cbiisc_dma_go __P((struct ncr53c9x_softc *));
void cbiisc_dma_stop __P((struct ncr53c9x_softc *));
int cbiisc_dma_isactive __P((struct ncr53c9x_softc *));
struct ncr53c9x_glue cbiisc_glue = {
cbiisc_read_reg,
cbiisc_write_reg,
cbiisc_dma_isintr,
cbiisc_dma_reset,
cbiisc_dma_intr,
cbiisc_dma_setup,
cbiisc_dma_go,
cbiisc_dma_stop,
cbiisc_dma_isactive,
0,
};
/* Maximum DMA transfer length to reduce impact on high-speed serial input */
u_long cbiisc_max_dma = 1024;
extern int ser_open_speed;
u_long cbiisc_cnt_pio = 0; /* number of PIO transfers */
u_long cbiisc_cnt_dma = 0; /* number of DMA transfers */
u_long cbiisc_cnt_dma2 = 0; /* number of DMA transfers broken up */
u_long cbiisc_cnt_dma3 = 0; /* number of pages combined */
#ifdef DEBUG
struct {
u_char hardbits;
u_char status;
u_char xx;
u_char yy;
} cbiisc_trace[128];
int cbiisc_trace_ptr = 0;
int cbiisc_trace_enable = 1;
void cbiisc_dump __P((void));
#endif
/*
* if we are a Phase5 CyberSCSI II
*/
int
cbiiscmatch(parent, cf, aux)
struct device *parent;
struct cfdata *cf;
void *aux;
{
struct zbus_args *zap;
volatile u_char *regs;
zap = aux;
if (zap->manid != 0x2140 && zap->prodid != 25)
return(0);
regs = &((volatile u_char *)zap->va)[0x1ff03];
if (badaddr((caddr_t)regs))
return(0);
regs[NCR_CFG1 * 4] = 0;
regs[NCR_CFG1 * 4] = NCRCFG1_PARENB | 7;
delay(5);
if (regs[NCR_CFG1 * 4] != (NCRCFG1_PARENB | 7))
return(0);
return(1);
}
/*
* Attach this instance, and then all the sub-devices
*/
void
cbiiscattach(parent, self, aux)
struct device *parent, *self;
void *aux;
{
struct cbiisc_softc *csc = (void *)self;
struct ncr53c9x_softc *sc = &csc->sc_ncr53c9x;
struct zbus_args *zap;
extern u_long scsi_nosync;
extern int shift_nosync;
extern int ncr53c9x_debug;
/*
* Set up the glue for MI code early; we use some of it here.
*/
sc->sc_glue = &cbiisc_glue;
/*
* Save the regs
*/
zap = aux;
csc->sc_reg = &((volatile u_char *)zap->va)[0x1ff03];
csc->sc_dmabase = &csc->sc_reg[0x80];
sc->sc_freq = 40; /* Clocked at 40Mhz */
printf(": address %p", csc->sc_reg);
sc->sc_id = 7;
/*
* It is necessary to try to load the 2nd config register here,
* to find out what rev the FAS chip is, else the ncr53c9x_reset
* will not set up the defaults correctly.
*/
sc->sc_cfg1 = sc->sc_id | NCRCFG1_PARENB;
sc->sc_cfg2 = NCRCFG2_SCSI2 | NCRCFG2_FE;
sc->sc_cfg3 = 0x08 /*FCLK*/ | NCRESPCFG3_FSCSI | NCRESPCFG3_CDB;
sc->sc_rev = NCR_VARIANT_FAS216;
/*
* This is the value used to start sync negotiations
* Note that the NCR register "SYNCTP" is programmed
* in "clocks per byte", and has a minimum value of 4.
* The SCSI period used in negotiation is one-fourth
* of the time (in nanoseconds) needed to transfer one byte.
* Since the chip's clock is given in MHz, we have the following
* formula: 4 * period = (1000 / freq) * 4
*/
sc->sc_minsync = 1000 / sc->sc_freq;
/*
* get flags from -I argument and set cf_flags.
* NOTE: low 8 bits are to disable disconnect, and the next
* 8 bits are to disable sync.
*/
sc->sc_dev.dv_cfdata->cf_flags |= (scsi_nosync >> shift_nosync)
& 0xffff;
shift_nosync += 16;
/* Use next 16 bits of -I argument to set ncr53c9x_debug flags */
ncr53c9x_debug |= (scsi_nosync >> shift_nosync) & 0xffff;
shift_nosync += 16;
#if 1
if (((scsi_nosync >> shift_nosync) & 0xff00) == 0xff00)
sc->sc_minsync = 0;
#endif
/* Really no limit, but since we want to fit into the TCR... */
sc->sc_maxxfer = 64 * 1024;
/*
* Configure interrupts.
*/
csc->sc_isr.isr_intr = (int (*)(void *))ncr53c9x_intr;
csc->sc_isr.isr_arg = sc;
csc->sc_isr.isr_ipl = 2;
add_isr(&csc->sc_isr);
/*
* Now try to attach all the sub-devices
*/
ncr53c9x_attach(sc, &cbiisc_switch, &cbiisc_dev);
}
/*
* Glue functions.
*/
u_char
cbiisc_read_reg(sc, reg)
struct ncr53c9x_softc *sc;
int reg;
{
struct cbiisc_softc *csc = (struct cbiisc_softc *)sc;
return csc->sc_reg[reg * 4];
}
void
cbiisc_write_reg(sc, reg, val)
struct ncr53c9x_softc *sc;
int reg;
u_char val;
{
struct cbiisc_softc *csc = (struct cbiisc_softc *)sc;
u_char v = val;
csc->sc_reg[reg * 4] = v;
#ifdef DEBUG
if (cbiisc_trace_enable/* && sc->sc_nexus && sc->sc_nexus->xs->flags & SCSI_POLL*/ &&
reg == NCR_CMD/* && csc->sc_active*/) {
cbiisc_trace[(cbiisc_trace_ptr - 1) & 127].yy = v;
/* printf(" cmd %x", v);*/
}
#endif
}
int
cbiisc_dma_isintr(sc)
struct ncr53c9x_softc *sc;
{
struct cbiisc_softc *csc = (struct cbiisc_softc *)sc;
if ((csc->sc_reg[NCR_STAT * 4] & NCRSTAT_INT) == 0)
return 0;
if (sc->sc_state == NCR_CONNECTED)
csc->sc_reg[0x40] = CBIISC_PB_LED;
else
csc->sc_reg[0x40] = 0;
#ifdef DEBUG
if (/*sc->sc_nexus && sc->sc_nexus->xs->flags & SCSI_POLL &&*/ cbiisc_trace_enable) {
cbiisc_trace[cbiisc_trace_ptr].status = csc->sc_reg[NCR_STAT * 4];
cbiisc_trace[cbiisc_trace_ptr].xx = csc->sc_reg[NCR_CMD * 4];
cbiisc_trace[cbiisc_trace_ptr].yy = csc->sc_active;
cbiisc_trace_ptr = (cbiisc_trace_ptr + 1) & 127;
}
#endif
return 1;
}
void
cbiisc_dma_reset(sc)
struct ncr53c9x_softc *sc;
{
struct cbiisc_softc *csc = (struct cbiisc_softc *)sc;
csc->sc_active = 0;
}
int
cbiisc_dma_intr(sc)
struct ncr53c9x_softc *sc;
{
register struct cbiisc_softc *csc = (struct cbiisc_softc *)sc;
register int cnt;
NCR_DMA(("cbiisc_dma_intr: cnt %d int %x stat %x fifo %d ",
csc->sc_dmasize, sc->sc_espintr, sc->sc_espstat,
csc->sc_reg[NCR_FFLAG * 4] & NCRFIFO_FF));
if (csc->sc_active == 0) {
printf("cbiisc_intr--inactive DMA\n");
return -1;
}
/* update sc_dmaaddr and sc_pdmalen */
cnt = csc->sc_reg[NCR_TCL * 4];
cnt += csc->sc_reg[NCR_TCM * 4] << 8;
cnt += csc->sc_reg[NCR_TCH * 4] << 16;
if (!csc->sc_datain) {
cnt += csc->sc_reg[NCR_FFLAG * 4] & NCRFIFO_FF;
csc->sc_reg[NCR_CMD * 4] = NCRCMD_FLUSH;
}
cnt = csc->sc_dmasize - cnt; /* number of bytes transferred */
NCR_DMA(("DMA xferred %d\n", cnt));
if (csc->sc_xfr_align) {
bcopy(csc->sc_alignbuf, *csc->sc_dmaaddr, cnt);
csc->sc_xfr_align = 0;
}
*csc->sc_dmaaddr += cnt;
*csc->sc_pdmalen -= cnt;
csc->sc_active = 0;
return 0;
}
int
cbiisc_dma_setup(sc, addr, len, datain, dmasize)
struct ncr53c9x_softc *sc;
caddr_t *addr;
size_t *len;
int datain;
size_t *dmasize;
{
struct cbiisc_softc *csc = (struct cbiisc_softc *)sc;
vm_offset_t pa;
u_char *ptr;
size_t xfer;
csc->sc_dmaaddr = addr;
csc->sc_pdmalen = len;
csc->sc_datain = datain;
csc->sc_dmasize = *dmasize;
/*
* DMA can be nasty for high-speed serial input, so limit the
* size of this DMA operation if the serial port is running at
* a high speed (higher than 19200 for now - should be adjusted
* based on cpu type and speed?).
* XXX - add serial speed check XXX
*/
if (ser_open_speed > 19200 && cbiisc_max_dma != 0 &&
csc->sc_dmasize > cbiisc_max_dma)
csc->sc_dmasize = cbiisc_max_dma;
ptr = *addr; /* Kernel virtual address */
pa = kvtop(ptr); /* Physical address of DMA */
xfer = min(csc->sc_dmasize, NBPG - (pa & (NBPG - 1)));
csc->sc_xfr_align = 0;
/*
* If output and unaligned, stuff odd byte into FIFO
*/
if (datain == 0 && (int)ptr & 1) {
NCR_DMA(("cbiisc_dma_setup: align byte written to fifo\n"));
pa++;
xfer--; /* XXXX CHECK THIS !!!! XXXX */
csc->sc_reg[NCR_FIFO * 4] = *ptr++;
}
/*
* If unaligned address, read unaligned bytes into alignment buffer
*/
else if ((int)ptr & 1) {
pa = kvtop((caddr_t)&csc->sc_alignbuf);
xfer = csc->sc_dmasize = min(xfer, sizeof (csc->sc_alignbuf));
NCR_DMA(("cbiisc_dma_setup: align read by %d bytes\n", xfer));
csc->sc_xfr_align = 1;
}
++cbiisc_cnt_dma; /* number of DMA operations */
while (xfer < csc->sc_dmasize) {
if ((pa + xfer) != kvtop(*addr + xfer))
break;
if ((csc->sc_dmasize - xfer) < NBPG)
xfer = csc->sc_dmasize;
else
xfer += NBPG;
++cbiisc_cnt_dma3;
}
if (xfer != *len)
++cbiisc_cnt_dma2;
csc->sc_dmasize = xfer;
*dmasize = csc->sc_dmasize;
csc->sc_pa = pa;
#if defined(M68040) || defined(M68060)
if (mmutype == MMU_68040) {
if (csc->sc_xfr_align) {
dma_cachectl(csc->sc_alignbuf,
sizeof(csc->sc_alignbuf));
}
else
dma_cachectl(*csc->sc_dmaaddr, csc->sc_dmasize);
}
#endif
if (csc->sc_datain)
pa &= ~1;
else
pa |= 1;
csc->sc_dmabase[0] = (u_int8_t)(pa >> 24);
csc->sc_dmabase[4] = (u_int8_t)(pa >> 16);
csc->sc_dmabase[8] = (u_int8_t)(pa >> 8);
csc->sc_dmabase[12] = (u_int8_t)(pa);
csc->sc_active = 1;
return 0;
}
void
cbiisc_dma_go(sc)
struct ncr53c9x_softc *sc;
{
}
void
cbiisc_dma_stop(sc)
struct ncr53c9x_softc *sc;
{
}
int
cbiisc_dma_isactive(sc)
struct ncr53c9x_softc *sc;
{
struct cbiisc_softc *csc = (struct cbiisc_softc *)sc;
return csc->sc_active;
}
#ifdef DEBUG
void
cbiisc_dump()
{
int i;
i = cbiisc_trace_ptr;
printf("cbiisc_trace dump: ptr %x\n", cbiisc_trace_ptr);
do {
if (cbiisc_trace[i].hardbits == 0) {
i = (i + 1) & 127;
continue;
}
printf("%02x%02x%02x%02x(", cbiisc_trace[i].hardbits,
cbiisc_trace[i].status, cbiisc_trace[i].xx, cbiisc_trace[i].yy);
if (cbiisc_trace[i].status & NCRSTAT_INT)
printf("NCRINT/");
if (cbiisc_trace[i].status & NCRSTAT_TC)
printf("NCRTC/");
switch(cbiisc_trace[i].status & NCRSTAT_PHASE) {
case 0:
printf("dataout"); break;
case 1:
printf("datain"); break;
case 2:
printf("cmdout"); break;
case 3:
printf("status"); break;
case 6:
printf("msgout"); break;
case 7:
printf("msgin"); break;
default:
printf("phase%d?", cbiisc_trace[i].status & NCRSTAT_PHASE);
}
printf(") ");
i = (i + 1) & 127;
} while (i != cbiisc_trace_ptr);
printf("\n");
}
#endif

60
sys/arch/amiga/dev/cbiiscvar.h Normal file
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/* $NetBSD: cbiiscvar.h,v 1.1 1997/10/04 04:01:30 mhitch Exp $ */
/*
* Copyright (c) 1997 Michael L. Hitch.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* 3. All advertising materials mentioning features or use of this software
* must display the following acknowledgement:
* This product includes software developed for the NetBSD Project
* by Michael L. Hitch.
* 4. The name of the author may not be used to endorse or promote products
* derived from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
struct cbiisc_softc {
struct ncr53c9x_softc sc_ncr53c9x; /* glue to MI code */
struct isr sc_isr; /* Interrupt chain struct */
volatile u_char *sc_reg; /* the registers */
volatile u_char *sc_dmabase;
int sc_active; /* Pseudo-DMA state vars */
int sc_datain;
int sc_tc;
size_t sc_dmasize;
size_t sc_dmatrans;
char **sc_dmaaddr;
size_t *sc_pdmalen;
vm_offset_t sc_pa;
u_char sc_pad1[18]; /* XXX */
u_char sc_alignbuf[256];
u_char sc_pad2[16];
u_char sc_hardbits;
u_char sc_portbits;
u_char sc_xfr_align;
};
#define CBIISC_PB_LED 0x02

514
sys/arch/amiga/dev/cbsc.c Normal file
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@ -0,0 +1,514 @@
/* $NetBSD: cbsc.c,v 1.1 1997/10/04 04:01:24 mhitch Exp $ */
/*
* Copyright (c) 1997 Michael L. Hitch
* Copyright (c) 1982, 1990 The Regents of the University of California.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* 3. All advertising materials mentioning features or use of this software
* must display the following acknowledgement:
* This product contains software written by Michael L. Hitch for
* the NetBSD project.
* 4. Neither the name of the University nor the names of its contributors
* may be used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
* SUCH DAMAGE.
*
*/
#include <sys/types.h>
#include <sys/param.h>
#include <sys/systm.h>
#include <sys/kernel.h>
#include <sys/errno.h>
#include <sys/ioctl.h>
#include <sys/device.h>
#include <sys/buf.h>
#include <sys/proc.h>
#include <sys/user.h>
#include <sys/queue.h>
#include <dev/scsipi/scsi_all.h>
#include <dev/scsipi/scsipi_all.h>
#include <dev/scsipi/scsiconf.h>
#include <dev/scsipi/scsi_message.h>
#include <machine/cpu.h>
#include <machine/param.h>
#include <dev/ic/ncr53c9xreg.h>
#include <dev/ic/ncr53c9xvar.h>
#include <amiga/amiga/isr.h>
#include <amiga/dev/cbscvar.h>
#include <amiga/dev/zbusvar.h>
void cbscattach __P((struct device *, struct device *, void *));
int cbscmatch __P((struct device *, struct cfdata *, void *));
/* Linkup to the rest of the kernel */
struct cfattach cbsc_ca = {
sizeof(struct cbsc_softc), cbscmatch, cbscattach
};
struct cfdriver cbsc_cd = {
NULL, "cbsc", DV_DULL
};
struct scsipi_adapter cbsc_switch = {
ncr53c9x_scsi_cmd,
minphys, /* no max at this level; handled by DMA code */
NULL,
NULL,
};
struct scsipi_device cbsc_dev = {
NULL, /* Use default error handler */
NULL, /* have a queue, served by this */
NULL, /* have no async handler */
NULL, /* Use default 'done' routine */
};
/*
* Functions and the switch for the MI code.
*/
u_char cbsc_read_reg __P((struct ncr53c9x_softc *, int));
void cbsc_write_reg __P((struct ncr53c9x_softc *, int, u_char));
int cbsc_dma_isintr __P((struct ncr53c9x_softc *));
void cbsc_dma_reset __P((struct ncr53c9x_softc *));
int cbsc_dma_intr __P((struct ncr53c9x_softc *));
int cbsc_dma_setup __P((struct ncr53c9x_softc *, caddr_t *,
size_t *, int, size_t *));
void cbsc_dma_go __P((struct ncr53c9x_softc *));
void cbsc_dma_stop __P((struct ncr53c9x_softc *));
int cbsc_dma_isactive __P((struct ncr53c9x_softc *));
struct ncr53c9x_glue cbsc_glue = {
cbsc_read_reg,
cbsc_write_reg,
cbsc_dma_isintr,
cbsc_dma_reset,
cbsc_dma_intr,
cbsc_dma_setup,
cbsc_dma_go,
cbsc_dma_stop,
cbsc_dma_isactive,
0,
};
/* Maximum DMA transfer length to reduce impact on high-speed serial input */
u_long cbsc_max_dma = 1024;
extern int ser_open_speed;
u_long cbsc_cnt_pio = 0; /* number of PIO transfers */
u_long cbsc_cnt_dma = 0; /* number of DMA transfers */
u_long cbsc_cnt_dma2 = 0; /* number of DMA transfers broken up */
u_long cbsc_cnt_dma3 = 0; /* number of pages combined */
#ifdef DEBUG
struct {
u_char hardbits;
u_char status;
u_char xx;
u_char yy;
} cbsc_trace[128];
int cbsc_trace_ptr = 0;
int cbsc_trace_enable = 1;
void cbsc_dump __P((void));
#endif
/*
* if we are a Phase5 CyberSCSI [mark I?]
*/
int
cbscmatch(parent, cf, aux)
struct device *parent;
struct cfdata *cf;
void *aux;
{
struct zbus_args *zap;
volatile u_char *regs;
zap = aux;
if (zap->manid != 0x2140 && zap->prodid != 12)
return(0);
regs = &((volatile u_char *)zap->va)[0xf400];
if (badaddr((caddr_t)regs))
return(0);
regs[NCR_CFG1 * 4] = 0;
regs[NCR_CFG1 * 4] = NCRCFG1_PARENB | 7;
delay(5);
if (regs[NCR_CFG1 * 4] != (NCRCFG1_PARENB | 7))
return(0);
return(1);
}
/*
* Attach this instance, and then all the sub-devices
*/
void
cbscattach(parent, self, aux)
struct device *parent, *self;
void *aux;
{
struct cbsc_softc *csc = (void *)self;
struct ncr53c9x_softc *sc = &csc->sc_ncr53c9x;
struct zbus_args *zap;
extern u_long scsi_nosync;
extern int shift_nosync;
extern int ncr53c9x_debug;
/*
* Set up the glue for MI code early; we use some of it here.
*/
sc->sc_glue = &cbsc_glue;
/*
* Save the regs
*/
zap = aux;
csc->sc_reg = &((volatile u_char *)zap->va)[0xf400];
csc->sc_dmabase = &csc->sc_reg[0x400];
sc->sc_freq = 40; /* Clocked at 40Mhz */
printf(": address %p", csc->sc_reg);
sc->sc_id = 7;
/*
* It is necessary to try to load the 2nd config register here,
* to find out what rev the FAS chip is, else the ncr53c9x_reset
* will not set up the defaults correctly.
*/
sc->sc_cfg1 = sc->sc_id | NCRCFG1_PARENB;
sc->sc_cfg2 = NCRCFG2_SCSI2 | NCRCFG2_FE;
sc->sc_cfg3 = 0x08 /*FCLK*/ | NCRESPCFG3_FSCSI | NCRESPCFG3_CDB;
sc->sc_rev = NCR_VARIANT_FAS216;
/*
* This is the value used to start sync negotiations
* Note that the NCR register "SYNCTP" is programmed
* in "clocks per byte", and has a minimum value of 4.
* The SCSI period used in negotiation is one-fourth
* of the time (in nanoseconds) needed to transfer one byte.
* Since the chip's clock is given in MHz, we have the following
* formula: 4 * period = (1000 / freq) * 4
*/
sc->sc_minsync = 1000 / sc->sc_freq;
/*
* get flags from -I argument and set cf_flags.
* NOTE: low 8 bits are to disable disconnect, and the next
* 8 bits are to disable sync.
*/
sc->sc_dev.dv_cfdata->cf_flags |= (scsi_nosync >> shift_nosync)
& 0xffff;
shift_nosync += 16;
/* Use next 16 bits of -I argument to set ncr53c9x_debug flags */
ncr53c9x_debug |= (scsi_nosync >> shift_nosync) & 0xffff;
shift_nosync += 16;
#if 1
if (((scsi_nosync >> shift_nosync) & 0xff00) == 0xff00)
sc->sc_minsync = 0;
#endif
/* Really no limit, but since we want to fit into the TCR... */
sc->sc_maxxfer = 64 * 1024;
/*
* Configure interrupts.
*/
csc->sc_isr.isr_intr = (int (*)(void *))ncr53c9x_intr;
csc->sc_isr.isr_arg = sc;
csc->sc_isr.isr_ipl = 2;
add_isr(&csc->sc_isr);
/*
* Now try to attach all the sub-devices
*/
ncr53c9x_attach(sc, &cbsc_switch, &cbsc_dev);
}
/*
* Glue functions.
*/
u_char
cbsc_read_reg(sc, reg)
struct ncr53c9x_softc *sc;
int reg;
{
struct cbsc_softc *csc = (struct cbsc_softc *)sc;
return csc->sc_reg[reg * 4];
}
void
cbsc_write_reg(sc, reg, val)
struct ncr53c9x_softc *sc;
int reg;
u_char val;
{
struct cbsc_softc *csc = (struct cbsc_softc *)sc;
u_char v = val;
csc->sc_reg[reg * 4] = v;
#ifdef DEBUG
if (cbsc_trace_enable/* && sc->sc_nexus && sc->sc_nexus->xs->flags & SCSI_POLL*/ &&
reg == NCR_CMD/* && csc->sc_active*/) {
cbsc_trace[(cbsc_trace_ptr - 1) & 127].yy = v;
/* printf(" cmd %x", v);*/
}
#endif
}
int
cbsc_dma_isintr(sc)
struct ncr53c9x_softc *sc;
{
struct cbsc_softc *csc = (struct cbsc_softc *)sc;
if ((csc->sc_reg[NCR_STAT * 4] & NCRSTAT_INT) == 0)
return 0;
if (sc->sc_state == NCR_CONNECTED)
csc->sc_portbits |= CBSC_PB_LED;
else
csc->sc_portbits &= ~CBSC_PB_LED;
csc->sc_reg[0x802] = csc->sc_portbits;
if ((csc->sc_reg[0x802] & CBSC_HB_CREQ) == 0)
return 0;
#ifdef DEBUG
if (/*sc->sc_nexus && sc->sc_nexus->xs->flags & SCSI_POLL &&*/ cbsc_trace_enable) {
cbsc_trace[cbsc_trace_ptr].status = csc->sc_reg[NCR_STAT * 4];
cbsc_trace[cbsc_trace_ptr].xx = csc->sc_reg[NCR_CMD * 4];
cbsc_trace[cbsc_trace_ptr].yy = csc->sc_active;
cbsc_trace_ptr = (cbsc_trace_ptr + 1) & 127;
}
#endif
return 1;
}
void
cbsc_dma_reset(sc)
struct ncr53c9x_softc *sc;
{
struct cbsc_softc *csc = (struct cbsc_softc *)sc;
csc->sc_active = 0;
}
int
cbsc_dma_intr(sc)
struct ncr53c9x_softc *sc;
{
register struct cbsc_softc *csc = (struct cbsc_softc *)sc;
register int cnt;
NCR_DMA(("cbsc_dma_intr: cnt %d int %x stat %x fifo %d ",
csc->sc_dmasize, sc->sc_espintr, sc->sc_espstat,
csc->sc_reg[NCR_FFLAG * 4] & NCRFIFO_FF));
if (csc->sc_active == 0) {
printf("cbsc_intr--inactive DMA\n");
return -1;
}
/* update sc_dmaaddr and sc_pdmalen */
cnt = csc->sc_reg[NCR_TCL * 4];
cnt += csc->sc_reg[NCR_TCM * 4] << 8;
cnt += csc->sc_reg[NCR_TCH * 4] << 16;
if (!csc->sc_datain) {
cnt += csc->sc_reg[NCR_FFLAG * 4] & NCRFIFO_FF;
csc->sc_reg[NCR_CMD * 4] = NCRCMD_FLUSH;
}
cnt = csc->sc_dmasize - cnt; /* number of bytes transferred */
NCR_DMA(("DMA xferred %d\n", cnt));
if (csc->sc_xfr_align) {
bcopy(csc->sc_alignbuf, *csc->sc_dmaaddr, cnt);
csc->sc_xfr_align = 0;
}
*csc->sc_dmaaddr += cnt;
*csc->sc_pdmalen -= cnt;
csc->sc_active = 0;
return 0;
}
int
cbsc_dma_setup(sc, addr, len, datain, dmasize)
struct ncr53c9x_softc *sc;
caddr_t *addr;
size_t *len;
int datain;
size_t *dmasize;
{
struct cbsc_softc *csc = (struct cbsc_softc *)sc;
vm_offset_t pa;
u_char *ptr;
size_t xfer;
csc->sc_dmaaddr = addr;
csc->sc_pdmalen = len;
csc->sc_datain = datain;
csc->sc_dmasize = *dmasize;
/*
* DMA can be nasty for high-speed serial input, so limit the
* size of this DMA operation if the serial port is running at
* a high speed (higher than 19200 for now - should be adjusted
* based on cpu type and speed?).
* XXX - add serial speed check XXX
*/
if (ser_open_speed > 19200 && cbsc_max_dma != 0 &&
csc->sc_dmasize > cbsc_max_dma)
csc->sc_dmasize = cbsc_max_dma;
ptr = *addr; /* Kernel virtual address */
pa = kvtop(ptr); /* Physical address of DMA */
xfer = min(csc->sc_dmasize, NBPG - (pa & (NBPG - 1)));
csc->sc_xfr_align = 0;
/*
* If output and unaligned, stuff odd byte into FIFO
*/
if (datain == 0 && (int)ptr & 1) {
NCR_DMA(("cbsc_dma_setup: align byte written to fifo\n"));
pa++;
xfer--; /* XXXX CHECK THIS !!!! XXXX */
csc->sc_reg[NCR_FIFO * 4] = *ptr++;
}
/*
* If unaligned address, read unaligned bytes into alignment buffer
*/
else if ((int)ptr & 1) {
pa = kvtop((caddr_t)&csc->sc_alignbuf);
xfer = csc->sc_dmasize = min(xfer, sizeof (csc->sc_alignbuf));
NCR_DMA(("cbsc_dma_setup: align read by %d bytes\n", xfer));
csc->sc_xfr_align = 1;
}
++cbsc_cnt_dma; /* number of DMA operations */
while (xfer < csc->sc_dmasize) {
if ((pa + xfer) != kvtop(*addr + xfer))
break;
if ((csc->sc_dmasize - xfer) < NBPG)
xfer = csc->sc_dmasize;
else
xfer += NBPG;
++cbsc_cnt_dma3;
}
if (xfer != *len)
++cbsc_cnt_dma2;
csc->sc_dmasize = xfer;
*dmasize = csc->sc_dmasize;
csc->sc_pa = pa;
#if defined(M68040) || defined(M68060)
if (mmutype == MMU_68040) {
if (csc->sc_xfr_align) {
dma_cachectl(csc->sc_alignbuf,
sizeof(csc->sc_alignbuf));
}
else
dma_cachectl(*csc->sc_dmaaddr, csc->sc_dmasize);
}
#endif
if (csc->sc_datain)
pa &= ~1;
else
pa |= 1;
csc->sc_dmabase[0] = (u_int8_t)(pa >> 24);
csc->sc_dmabase[2] = (u_int8_t)(pa >> 16);
csc->sc_dmabase[4] = (u_int8_t)(pa >> 8);
csc->sc_dmabase[6] = (u_int8_t)(pa);
if (csc->sc_datain)
csc->sc_portbits &= ~CBSC_PB_WRITE;
else
csc->sc_portbits |= CBSC_PB_WRITE;
csc->sc_reg[0x802] = csc->sc_portbits;
csc->sc_active = 1;
return 0;
}
void
cbsc_dma_go(sc)
struct ncr53c9x_softc *sc;
{
}
void
cbsc_dma_stop(sc)
struct ncr53c9x_softc *sc;
{
}
int
cbsc_dma_isactive(sc)
struct ncr53c9x_softc *sc;
{
struct cbsc_softc *csc = (struct cbsc_softc *)sc;
return csc->sc_active;
}
#ifdef DEBUG
void
cbsc_dump()
{
int i;
i = cbsc_trace_ptr;
printf("cbsc_trace dump: ptr %x\n", cbsc_trace_ptr);
do {
if (cbsc_trace[i].hardbits == 0) {
i = (i + 1) & 127;
continue;
}
printf("%02x%02x%02x%02x(", cbsc_trace[i].hardbits,
cbsc_trace[i].status, cbsc_trace[i].xx, cbsc_trace[i].yy);
if (cbsc_trace[i].status & NCRSTAT_INT)
printf("NCRINT/");
if (cbsc_trace[i].status & NCRSTAT_TC)
printf("NCRTC/");
switch(cbsc_trace[i].status & NCRSTAT_PHASE) {
case 0:
printf("dataout"); break;
case 1:
printf("datain"); break;
case 2:
printf("cmdout"); break;
case 3:
printf("status"); break;
case 6:
printf("msgout"); break;
case 7:
printf("msgin"); break;
default:
printf("phase%d?", cbsc_trace[i].status & NCRSTAT_PHASE);
}
printf(") ");
i = (i + 1) & 127;
} while (i != cbsc_trace_ptr);
printf("\n");
}
#endif

64
sys/arch/amiga/dev/cbscvar.h Normal file
View File

@ -0,0 +1,64 @@
/* $NetBSD: cbscvar.h,v 1.1 1997/10/04 04:01:25 mhitch Exp $ */
/*
* Copyright (c) 1997 Michael L. Hitch.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* 3. All advertising materials mentioning features or use of this software
* must display the following acknowledgement:
* This product includes software developed for the NetBSD Project
* by Michael L. Hitch.
* 4. The name of the author may not be used to endorse or promote products
* derived from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
struct cbsc_softc {
struct ncr53c9x_softc sc_ncr53c9x; /* glue to MI code */
struct isr sc_isr; /* Interrupt chain struct */
volatile u_char *sc_reg; /* the registers */
volatile u_char *sc_dmabase;
int sc_active; /* Pseudo-DMA state vars */
int sc_datain;
int sc_tc;
size_t sc_dmasize;
size_t sc_dmatrans;
char **sc_dmaaddr;
size_t *sc_pdmalen;
vm_offset_t sc_pa;
u_char sc_pad1[18]; /* XXX */
u_char sc_alignbuf[256];
u_char sc_pad2[16];
u_char sc_hardbits;
u_char sc_portbits;
u_char sc_xfr_align;
};
#define CBSC_HB_CREQ 0x80
#define CBSC_PB_LONG 0x20
#define CBSC_PB_WRITE 0x40
#define CBSC_PB_LED 0x80

902
sys/arch/amiga/dev/flsc.c
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File diff suppressed because it is too large Load Diff

70
sys/arch/amiga/dev/flscvar.h
View File

@ -1,7 +1,8 @@
/* $NetBSD: flscvar.h,v 1.2 1996/04/21 21:11:06 veego Exp $ */
/* $NetBSD: flscvar.h,v 1.3 1997/10/04 04:01:33 mhitch Exp $ */
/*
* Copyright (c) 1995 Daniel Widenfalk
* Copyright (c) 1997 Michael L. Hitch.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
@ -13,10 +14,10 @@
* documentation and/or other materials provided with the distribution.
* 3. All advertising materials mentioning features or use of this software
* must display the following acknowledgement:
* This product includes software developed by Daniel Widenfalk
* for the NetBSD Project.
* This product includes software developed for the NetBSD Project
* by Michael L. Hitch.
* 4. The name of the author may not be used to endorse or promote products
* derived from this software without specific prior written permission
* derived from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
@ -29,26 +30,51 @@
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
#ifndef _FLSCVAR_H_
#define _FLSCVAR_H_
#ifndef _SFASVAR_H_
#include <amiga/dev/sfasvar.h>
#endif
struct flsc_softc {
struct ncr53c9x_softc sc_ncr53c9x; /* glue to MI code */
#ifndef _FLSCREG_H_
#include <amiga/dev/flscvar.h>
#endif
struct isr sc_isr; /* Interrupt chain struct */
volatile u_char *sc_reg; /* the registers */
volatile u_char *sc_dmabase;
int sc_active; /* Pseudo-DMA state vars */
int sc_piomode;
int sc_datain;
int sc_tc;
size_t sc_dmasize;
size_t sc_dmatrans;
char **sc_dmaaddr;
size_t *sc_pdmalen;
vm_offset_t sc_pa;
u_char sc_pad1[18]; /* XXX */
u_char sc_alignbuf[256];
u_char sc_pad2[16];
u_char sc_hardbits;
u_char sc_portbits;
u_char sc_csr;
u_char sc_xfr_align;
struct flsc_specific {
u_char hardbits;
u_char portbits;
};
struct flsc_softc {
struct sfas_softc sc_softc;
flsc_regmap_t sc_regmap;
struct flsc_specific sc_specific;
};
#define FLSC_HB_DISABLED 0x01
#define FLSC_HB_BUSID6 0x02
#define FLSC_HB_SEAGATE 0x04
#define FLSC_HB_SLOW 0x08
#define FLSC_HB_SYNCHRON 0x10
#define FLSC_HB_CREQ 0x20
#define FLSC_HB_IACT 0x40
#define FLSC_HB_MINT 0x80
#endif /* _FLSCVAR_H_ */
#define FLSC_PB_ESI 0x01
#define FLSC_PB_EDI 0x02
#define FLSC_PB_ENABLE_DMA 0x04
#define FLSC_PB_DISABLE_DMA 0x00 /* Symmetric reasons */
#define FLSC_PB_DMA_WRITE 0x08
#define FLSC_PB_DMA_READ 0x00 /* Symmetric reasons */
#define FLSC_PB_LED 0x10
#define FLSC_PB_INT_BITS (FLSC_PB_ESI | FLSC_PB_EDI)
#define FLSC_PB_DMA_BITS (FLSC_PB_ENABLE_DMA | FLSC_PB_DMA_WRITE)