Pull up following revision(s) (requested by tsutsui in ticket #1590):
sys/arch/next68k/include/vmparam.h: revision 1.29 sys/arch/next68k/next68k/machdep.c: revision 1.118 sys/arch/next68k/include/param.h: revision 1.13 sys/arch/next68k/next68k/pmap_bootstrap.c: revision 1.45 sys/arch/next68k/next68k/locore.s: revision 1.70 sys/arch/next68k/next68k/locore.s: revision 1.71 Use explicit CPU strings and remove hp300 derived stuff. Remove #ifdef'ed out hp300 specific stuff. Remove leftover "last kernel PT page" settings derived from hp300. Whilehere, also remove VM definitions for obsolete COMPAT_HPUX stuff. All hp300 machines has RAMs at a region from the highest address i.e. 0xFFFFFFFF to smaller address (as HP claims "it's the MSB first"), so kernels have to prepare PA==KVA mappings as the "last PT page" to guarantee the running kernel works both before and after the MMU is turned on. For such a special mapping, we have to set up necessary segment table and page table during early startup, in pmap_bootstrap() invoked from locore.s. On the other hand, NeXT machines have RAMs at a region from 0x40000000 to below (i.e. to larger address) so we still need a PA==KVA mapping. However currently NetBSD/next68k just uses the transparent translation registers to achieve the PA==KVA mapping, so unlike hp300 we don't have to prepare special segment table and page table for it. Note many other m68k ports (like luna68k, news68k, x68k etc.) have RAMs at a region from 0x00000000 so usually we can assume PA==KVA and don't have to bother to prepare such speicial mappings. No user visible changes (except now freed wasted pages for the tables). Tested on my NeXTstation slab.
This commit is contained in:
martin
parent
6a8fda3af3
commit
6676131d63
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@ -1,4 +1,4 @@
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/* $NetBSD: param.h,v 1.12 2012/02/10 17:35:48 para Exp $ */
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/* $NetBSD: param.h,v 1.12.52.1 2023/02/12 11:47:10 martin Exp $ */
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/*
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* Copyright (c) 1988 University of Utah.
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@ -50,7 +50,7 @@
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#define PGSHIFT 12 /* LOG2(NBPG) */
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#define KERNBASE 0x00000000 /* start of kernel virtual */
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#define UPAGES 3 /* pages of u-area */
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#define UPAGES 2 /* pages of u-area */
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#include <m68k/param.h>
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@ -1,4 +1,4 @@
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/* $NetBSD: vmparam.h,v 1.26.2.1 2020/02/10 18:46:39 martin Exp $ */
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/* $NetBSD: vmparam.h,v 1.26.2.2 2023/02/12 11:47:10 martin Exp $ */
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/*
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* This file was taken from from mvme68k/include/vmparam.h and
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@ -59,16 +59,8 @@
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/*
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* USRSTACK is the top (end) of the user stack.
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*
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* NOTE: the ONLY reason that HIGHPAGES is 0x100 instead of UPAGES (3)
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* is for HPUX compatibility. Why?? Because HPUX's debuggers
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* have the user's stack hard-wired at FFF00000 for post-mortems,
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* and we must be compatible...
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*/
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#define USRSTACK (-HIGHPAGES*PAGE_SIZE) /* Start of user stack */
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#define BTOPUSRSTACK (0x100000-HIGHPAGES) /* btop(USRSTACK) */
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#define P1PAGES 0x100000
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#define HIGHPAGES (0x100000/PAGE_SIZE)
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#define USRSTACK VM_MAXUSER_ADDRESS /* Start of user stack */
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/*
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* Virtual memory related constants, all in bytes
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@ -106,7 +98,7 @@
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#define VM_MAXUSER_ADDRESS ((vaddr_t)0xFFF00000)
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#define VM_MAX_ADDRESS ((vaddr_t)0xFFF00000)
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#define VM_MIN_KERNEL_ADDRESS ((vaddr_t)0)
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#define VM_MAX_KERNEL_ADDRESS ((vaddr_t)(0-PAGE_SIZE*NPTEPG*2))
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#define VM_MAX_KERNEL_ADDRESS ((vaddr_t)(0-PAGE_SIZE*NPTEPG))
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/* virtual sizes (bytes) for various kernel submaps */
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#define VM_PHYS_SIZE (USRIOSIZE*PAGE_SIZE)
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@ -131,4 +123,4 @@ struct pmap_physseg {
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struct pv_header *pvheader; /* pv table for this seg */
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};
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#endif /* _MVME68K_VMPARAM_H_ */
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#endif /* _NEXT68K_VMPARAM_H_ */
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@ -1,4 +1,4 @@
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/* $NetBSD: locore.s,v 1.66 2018/12/19 13:57:49 maxv Exp $ */
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/* $NetBSD: locore.s,v 1.66.4.1 2023/02/12 11:47:10 martin Exp $ */
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/*
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* Copyright (c) 1998 Darrin B. Jewell
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@ -229,10 +229,6 @@ Lnot68030:
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movl #CPU_68040,%a0@ | and a 68040 CPU
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RELOC(fputype, %a0)
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movl #FPU_68040,%a0@ | ...and FPU
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#if defined(ENABLE_HP_CODE)
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RELOC(ectype, %a0)
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movl #EC_NONE,%a0@ | and no cache (for now XXX)
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#endif
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RELOC(machineid, %a0)
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movl #40,%a0@ | @@@ useless
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jra Lstart1
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@ -324,20 +320,16 @@ Lstart3:
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* Prepare to enable MMU.
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* Since the kernel is not mapped logical == physical we must insure
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* that when the MMU is turned on, all prefetched addresses (including
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* the PC) are valid. In order guarantee that, we use the last physical
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* page (which is conveniently mapped == VA) and load it up with enough
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* code to defeat the prefetch, then we execute the jump back to here.
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*
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* Is this all really necessary, or am I paranoid??
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* the PC) are valid. In order guarantee that, we use the transparent
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* translation registers (which provide PA == VA mappings) and just
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* turns on the MMU, then jump from the VA == PA address (at 0x40XXXXXX)
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* to the actual kernel virtual address (at 0x00XXXXXX) code via a far
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* jump instruction so that we can defeat the prefetch.
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*/
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RELOC(Sysseg_pa, %a0) | system segment table addr
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movl %a0@,%d1 | read value (a PA)
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RELOC(mmutype, %a0)
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#if defined(ENABLE_HP_CODE)
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tstl %a0@ | HP MMU?
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jeq Lhpmmu2 | yes, skip
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#endif
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cmpl #MMU_68040,%a0@ | 68040?
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jne Lmotommu1 | no, skip
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.long 0x4e7b1807 | movc %d1,%srp
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@ -349,31 +341,7 @@ Lmotommu1:
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pmove %a0@,%srp | load the supervisor root pointer
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movl #0x80000002,%a0@ | reinit upper half for CRP loads
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#if defined(ENABLE_HP_CODE)
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jra Lstploaddone | done
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Lhpmmu2:
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moveq #PGSHIFT,%d2
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lsrl %d2,%d1 | convert to page frame
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movl %d1,INTIOBASE+MMUBASE+MMUSSTP | load in sysseg table register
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#endif
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Lstploaddone:
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#if defined(ENABLE_MAXADDR_TRAMPOLINE)
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lea MAXADDR,%a2 | PA of last RAM page
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ASRELOC(Lhighcode, %a1) | addr of high code
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ASRELOC(Lehighcode, %a3) | end addr
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Lcodecopy:
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movw %a1@+,%a2@+ | copy a word
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cmpl %a3,%a1 | done yet?
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jcs Lcodecopy | no, keep going
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jmp MAXADDR | go for it!
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/*
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* BEGIN MMU TRAMPOLINE. This section of code is not
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* executed in-place. It's copied to the last page
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* of RAM (mapped va == pa) and executed there.
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*/
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Lhighcode:
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#endif /* ENABLE_MAXADDR_TRAMPOLINE */
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/*
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* Set up the vector table, and race to get the MMU
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@ -387,21 +355,12 @@ Lhighcode:
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movc %d0,%vbr
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RELOC(mmutype, %a0)
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#if defined(ENABLE_HP_CODE)
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tstl %a0@ | HP MMU?
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jeq Lhpmmu3 | yes, skip
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#endif
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cmpl #MMU_68040,%a0@ | 68040?
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jne Lmotommu2 | no, skip
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#if defined(ENABLE_HP_CODE)
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movw #0,INTIOBASE+MMUBASE+MMUCMD+2
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movw #MMU_IEN+MMU_CEN+MMU_FPE,INTIOBASE+MMUBASE+MMUCMD+2
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| enable FPU and caches
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#endif
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| This is a hack to get PA=KVA when turning on MMU
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| it will only work on 68040's. We should fix something
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| to boot 68030's later.
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| This is a hack to get PA=KVA when turning on MMU as mentioned above.
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| Currintly this will only work on 68040's. We should also provide
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| %tt0 and %tt1 settings to boot 68030's later.
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movel #0x0200c040,%d0 | intio devices are at 0x02000000
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.long 0x4e7b0004 | movc %d0,%itt0
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.long 0x4e7b0006 | movc %d0,%dtt0
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@ -425,28 +384,11 @@ Lturnoffttr:
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.long 0x4e7b0007 | movc %d0,%dtt1
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jmp Lenab1
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Lmotommu2:
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#if defined(ENABLE_HP_CODE)
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movl #MMU_IEN+MMU_FPE,INTIOBASE+MMUBASE+MMUCMD
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| enable 68881 and i-cache
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#endif
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pflusha
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RELOC(prototc, %a2)
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movl #0x82c0aa00,%a2@ | value to load TC with
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pmove %a2@,%tc | load it
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jmp Lenab1:l | force absolute (not pc-relative) jmp
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#if defined(ENABLE_HP_CODE)
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Lhpmmu3:
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movl #0,INTIOBASE+MMUBASE+MMUCMD | clear external cache
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movl #MMU_ENAB,INTIOBASE+MMUBASE+MMUCMD | turn on MMU
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jmp Lenab1:l | jmp to mapped code
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#endif
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#if defined(ENABLE_MAXADDR_TRAMPOLINE)
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Lehighcode:
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/*
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* END MMU TRAMPOLINE. Address register %a5 is now free.
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*/
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#endif
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/*
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* Should be running mapped from this point on
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@ -478,7 +420,7 @@ Lenab2:
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movc %d0,%cacr | clear cache(s)
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jra Lenab3
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Ltbia040:
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.word 0xf518
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.word 0xf518 | pflusha
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Lenab3:
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jbsr _C_LABEL(next68k_init)
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@ -944,24 +886,6 @@ Lsldone:
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rts
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#endif
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#if defined(ENABLE_HP_CODE)
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ENTRY(ecacheon)
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tstl _C_LABEL(ectype)
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jeq Lnocache7
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MMUADDR(%a0)
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orl #MMU_CEN,%a0@(MMUCMD)
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Lnocache7:
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rts
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ENTRY(ecacheoff)
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tstl _C_LABEL(ectype)
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jeq Lnocache8
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MMUADDR(%a0)
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andl #~MMU_CEN,%a0@(MMUCMD)
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Lnocache8:
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rts
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#endif
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/*
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* Load a new user segment table pointer.
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*/
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@ -1140,11 +1064,6 @@ GLOBAL(mmutype)
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GLOBAL(cputype)
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.long 0xdeadbeef | default to 68020 CPU
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#if defined(ENABLE_HP_CODE)
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GLOBAL(ectype)
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.long EC_NONE | external cache type, default to none
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#endif
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GLOBAL(fputype)
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.long 0xdeadbeef | default to 68882 FPU
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@ -1178,20 +1097,6 @@ ASLOCAL(save_vbr) | VBR from ROM
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GLOBAL(monbootflag)
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.long 0
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#if defined(ENABLE_HP_CODE)
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GLOBAL(extiobase)
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.long 0 | KVA of base of external IO space
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GLOBAL(CLKbase)
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.long 0 | KVA of base of clock registers
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GLOBAL(MMUbase)
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.long 0 | KVA of base of HP MMU registers
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GLOBAL(pagezero)
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.long 0 | PA of first page of kernel text
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#endif
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#ifdef USELEDS
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ASLOCAL(heartbeat)
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.long 0 | clock ticks since last pulse of heartbeat
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@ -1,4 +1,4 @@
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/* $NetBSD: machdep.c,v 1.112.4.1 2023/02/01 18:56:44 martin Exp $ */
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/* $NetBSD: machdep.c,v 1.112.4.2 2023/02/12 11:47:10 martin Exp $ */
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/*
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* Copyright (c) 1998 Darrin B. Jewell
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@ -40,7 +40,7 @@
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*/
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#include <sys/cdefs.h>
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__KERNEL_RCSID(0, "$NetBSD: machdep.c,v 1.112.4.1 2023/02/01 18:56:44 martin Exp $");
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__KERNEL_RCSID(0, "$NetBSD: machdep.c,v 1.112.4.2 2023/02/12 11:47:10 martin Exp $");
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#include "opt_ddb.h"
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#include "opt_kgdb.h"
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@ -321,7 +321,7 @@ cpu_startup(void)
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void
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identifycpu(void)
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{
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const char *mc, *mmu_str, *fpu_str, *cache_str;
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const char *cpu_str, *mmu_str, *fpu_str, *cache_str;
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extern int turbo;
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/*
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@ -329,21 +329,23 @@ identifycpu(void)
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*/
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switch (cputype) {
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case CPU_68040:
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mc = "40";
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cpu_str = "MC68040";
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cpuspeed = turbo ? 33 : 25;
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delay_divisor = 759 / cpuspeed;
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break;
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case CPU_68030:
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mc = "30";
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cpu_str = "MC68030";
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cpuspeed = 25;
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delay_divisor = 2048 / cpuspeed;
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break;
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#if 0
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case CPU_68020:
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mc = "20";
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cpu_str = "MC68020";
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break;
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#endif
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default:
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printf("\nunknown cputype %d\n", cputype);
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goto lose;
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panic("startup");
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}
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/*
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@ -354,14 +356,13 @@ identifycpu(void)
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case MMU_68030:
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mmu_str = "+MMU";
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break;
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#if 0
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case MMU_68851:
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mmu_str = ", MC68851 MMU";
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break;
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case MMU_HP:
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mmu_str = ", HP MMU";
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break;
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#endif
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default:
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printf("MC680%s: unknown MMU type %d\n", mc, mmutype);
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printf("%s: unknown MMU type %d\n", cpu_str, mmutype);
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panic("startup");
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}
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@ -376,7 +377,7 @@ identifycpu(void)
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fpu_str = ", MC68882 FPU";
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break;
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case FPU_68881:
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fpu_str = ", MHz MC68881 FPU";
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fpu_str = ", MC68881 FPU";
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break;
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default:
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fpu_str = ", unknown FPU";
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@ -387,30 +388,11 @@ identifycpu(void)
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*/
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if (cputype == CPU_68040)
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cache_str = ", 4k on-chip physical I/D caches";
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else {
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#if defined(ENABLE_HP_CODE)
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switch (ectype) {
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case EC_VIRT:
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cache_str = ", virtual-address cache";
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break;
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case EC_PHYS:
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cache_str = ", physical-address cache";
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break;
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default:
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else
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cache_str = "";
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break;
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}
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#else
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cache_str = "";
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#endif
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}
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cpu_setmodel("NeXT/MC680%s CPU%s%s%s", mc, mmu_str, fpu_str, cache_str);
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cpu_setmodel("NeXT/%s CPU%s%s%s", cpu_str, mmu_str, fpu_str, cache_str);
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printf("%s\n", cpu_getmodel());
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return;
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lose:
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panic("startup");
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}
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/*
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|
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@ -1,4 +1,4 @@
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/* $NetBSD: pmap_bootstrap.c,v 1.44 2016/12/23 10:48:12 maya Exp $ */
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/* $NetBSD: pmap_bootstrap.c,v 1.44.20.1 2023/02/12 11:47:10 martin Exp $ */
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/*
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* This file was taken from mvme68k/mvme68k/pmap_bootstrap.c
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@ -45,7 +45,7 @@
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*/
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#include <sys/cdefs.h>
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__KERNEL_RCSID(0, "$NetBSD: pmap_bootstrap.c,v 1.44 2016/12/23 10:48:12 maya Exp $");
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__KERNEL_RCSID(0, "$NetBSD: pmap_bootstrap.c,v 1.44.20.1 2023/02/12 11:47:10 martin Exp $");
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#include "opt_m68k_arch.h"
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@ -100,7 +100,6 @@ void
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pmap_bootstrap(paddr_t nextpa, paddr_t firstpa)
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{
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paddr_t lwp0upa, kstpa, kptmpa, kptpa;
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paddr_t lkptpa;
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u_int nptpages, kstsize;
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st_entry_t protoste, *ste, *este;
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pt_entry_t protopte, *pte, *epte;
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|
|
@ -156,8 +155,6 @@ pmap_bootstrap(paddr_t nextpa, paddr_t firstpa)
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*
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* kptmpa kernel PT map 1 page
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*
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* lkptpa last kernel PT page 1 page
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*
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* kptpa statically allocated
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* kernel PT pages Sysptsize+ pages
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*
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@ -180,8 +177,6 @@ pmap_bootstrap(paddr_t nextpa, paddr_t firstpa)
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nextpa += kstsize * PAGE_SIZE;
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kptmpa = nextpa;
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nextpa += PAGE_SIZE;
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lkptpa = nextpa;
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nextpa += PAGE_SIZE;
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kptpa = nextpa;
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nptpages = RELOC(Sysptsize, int) + howmany(RELOC(physmem, int), NPTEPG) +
|
||||
(IIOMAPSIZE + MONOMAPSIZE + COLORMAPSIZE + NPTEPG - 1) / NPTEPG;
|
||||
|
|
@ -207,18 +202,8 @@ pmap_bootstrap(paddr_t nextpa, paddr_t firstpa)
|
|||
* each mapping 256kb. Note that there may be additional "segment
|
||||
* table" pages depending on how large MAXKL2SIZE is.
|
||||
*
|
||||
* Portions of the last two segment of KVA space (0xFF800000 -
|
||||
* 0xFFFFFFFF) are mapped for a couple of purposes.
|
||||
* The first segment (0xFF800000 - 0xFFBFFFFF) is mapped
|
||||
* for the kernel page tables.
|
||||
*
|
||||
* XXX: It looks this was copied from hp300 and not sure if
|
||||
* XXX: last physical page mapping is really needed on this port.
|
||||
* The very last page (0xFFFFF000) in the second segment is mapped
|
||||
* to the last physical page of RAM to give us a region in which
|
||||
* PA == VA. We use the first part of this page for enabling
|
||||
* and disabling mapping. The last part of this page also contains
|
||||
* info left by the boot ROM.
|
||||
* Portions of the last segment of KVA space (0xFFC00000 -
|
||||
* 0xFFFFFFFF) are mapped for the kernel page tables.
|
||||
*
|
||||
* XXX cramming two levels of mapping into the single "segment"
|
||||
* table on the 68040 is intended as a temporary hack to get things
|
||||
|
|
@ -276,23 +261,17 @@ pmap_bootstrap(paddr_t nextpa, paddr_t firstpa)
|
|||
*ste = protoste;
|
||||
/*
|
||||
* Now initialize the final portion of that block of
|
||||
* descriptors to map Sysmap and the "last PT page".
|
||||
* descriptors to map Sysmap.
|
||||
*/
|
||||
i = SG4_LEV1SIZE + (nl1desc * SG4_LEV2SIZE);
|
||||
ste = (st_entry_t *)kstpa;
|
||||
ste = &ste[i + SG4_LEV2SIZE - (NPTEPG / SG4_LEV3SIZE) * 2];
|
||||
ste = &ste[i + SG4_LEV2SIZE - (NPTEPG / SG4_LEV3SIZE)];
|
||||
este = &ste[NPTEPG / SG4_LEV3SIZE];
|
||||
protoste = kptmpa | SG_U | SG_RW | SG_V;
|
||||
while (ste < este) {
|
||||
*ste++ = protoste;
|
||||
protoste += (SG4_LEV3SIZE * sizeof(st_entry_t));
|
||||
}
|
||||
este = &ste[NPTEPG / SG4_LEV3SIZE];
|
||||
protoste = lkptpa | SG_U | SG_RW | SG_V;
|
||||
while (ste < este) {
|
||||
*ste++ = protoste;
|
||||
protoste += (SG4_LEV3SIZE * sizeof(st_entry_t));
|
||||
}
|
||||
/*
|
||||
* Calculate the free level 2 descriptor mask
|
||||
* noting that we have used:
|
||||
|
|
@ -305,7 +284,7 @@ pmap_bootstrap(paddr_t nextpa, paddr_t firstpa)
|
|||
/* mark entries for map page tables */
|
||||
for (i = 1; i <= nl1desc; i++)
|
||||
stfree &= ~l2tobm(i);
|
||||
/* mark an entry for kptmpa and lkptpa */
|
||||
/* mark an entry for kptmpa */
|
||||
stfree &= ~l2tobm(i);
|
||||
/* mark entries not available */
|
||||
for (i = MAXKL2SIZE; i < sizeof(stfree) * NBBY; i++)
|
||||
|
|
@ -330,14 +309,11 @@ pmap_bootstrap(paddr_t nextpa, paddr_t firstpa)
|
|||
*pte++ = PG_NV;
|
||||
}
|
||||
/*
|
||||
* Initialize the last ones to point to Sysptmap and the page
|
||||
* table page allocated earlier.
|
||||
* Initialize the last one to point to Sysptmap.
|
||||
*/
|
||||
pte = (pt_entry_t *)kptmpa;
|
||||
pte = &pte[SYSMAP_VA >> SEGSHIFT];
|
||||
*pte = kptmpa | PG_RW | PG_CI | PG_V;
|
||||
pte++; /* XXX should use [MAXADDR >> SEGSHIFT] */
|
||||
*pte = lkptpa | PG_RW | PG_CI | PG_U | PG_V;
|
||||
} else
|
||||
#endif /* M68040 || M68060 */
|
||||
{
|
||||
|
|
@ -368,8 +344,7 @@ pmap_bootstrap(paddr_t nextpa, paddr_t firstpa)
|
|||
while (pte < epte)
|
||||
*pte++ = PG_NV;
|
||||
/*
|
||||
* Initialize the last ones to point to Sysptmap and the page
|
||||
* table page allocated earlier.
|
||||
* Initialize the last one to point to Sysptmap.
|
||||
*/
|
||||
ste = (st_entry_t *)kstpa;
|
||||
ste = &ste[SYSMAP_VA >> SEGSHIFT];
|
||||
|
|
@ -377,28 +352,8 @@ pmap_bootstrap(paddr_t nextpa, paddr_t firstpa)
|
|||
pte = &pte[SYSMAP_VA >> SEGSHIFT];
|
||||
*ste = kptmpa | SG_RW | SG_V;
|
||||
*pte = kptmpa | PG_RW | PG_CI | PG_V;
|
||||
ste++; /* XXX should use [MAXADDR >> SEGSHIFT] */
|
||||
pte++; /* XXX should use [MAXADDR >> SEGSHIFT] */
|
||||
*ste = lkptpa | SG_RW | SG_V;
|
||||
*pte = lkptpa | PG_RW | PG_CI | PG_V;
|
||||
}
|
||||
|
||||
/*
|
||||
* Invalidate all but the final entry in the last kernel PT page.
|
||||
* The final entry maps the last page of physical memory to
|
||||
* prepare a page that is PA == VA to turn on the MMU.
|
||||
*
|
||||
* XXX: This looks copied from hp300 where PA != VA, but
|
||||
* XXX: it's suspicious if this is also required on this port.
|
||||
*/
|
||||
pte = (pt_entry_t *)lkptpa;
|
||||
epte = &pte[NPTEPG - 1];
|
||||
while (pte < epte)
|
||||
*pte++ = PG_NV;
|
||||
#ifdef MAXADDR
|
||||
/* tmp double-map for CPUs with physmem at the end of memory */
|
||||
*pte = MAXADDR | PG_RW | PG_CI | PG_U | PG_V;
|
||||
#endif
|
||||
/*
|
||||
* Initialize kernel page table.
|
||||
* Start by invalidating the `nptpages' that we have allocated.
|
||||
|
|
|
|||
Loading…
Reference in New Issue