Ensure that data accessed by the ADW driver in memory is in
little-endian byte-order. This should work out to be a no-op for LE systems, and allows BE systems to use the board. Tested on PPC, reviewed by Dante. NOTE: The board/microcode does have a BIG_ENDIAN mode of operation, but it's not well-documented. That might be interesting to investigate at some point in the future, though.
This commit is contained in:
briggs
parent
a0f0f74348
commit
665cc59e75
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@ -1,4 +1,4 @@
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/* $NetBSD: adw.c,v 1.34 2001/07/31 23:12:01 dante Exp $ */
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/* $NetBSD: adw.c,v 1.35 2001/08/29 17:25:03 briggs Exp $ */
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/*
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* Generic driver for the Advanced Systems Inc. SCSI controllers
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@ -278,8 +278,8 @@ adw_init_ccb(ADW_SOFTC *sc, ADW_CCB *ccb)
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* put in the phystokv hash table
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* Never gets taken out.
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*/
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ccb->hashkey = sc->sc_dmamap_control->dm_segs[0].ds_addr +
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ADW_CCB_OFF(ccb);
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ccb->hashkey = htole32(sc->sc_dmamap_control->dm_segs[0].ds_addr +
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ADW_CCB_OFF(ccb));
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hashnum = CCB_HASH(ccb->hashkey);
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ccb->nexthash = sc->sc_ccbhash[hashnum];
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sc->sc_ccbhash[hashnum] = ccb;
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@ -663,8 +663,8 @@ adw_build_req(ADW_SOFTC *sc, ADW_CCB *ccb)
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scsiqp->target_lun = periph->periph_lun;
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scsiqp->vsense_addr = &ccb->scsi_sense;
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scsiqp->sense_addr = sc->sc_dmamap_control->dm_segs[0].ds_addr +
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ADW_CCB_OFF(ccb) + offsetof(struct adw_ccb, scsi_sense);
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scsiqp->sense_addr = htole32(sc->sc_dmamap_control->dm_segs[0].ds_addr +
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ADW_CCB_OFF(ccb) + offsetof(struct adw_ccb, scsi_sense));
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scsiqp->sense_len = sizeof(struct scsipi_sense_data);
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/*
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@ -720,9 +720,9 @@ out_bad:
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/*
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* Build scatter-gather list.
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*/
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scsiqp->data_cnt = xs->datalen;
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scsiqp->data_cnt = htole32(xs->datalen);
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scsiqp->vdata_addr = xs->data;
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scsiqp->data_addr = ccb->dmamap_xfer->dm_segs[0].ds_addr;
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scsiqp->data_addr = htole32(ccb->dmamap_xfer->dm_segs[0].ds_addr);
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memset(ccb->sg_block, 0,
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sizeof(ADW_SG_BLOCK) * ADW_NUM_SG_BLOCK);
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adw_build_sglist(ccb, scsiqp, ccb->sg_block);
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@ -753,9 +753,9 @@ adw_build_sglist(ADW_CCB *ccb, ADW_SCSI_REQ_Q *scsiqp, ADW_SG_BLOCK *sg_block)
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sg_block_next_addr = (u_long) sg_block; /* allow math operation */
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sg_block_physical_addr = ccb->hashkey +
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sg_block_physical_addr = le32toh(ccb->hashkey) +
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offsetof(struct adw_ccb, sg_block[0]);
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scsiqp->sg_real_addr = sg_block_physical_addr;
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scsiqp->sg_real_addr = htole32(sg_block_physical_addr);
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/*
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* If there are more than NO_OF_SG_PER_BLOCK dma segments (hw sg-list)
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@ -764,8 +764,8 @@ adw_build_sglist(ADW_CCB *ccb, ADW_SCSI_REQ_Q *scsiqp, ADW_SG_BLOCK *sg_block)
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do {
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for (i = 0; i < NO_OF_SG_PER_BLOCK; i++) {
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sg_block->sg_list[i].sg_addr = sg_list->ds_addr;
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sg_block->sg_list[i].sg_count = sg_list->ds_len;
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sg_block->sg_list[i].sg_addr = htole32(sg_list->ds_addr);
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sg_block->sg_list[i].sg_count = htole32(sg_list->ds_len);
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if (--sg_elem_cnt == 0) {
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/* last entry, get out */
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@ -779,7 +779,7 @@ adw_build_sglist(ADW_CCB *ccb, ADW_SCSI_REQ_Q *scsiqp, ADW_SG_BLOCK *sg_block)
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sg_block_physical_addr += sizeof(ADW_SG_BLOCK);
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sg_block->sg_cnt = NO_OF_SG_PER_BLOCK;
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sg_block->sg_ptr = sg_block_physical_addr;
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sg_block->sg_ptr = htole32(sg_block_physical_addr);
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sg_block = (ADW_SG_BLOCK *) sg_block_next_addr; /* virt. addr */
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} while (1);
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}
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@ -1079,7 +1079,7 @@ adw_isr_callback(ADW_SOFTC *sc, ADW_SCSI_REQ_Q *scsiq)
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adw_print_info(sc, scsiq->target_id);
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}
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xs->error = XS_NOERROR;
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xs->resid = scsiq->data_cnt;
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xs->resid = le32toh(scsiq->data_cnt);
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sc->sc_freeze_dev[scsiq->target_id] = 0;
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break;
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@ -1,4 +1,4 @@
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/* $NetBSD: adwlib.c,v 1.21 2001/04/30 03:43:09 lukem Exp $ */
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/* $NetBSD: adwlib.c,v 1.22 2001/08/29 17:25:03 briggs Exp $ */
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/*
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* Low level routines for the Advanced Systems Inc. SCSI controllers chips
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@ -853,12 +853,12 @@ ADW_SOFTC *sc;
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/*
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* The first command issued will be placed in the stopper carrier.
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*/
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sc->icq_sp->next_ba = ASC_CQ_STOPPER;
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sc->icq_sp->next_ba = htole32(ASC_CQ_STOPPER);
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/*
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* Set RISC ICQ physical address start value.
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*/
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ADW_WRITE_DWORD_LRAM(iot, ioh, ADW_MC_ICQ, sc->icq_sp->carr_ba);
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ADW_WRITE_DWORD_LRAM(iot, ioh, ADW_MC_ICQ, le32toh(sc->icq_sp->carr_ba));
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/*
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* Initialize the COMMA register to the same value otherwise
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@ -866,7 +866,7 @@ ADW_SOFTC *sc;
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*/
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if(sc->chip_type == ADW_CHIP_ASC38C1600) {
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ADW_WRITE_DWORD_REGISTER(iot, ioh, IOPDW_COMMA,
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sc->icq_sp->carr_ba);
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le32toh(sc->icq_sp->carr_ba));
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}
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/*
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@ -885,12 +885,12 @@ ADW_SOFTC *sc;
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* Note: Set 'next_ba' to ASC_CQ_STOPPER. When the request is
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* completed the RISC will set the ASC_RQ_DONE bit.
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*/
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sc->irq_sp->next_ba = ASC_CQ_STOPPER;
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sc->irq_sp->next_ba = htole32(ASC_CQ_STOPPER);
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/*
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* Set RISC IRQ physical address start value.
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*/
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ADW_WRITE_DWORD_LRAM(iot, ioh, ADW_MC_IRQ, sc->irq_sp->carr_ba);
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ADW_WRITE_DWORD_LRAM(iot, ioh, ADW_MC_IRQ, le32toh(sc->irq_sp->carr_ba));
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sc->carr_pending_cnt = 0;
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ADW_WRITE_BYTE_REGISTER(iot, ioh, IOPB_INTR_ENABLES,
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@ -1757,14 +1757,14 @@ ADW_SCSI_REQ_Q *scsiq;
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* to the stopper value. The current stopper will be changed
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* below to point to the new stopper.
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*/
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new_carrp->next_ba = ASC_CQ_STOPPER;
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new_carrp->next_ba = htole32(ASC_CQ_STOPPER);
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req_size = sizeof(ADW_SCSI_REQ_Q);
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req_paddr = sc->sc_dmamap_control->dm_segs[0].ds_addr +
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ADW_CCB_OFF(ccb) + offsetof(struct adw_ccb, scsiq);
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/* Save physical address of ADW_SCSI_REQ_Q and Carrier. */
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scsiq->scsiq_rptr = req_paddr;
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scsiq->scsiq_rptr = htole32(req_paddr);
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/*
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* Every ADV_CARR_T.carr_ba is byte swapped to little-endian
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@ -1778,7 +1778,7 @@ ADW_SCSI_REQ_Q *scsiq;
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* the microcode. The newly allocated stopper will become the new
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* stopper.
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*/
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sc->icq_sp->areq_ba = req_paddr;
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sc->icq_sp->areq_ba = htole32(req_paddr);
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/*
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* Set the 'next_ba' pointer for the old stopper to be the
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@ -1821,7 +1821,7 @@ ADW_SCSI_REQ_Q *scsiq;
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* address of the new carrier stopper to the COMMA register.
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*/
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ADW_WRITE_DWORD_REGISTER(iot, ioh, IOPDW_COMMA,
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new_carrp->carr_ba);
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le32toh(new_carrp->carr_ba));
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}
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/*
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@ -2054,7 +2054,7 @@ ADW_SOFTC *sc;
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/*
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* Check if the IRQ stopper carrier contains a completed request.
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*/
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while (((irq_next_pa = sc->irq_sp->next_ba) & ASC_RQ_DONE) != 0)
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while (((le32toh(irq_next_pa = sc->irq_sp->next_ba)) & ASC_RQ_DONE) != 0)
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{
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#if ADW_DEBUG
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printf("irq 0x%x, 0x%x, 0x%x, 0x%x\n",
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@ -2082,7 +2082,7 @@ ADW_SOFTC *sc;
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* DMAed to host memory by the firmware. Set all status fields
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* to indicate good status.
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*/
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if ((irq_next_pa & ASC_RQ_GOOD) != 0) {
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if ((le32toh(irq_next_pa) & ASC_RQ_GOOD) != 0) {
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scsiq->done_status = QD_NO_ERROR;
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scsiq->host_status = scsiq->scsi_status = 0;
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scsiq->data_cnt = 0L;
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@ -1,4 +1,4 @@
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/* $NetBSD: adwmcode.h,v 1.6 2001/01/18 20:28:17 jdolecek Exp $ */
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/* $NetBSD: adwmcode.h,v 1.7 2001/08/29 17:25:04 briggs Exp $ */
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/*
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* Generic driver definitions and exported functions for the Advanced
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@ -77,21 +77,21 @@ typedef struct adw_carrier ADW_CARRIER;
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* Mask used to eliminate low 4 bits of carrier 'next_ba' field.
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*/
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#define ASC_NEXT_BA_MASK 0xFFFFFFF0
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#define ASC_GET_CARRP(carrp) ((carrp) & ASC_NEXT_BA_MASK)
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#define ASC_GET_CARRP(carrp) htole32((le32toh(carrp)) & ASC_NEXT_BA_MASK)
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/*
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* Bus Address of a Carrier.
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* ba = base_ba + v_address - base_va
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*/
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#define ADW_CARRIER_BADDR(dmamap, carriers, x) ((dmamap)->dm_segs[0].ds_addr +\
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(((u_long)x) - ((u_long)(carriers))))
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#define ADW_CARRIER_BADDR(dmamap, carriers, x) \
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htole32((dmamap)->dm_segs[0].ds_addr + ((u_long)x - (u_long)(carriers)))
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/*
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* Virtual Address of a Carrier.
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* va = base_va + bus_address - base_ba
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*/
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#define ADW_CARRIER_VADDR(sc, x) ((ADW_CARRIER *) \
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(((u_int8_t *)(sc)->sc_control->carriers) + \
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((u_long)x) - \
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le32toh((u_long)x) - \
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(sc)->sc_dmamap_carrier->dm_segs[0].ds_addr))
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/******************************************************************************/
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