Disable 1ofN distribution of SPIs by default. This is a workaround for an
issue in the USB stack -- signaling transfer complete on multiple PEs can cause transfer completions to be processed out of order.
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@ -1,4 +1,4 @@
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/* $NetBSD: gicv3.c,v 1.43 2021/02/23 10:03:04 jmcneill Exp $ */
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/* $NetBSD: gicv3.c,v 1.44 2021/03/28 11:13:24 jmcneill Exp $ */
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/*-
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* Copyright (c) 2018 Jared McNeill <jmcneill@invisible.ca>
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@ -31,7 +31,7 @@
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#define _INTR_PRIVATE
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#include <sys/cdefs.h>
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__KERNEL_RCSID(0, "$NetBSD: gicv3.c,v 1.43 2021/02/23 10:03:04 jmcneill Exp $");
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__KERNEL_RCSID(0, "$NetBSD: gicv3.c,v 1.44 2021/03/28 11:13:24 jmcneill Exp $");
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#include <sys/param.h>
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#include <sys/kernel.h>
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@ -65,6 +65,13 @@ __KERNEL_RCSID(0, "$NetBSD: gicv3.c,v 1.43 2021/02/23 10:03:04 jmcneill Exp $");
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#define GIC_PRIO_SHIFT_NS 4
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#define GIC_PRIO_SHIFT_S 3
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/*
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* Set to true if you want to use 1 of N interrupt distribution for SPIs
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* when available. Disabled by default because it causes issues with the
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* USB stack.
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*/
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bool gicv3_use_1ofn = false;
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static struct gicv3_softc *gicv3_softc;
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static inline uint32_t
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@ -195,7 +202,7 @@ gicv3_establish_irq(struct pic_softc *pic, struct intrsource *is)
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* If 1 of N SPI routing is supported, route MP-safe interrupts to all
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* participating PEs. Otherwise, just route to the primary PE.
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*/
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if (is->is_mpsafe && GIC_SUPPORTS_1OFN(sc)) {
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if (is->is_mpsafe && GIC_SUPPORTS_1OFN(sc) && gicv3_use_1ofn) {
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irouter = GICD_IROUTER_Interrupt_Routing_mode;
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} else {
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irouter = sc->sc_irouter[0];
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@ -498,7 +505,7 @@ gicv3_set_affinity(struct pic_softc *pic, size_t irq, const kcpuset_t *affinity)
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const int set = kcpuset_countset(affinity);
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if (set == 1) {
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irouter = sc->sc_irouter[kcpuset_ffs(affinity) - 1];
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} else if (set == ncpu && GIC_SUPPORTS_1OFN(sc)) {
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} else if (set == ncpu && GIC_SUPPORTS_1OFN(sc) && gicv3_use_1ofn) {
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irouter = GICD_IROUTER_Interrupt_Routing_mode;
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} else {
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return EINVAL;
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