Add a skeleton driver for the random latches on the Archimedes, which are
shared between the printer port and floppy drive. Useful facilities will be added when I know what I need.
This commit is contained in:
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@ -1,4 +1,4 @@
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# $NetBSD: FOURMEG,v 1.13 2001/04/10 21:33:00 bjh21 Exp $
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# $NetBSD: FOURMEG,v 1.14 2001/04/22 00:26:35 bjh21 Exp $
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# FOURMEG arm26 configuration -- something small
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# FOURMEG arm26 configuration -- something small
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@ -130,6 +130,7 @@ arcwsmouse0 at arckbd0
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wsmouse0 at arcwsmouse0
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wsmouse0 at arcwsmouse0
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ioeb0 at ioc0 bank 5 # I/O Extension Block (A5000)
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ioeb0 at ioc0 bank 5 # I/O Extension Block (A5000)
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latches0 at ioc0 bank 5 # Printer/FDC control latches (Arc)
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podulebus0 at ioc0 bank 4 # Expansion card bus
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podulebus0 at ioc0 bank 4 # Expansion card bus
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unixbp0 at ioc0 bank 6 # Unix Backplane (interrupt routing)
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unixbp0 at ioc0 bank 6 # Unix Backplane (interrupt routing)
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@ -1,4 +1,4 @@
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# $NetBSD: GENERIC,v 1.19 2001/04/10 21:33:00 bjh21 Exp $
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# $NetBSD: GENERIC,v 1.20 2001/04/22 00:26:35 bjh21 Exp $
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# GENERIC arm26 configuration -- everything I've implemented so far
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# GENERIC arm26 configuration -- everything I've implemented so far
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@ -127,6 +127,7 @@ arcwsmouse0 at arckbd0
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wsmouse0 at arcwsmouse0
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wsmouse0 at arcwsmouse0
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ioeb0 at ioc0 bank 5 # I/O Extension Block (A5000)
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ioeb0 at ioc0 bank 5 # I/O Extension Block (A5000)
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latches0 at ioc0 bank 5 # Printer/FDC control latches (Arc)
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podulebus0 at ioc0 bank 4 # Expansion card bus
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podulebus0 at ioc0 bank 4 # Expansion card bus
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unixbp0 at ioc0 bank 6 # Unix Backplane (interrupt routing)
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unixbp0 at ioc0 bank 6 # Unix Backplane (interrupt routing)
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@ -1,4 +1,4 @@
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# $NetBSD: files.arm26,v 1.27 2001/04/10 21:33:01 bjh21 Exp $
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# $NetBSD: files.arm26,v 1.28 2001/04/22 00:26:35 bjh21 Exp $
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# Copyright (c) 1997, 1998, 2000 Ben Harris
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# Copyright (c) 1997, 1998, 2000 Ben Harris
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# All rights reserved.
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# All rights reserved.
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@ -84,9 +84,10 @@ file arch/arm26/ioc/ioeb.c ioeb needs-flag
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device joy
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device joy
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attach joy at ioeb
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attach joy at ioeb
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# Latches (random internal use) (usually at bank 5 offset 0x18 and 0x40)
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# Latches (random internal use) (usually at ioc0 bank 5)
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device latch
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device latches
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attach latch at ioc
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attach latches at ioc
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file arch/arm26/ioc/latches.c latches
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# On-board keyboard interface
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# On-board keyboard interface
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device arckbd { }
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device arckbd { }
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99
sys/arch/arm26/ioc/latches.c
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99
sys/arch/arm26/ioc/latches.c
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/* $NetBSD: latches.c,v 1.1 2001/04/22 00:26:36 bjh21 Exp $ */
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/*-
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* Copyright (c) 2001 Ben Harris
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* 3. The name of the author may not be used to endorse or promote products
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* derived from this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
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* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
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* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
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* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
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* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
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* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
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* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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#include <sys/param.h>
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__KERNEL_RCSID(0, "$NetBSD: latches.c,v 1.1 2001/04/22 00:26:36 bjh21 Exp $");
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#include <sys/device.h>
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#include <sys/systm.h>
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#include <machine/bus.h>
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#include <arch/arm26/iobus/iocvar.h>
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#include <arch/arm26/ioc/latchreg.h>
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#include <arch/arm26/ioc/latchvar.h>
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#include <arch/arm26/ioc/ioebvar.h>
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#include "ioeb.h"
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struct latches_softc {
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struct device sc_dev;
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bus_space_tag_t sc_iot;
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bus_space_handle_t sc_ioh;
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u_int8_t sc_latcha;
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u_int8_t sc_latchb;
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};
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static int latches_match(struct device *, struct cfdata *, void *);
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static void latches_attach(struct device *, struct device *, void *);
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struct cfattach latches_ca = {
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sizeof(struct latches_softc), latches_match, latches_attach
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};
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struct device *the_latches;
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static int
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latches_match(struct device *parent, struct cfdata *cf, void *aux)
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{
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/*
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* Latches are write-only, so we can't probe for them.
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* Happily, the set of machines they exist on is precisely the
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* set that doesn't have IOEBs, so...
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*/
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#if NIOEB > 0
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if (the_ioeb != NULL)
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return 0;
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#endif
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return 1;
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}
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static void
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latches_attach(struct device *parent, struct device *self, void *aux)
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{
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struct latches_softc *sc = (void *)self;
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struct ioc_attach_args *ioc = aux;
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bus_space_tag_t iot;
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bus_space_handle_t ioh;
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if (the_latches == NULL)
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the_latches = self;
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iot = sc->sc_iot = ioc->ioc_fast_t;
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ioh = sc->sc_ioh = ioc->ioc_fast_h;
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sc->sc_latcha =
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LATCHA_NSEL0 | LATCHA_NSEL1 | LATCHA_NSEL2 | LATCHA_NSEL3 |
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LATCHA_NSIDE1 | LATCHA_NMOTORON | LATCHA_NINUSE;
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sc->sc_latchb = LATCHB_NFDCR | LATCHB_NPSTB;
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bus_space_write_1(sc->sc_iot, sc->sc_ioh, LATCH_A, sc->sc_latcha);
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bus_space_write_1(sc->sc_iot, sc->sc_ioh, LATCH_B, sc->sc_latchb);
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printf("\n");
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}
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@ -1,6 +1,6 @@
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/* $NetBSD: latchreg.h,v 1.1 2000/05/09 21:56:02 bjh21 Exp $ */
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/* $NetBSD: latchreg.h,v 1.2 2001/04/22 00:26:36 bjh21 Exp $ */
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/*-
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/*-
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* Copyright (c) 1997, 1998 Ben Harris
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* Copyright (c) 1997, 1998, 2001 Ben Harris
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* All rights reserved.
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* All rights reserved.
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*
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*
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* Redistribution and use in source and binary forms, with or without
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* Redistribution and use in source and binary forms, with or without
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@ -30,31 +30,32 @@
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* latchreg.h - Archimedes internal latches
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* latchreg.h - Archimedes internal latches
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*/
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*/
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/* Under NetBSD, Latch A is latch0 and Latch B is latch1. */
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#ifndef _LATCHREG_H
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#ifndef _LATCHREG_H
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#define _LATCHREG_H
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#define _LATCHREG_H
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/* Latch A controls some of the floppy disc system */
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/* Register offsets for latches (bus_space units) */
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#define LATCH0_DRIVESEL0 0x01 /* Floppy drive 0 select */
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#define LATCH_A 0x10
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#define LATCH0_DRIVESEL1 0x02 /* Floppy drive 1 select */
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#define LATCH_B 0x06
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#define LATCH0_DRIVESEL2 0x04 /* Floppy drive 2 select */
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#define LATCH0_DRIVESEL3 0x08 /* Floppy drive 3 select */
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#define LATCH0_SIDESEL 0x10 /* Floppy side select, inverted. */
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#define LATCH0_SIDE0 0x10
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#define LATCH0_SIDE1 0x00 /* Just to be friendly... */
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#define LATCH0_MOTORONOFF 0x20 /* Motor on/off */
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#define LATCH0_INUSE 0x40 /* 'In Use' */
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/* Latch B does all sorts of random stuff */
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/* Latch A controls some of the floppy disc system (all active-low). */
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#define LATCHA_NSEL0 0x01 /* Floppy drive 0 select */
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#define LATCHA_NSEL1 0x02 /* Floppy drive 1 select */
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#define LATCHA_NSEL2 0x04 /* Floppy drive 2 select */
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#define LATCHA_NSEL3 0x08 /* Floppy drive 3 select */
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#define LATCHA_NSIDE1 0x10 /* Floppy side select. */
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#define LATCHA_NMOTORON 0x20 /* Motor on/off */
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#define LATCHA_NINUSE 0x40 /* 'In Use' */
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/* Bit 7 not used */
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#define LATCH1_DENSITY 0x02 /* Floppy disc density setting */
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/* Latch B does all sorts of random stuff (mostly active-low). */
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#define LATCH1_DOUBLEDENSITY 0x00 /* Double density */
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/* Bit 0 reserved */
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#define LATCH1_SINGLEDENSITY 0x02 /* Single density */
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#define LATCHB_NDDEN 0x02 /* Floppy disc density setting */
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#define LATCH1_NOTFDCRESET 0x08 /* Floppy controller reset (inverted) */
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/* Bit 2 reserved */
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#define LATCH1_LPTSTROBE 0x10 /* Printer strobe line */
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#define LATCHB_NFDCR 0x08 /* Floppy controller reset */
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#define LATCH1_AUX1 0x20 /* Spare (VIDC Enhancer?) */
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#define LATCHB_NPSTB 0x10 /* Printer strobe line */
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#define LATCH1_AUX2 0x40 /* Spare */
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#define LATCHB_AUX1 0x20 /* Spare (VIDC Enhancer?) */
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#define LATCHB_AUX2 0x40 /* Spare */
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/* Bit 7 not used */
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#endif /* !_LATCHREG_H */
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#endif /* !_LATCHREG_H */
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33
sys/arch/arm26/ioc/latchvar.h
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33
sys/arch/arm26/ioc/latchvar.h
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/* $NetBSD: latchvar.h,v 1.1 2001/04/22 00:26:36 bjh21 Exp $ */
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/*-
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* Copyright (c) 2001 Ben Harris
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* 3. The name of the author may not be used to endorse or promote products
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* derived from this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
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* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
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* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
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* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
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* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
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* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
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* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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#ifndef _LATCHVAR_H_
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#define _LATCHVAR_H_
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extern struct device *the_latches;
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#endif
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