Add an assembler version of strcmp, based on example code from the ARM
ARM. As an example of the performance difference that this provides a Dhrystone score on my Shark goes from 213k to 261k.
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rearnsha
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c1058540a3
commit
6576c49b48
@ -1,8 +1,8 @@
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# $NetBSD: Makefile.inc,v 1.2 2001/11/11 22:05:18 chris Exp $
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# $NetBSD: Makefile.inc,v 1.3 2002/11/16 18:28:52 rearnsha Exp $
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SRCS+= memcpy.S _memcpy.S bcopy.S memmove.S memset.S bzero.S ffs.S
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SRCS+= memcpy.S _memcpy.S bcopy.S memmove.S memset.S bzero.S ffs.S strcmp.S
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SRCS+= bcmp.c index.c memchr.c memcmp.c \
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rindex.c strcat.c strcmp.c strcpy.c strcspn.c strlen.c \
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rindex.c strcat.c strcpy.c strcspn.c strlen.c \
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strncat.c strncmp.c strncpy.c strpbrk.c strsep.c \
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strspn.c strstr.c swab.c
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45
lib/libc/arch/arm/string/strcmp.S
Normal file
45
lib/libc/arch/arm/string/strcmp.S
Normal file
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/* $NetBSD: strcmp.S,v 1.1 2002/11/16 18:28:52 rearnsha Exp $ */
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/*
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* Copyright (c) 2002 ARM Ltd
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* 3. The name of the company may not be used to endorse or promote
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* products derived from this software without specific prior written
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* permission.
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*
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* THIS SOFTWARE IS PROVIDED BY ARM LTD ``AS IS'' AND ANY EXPRESS OR IMPLIED
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* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
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* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
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* IN NO EVENT SHALL ARM LTD BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED
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* TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
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* PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
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* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
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* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
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* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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#include <machine/asm.h>
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ENTRY(strcmp)
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.Loop:
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ldrb r2, [r0], #1
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ldrb r3, [r1], #1
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cmp r2, #1
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cmpcs r2, r3
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beq .Loop
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sub r0, r2, r3
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#ifdef __APCS_26__
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movs pc, lr
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#else
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mov pc, lr
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#endif
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@ -1,10 +1,10 @@
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# $NetBSD: Makefile.inc,v 1.4 2002/08/17 01:22:33 chris Exp $
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# $NetBSD: Makefile.inc,v 1.5 2002/11/16 18:27:40 rearnsha Exp $
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SRCS+= __assert.c __main.c bswap64.c byte_swap_2.S byte_swap_4.S \
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ffs.S imax.c imin.c lmax.c lmin.c max.c min.c random.c scanc.c \
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skpc.c strcat.c strcmp.c strcasecmp.c \
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skpc.c strcat.c strcasecmp.c \
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strcpy.c strlen.c strncasecmp.c strncmp.c \
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strncpy.c strtoul.c ulmax.c ulmin.c
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SRCS+= divsi3.S
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SRCS+= memchr.c memcmp.c memcpy.S memset.S memmove.S
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SRCS+= memchr.c memcmp.c memcpy.S memset.S memmove.S strcmp.S
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45
sys/lib/libkern/arch/arm/strcmp.S
Normal file
45
sys/lib/libkern/arch/arm/strcmp.S
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@ -0,0 +1,45 @@
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/* $NetBSD: strcmp.S,v 1.1 2002/11/16 18:27:40 rearnsha Exp $ */
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/*
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* Copyright (c) 2002 ARM Ltd
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* 3. The name of the company may not be used to endorse or promote
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* products derived from this software without specific prior written
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* permission.
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*
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* THIS SOFTWARE IS PROVIDED BY ARM LTD ``AS IS'' AND ANY EXPRESS OR IMPLIED
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* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
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* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
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* IN NO EVENT SHALL ARM LTD BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED
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* TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
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* PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
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* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
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* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
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* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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#include <machine/asm.h>
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ENTRY(strcmp)
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.Loop:
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ldrb r2, [r0], #1
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ldrb r3, [r1], #1
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cmp r2, #1
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cmpcs r2, r3
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beq .Loop
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sub r0, r2, r3
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#ifdef __APCS_26__
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movs pc, lr
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#else
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mov pc, lr
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#endif
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