Allow multiple interrupt handler on same interrupt event.
Clear interrupt mask for specified interrupt in apbus_intr_establish(). Add dma stuff; define apbus_dmamap_sync() to flush DMA write cache by accessing the corresponding I/O port.
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onoe
parent
de22372491
commit
655ba83924
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@ -1,4 +1,4 @@
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/* $NetBSD: apbus.c,v 1.2 1999/12/23 06:52:30 tsubai Exp $ */
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/* $NetBSD: apbus.c,v 1.3 2000/10/12 03:11:38 onoe Exp $ */
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/*-
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* Copyright (C) 1999 SHIMIZU Ryo. All rights reserved.
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@ -28,10 +28,13 @@
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#include <sys/param.h>
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#include <sys/systm.h>
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#include <sys/malloc.h>
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#include <sys/device.h>
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#include <machine/adrsmap.h>
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#include <machine/autoconf.h>
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#define _NEWSMIPS_BUS_DMA_PRIVATE
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#include <machine/bus.h>
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#include <newsmips/apbus/apbusvar.h>
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static int apbusmatch __P((struct device *, struct cfdata *, void *));
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@ -52,19 +55,18 @@ struct cfattach ap_ca = {
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#define APBUS_DEVNAMELEN 16
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struct ap_intrhand {
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struct ap_intrhand *ai_next;
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int ai_mask;
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int ai_priority;
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void (*ai_func) __P((void*)); /* function */
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int (*ai_func) __P((void*)); /* function */
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void *ai_aux; /* softc */
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char ai_name[APBUS_DEVNAMELEN];
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int ai_ctlno;
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};
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#define NLEVEL 2
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#define NBIT 16
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#define LEVELxBIT(l,b) (((l)*NBIT)+(b))
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static struct ap_intrhand apintr[NLEVEL*NBIT];
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static struct ap_intrhand *apintr[NLEVEL];
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static int
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apbusmatch(parent, cfdata, aux)
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@ -181,16 +183,13 @@ apbus_intr_call(level, stat)
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int level;
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int stat;
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{
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int i;
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int nintr = 0;
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struct ap_intrhand *aip = &apintr[LEVELxBIT(level,0)];
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struct ap_intrhand *ai;
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for(i = 0; i < NBIT; i++) {
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if (aip->ai_mask & stat) {
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(*aip->ai_func)(aip->ai_aux);
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nintr++;
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for (ai = apintr[level]; ai != NULL; ai = ai->ai_next) {
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if (ai->ai_mask & stat) {
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nintr += (*ai->ai_func)(ai->ai_aux);
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}
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aip++;
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}
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return nintr;
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}
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@ -203,32 +202,88 @@ apbus_intr_establish(level, mask, priority, func, aux, name, ctlno)
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int level;
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int mask;
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int priority;
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void (*func) __P((void *));
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int (*func) __P((void *));
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void *aux;
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char *name;
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int ctlno;
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{
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int i;
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int nbit = -1;
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struct ap_intrhand *aip;
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struct ap_intrhand *ai, **aip;
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volatile unsigned int *inten0 = (volatile unsigned int *)NEWS5000_INTEN0;
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volatile unsigned int *inten1 = (volatile unsigned int *)NEWS5000_INTEN1;
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for (i = 0; i < NBIT; i++) {
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if (mask & (1 << i)) {
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nbit = i;
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ai = malloc(sizeof(*ai), M_DEVBUF, M_NOWAIT);
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if (ai == NULL)
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panic("apbus_intr_establish: can't malloc handler info");
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ai->ai_mask = mask;
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ai->ai_priority = priority;
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ai->ai_func = func;
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ai->ai_aux = aux;
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strncpy(ai->ai_name, name, APBUS_DEVNAMELEN-1);
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ai->ai_ctlno = ctlno;
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for (aip = &apintr[level]; *aip != NULL; aip = &(*aip)->ai_next) {
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if ((*aip)->ai_priority < priority)
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break;
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}
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}
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ai->ai_next = *aip;
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*aip = ai;
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switch (level) {
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case 0:
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*inten0 |= mask;
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break;
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case 1:
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*inten1 |= mask;
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break;
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}
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if (nbit == -1)
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panic("apbus_intr_establish");
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aip = &apintr[LEVELxBIT(level,nbit)];
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aip->ai_mask = 1 << nbit;
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aip->ai_priority = priority;
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aip->ai_func = func;
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aip->ai_aux = aux;
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strncpy(aip->ai_name, name, APBUS_DEVNAMELEN-1);
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aip->ai_ctlno = ctlno;
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return (void *)aip;
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return (void *)ai;
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}
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void
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apbus_dmamap_sync(t, map, offset, len, ops)
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bus_dma_tag_t t;
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bus_dmamap_t map;
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bus_addr_t offset;
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bus_size_t len;
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int ops;
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{
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/*
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* Flush DMA cache by issueing IO read for the AProm of specified slot.
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*/
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bus_space_read_4(t->_slotbaset, t->_slotbaseh, 0);
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_bus_dmamap_sync(t, map, offset, len, ops);
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}
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struct newsmips_bus_dma_tag apbus_dma_tag = {
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_bus_dmamap_create,
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_bus_dmamap_destroy,
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_bus_dmamap_load,
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_bus_dmamap_load_mbuf,
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_bus_dmamap_load_uio,
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_bus_dmamap_load_raw,
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_bus_dmamap_unload,
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apbus_dmamap_sync,
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_bus_dmamem_alloc,
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_bus_dmamem_free,
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_bus_dmamem_map,
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_bus_dmamem_unmap,
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_bus_dmamem_mmap,
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};
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struct newsmips_bus_dma_tag *
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apbus_dmatag_init(apa)
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struct apbus_attach_args *apa;
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{
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struct newsmips_bus_dma_tag *dmat;
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dmat = malloc(sizeof(*dmat), M_DEVBUF, M_NOWAIT);
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if (dmat != NULL) {
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memcpy(dmat, &apbus_dma_tag, sizeof(*dmat));
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dmat->_slotno = apa->apa_slotno;
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dmat->_slotbaset = 0;
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dmat->_slotbaseh = apa->apa_hwbase;
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}
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return dmat;
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}
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