Display verbose messages about L2 cache.
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tsubai
parent
33104934d9
commit
654e155756
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@ -1,7 +1,7 @@
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/* $NetBSD: cpu.c,v 1.3 1999/02/16 15:20:51 tsubai Exp $ */
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/* $NetBSD: cpu.c,v 1.4 1999/06/30 16:34:19 tsubai Exp $ */
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/*-
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* Copyright (C) 1998 Internet Research Institute, Inc.
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* Copyright (C) 1998, 1999 Internet Research Institute, Inc.
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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@ -41,14 +41,15 @@
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static int cpumatch __P((struct device *, struct cfdata *, void *));
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static void cpuattach __P((struct device *, struct device *, void *));
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static void ohare_init __P((void));
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static void display_l2cr __P((void));
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struct cfattach cpu_ca = {
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sizeof(struct device), cpumatch, cpuattach
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};
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extern struct cfdriver cpu_cd;
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extern void *mapiodev();
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int
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cpumatch(parent, cf, aux)
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struct device *parent;
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@ -63,27 +64,55 @@ cpumatch(parent, cf, aux)
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return 1;
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}
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#define MPC601 1
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#define MPC603 3
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#define MPC604 4
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#define MPC603e 6
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#define MPC603ev 7
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#define MPC750 8
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#define HID0_DOZE 0x00800000
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#define HID0_NAP 0x00400000
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#define HID0_SLEEP 0x00200000
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#define HID0_DPM 0x00100000 /* 1: DPM enable */
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void
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cpuattach(parent, self, aux)
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struct device *parent, *self;
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void *aux;
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{
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u_int x;
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u_int *cache_reg;
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u_int node;
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int addr = -1;
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int hid0, pvr;
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node = OF_finddevice("/hammerhead");
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OF_getprop(node, "reg", &addr, sizeof(addr));
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if (addr == -1) {
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printf("\n");
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return;
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__asm __volatile ("mfpvr %0" : "=r"(pvr));
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switch (pvr >> 16) {
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case MPC603:
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case MPC603e:
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case MPC603ev:
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case MPC750:
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/* Select DOZE power-save mode. */
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__asm __volatile ("mfspr %0,1008" : "=r"(hid0));
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hid0 &= ~(HID0_DOZE | HID0_NAP | HID0_SLEEP);
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hid0 |= HID0_DOZE | HID0_DPM;
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__asm __volatile ("mtspr 1008,%0" :: "r"(hid0));
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}
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#if 0
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if ((pvr >> 16) == MPC750)
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display_l2cr();
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else if (OF_finddevice("/bandit/ohare") != -1)
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ohare_init();
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else
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printf("\n");
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}
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#define CACHE_REG 0xf8000000
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void
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ohare_init()
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{
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u_int *cache_reg, x;
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/* enable L2 cache */
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cache_reg = mapiodev(addr, NBPG);
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cache_reg = mapiodev(CACHE_REG, NBPG);
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if (((cache_reg[2] >> 24) & 0x0f) >= 3) {
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x = cache_reg[4];
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if ((x & 0x10) == 0)
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@ -92,9 +121,80 @@ cpuattach(parent, self, aux)
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x |= 0x04000020;
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cache_reg[4] = x;
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printf(": L2 cache enabled");
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printf(": ohare L2 cache enabled\n");
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}
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#endif
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}
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#define L2CR 1017
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#define L2CR_L2E 0x80000000 /* 0: L2 enable */
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#define L2CR_L2PE 0x40000000 /* 1: L2 data parity enable */
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#define L2CR_L2SIZ 0x30000000 /* 2-3: L2 size */
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#define L2SIZ_RESERVED 0x00000000
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#define L2SIZ_256K 0x10000000
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#define L2SIZ_512K 0x20000000
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#define L2SIZ_1M 0x30000000
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#define L2CR_L2CLK 0x0e000000 /* 4-6 */
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#define L2CR_L2RAM 0x01800000 /* 7-8: L2 RAM type */
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#define L2RAM_FLOWTHRU_BURST 0x00000000
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#define L2RAM_PIPELINE_BURST 0x01000000
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#define L2RAM_PIPELINE_LATE 0x01800000
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#define L2CR_L2DO 0x00400000 /* 9: L2 data-only.
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Setting this bit disables instruction
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caching. */
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#define L2CR_L2I 0x00200000 /* 10: L2 global invalidate. */
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#define L2CR_L2CTL 0x00100000 /* 11: L2 RAM control (ZZ enable).
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Enables automatic operation of the
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L2ZZ (low-power mode) signal. */
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#define L2CR_L2WT 0x00080000 /* 12: L2 write-through. */
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#define L2CR_L2TS 0x00040000 /* 13: L2 test support. */
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#define L2CR_L2OH 0x00030000 /* 14-15: L2 output hold. */
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#define L2CR_L2SL 0x00008000 /* 16: L2 DLL slow. */
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#define L2CR_L2DF 0x00004000 /* 17: L2 differential clock. */
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#define L2CR_L2BYP 0x00002000 /* 18: L2 DLL bypass. */
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#define L2CR_L2IP 0x00000001 /* 31: L2 global invalidate in progress
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(read only). */
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void
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display_l2cr()
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{
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u_int l2cr;
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__asm __volatile ("mfspr %0, 1017" : "=r"(l2cr));
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if (l2cr & L2CR_L2E) {
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switch (l2cr & L2CR_L2SIZ) {
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case L2SIZ_256K:
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printf(": 256KB");
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break;
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case L2SIZ_512K:
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printf(": 512KB");
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break;
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case L2SIZ_1M:
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printf(": 1MB");
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break;
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default:
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printf(": unknown size");
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}
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#if 0
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switch (l2cr & L2CR_L2RAM) {
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case L2RAM_FLOWTHRU_BURST:
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printf(" Flow-through synchronous burst SRAM");
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break;
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case L2RAM_PIPELINE_BURST:
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printf(" Pipelined synchronous burst SRAM");
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break;
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case L2RAM_PIPELINE_LATE:
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printf(" Pipelined synchronous late-write SRAM");
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break;
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default:
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printf(" unknown type");
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}
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if (l2cr & L2CR_L2PE)
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printf(" with parity");
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#endif
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printf(" backside cache enabled");
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}
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printf("\n");
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}
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