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Merge from jmcneill-pm:

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Add some more defines from the spec. Remove some old ones not
existing in the current Intel Architecture Guide. Use some more
understandable names.

ANSIfy and use uintXX_t to hurt my eyes less.

Further improve readability by exploiting __HAVE_TIMECOUNTER as
invariance on x86 platforms.
This commit is contained in:
joerg 2007-11-14 15:54:22 +00:00
parent 8f1126a23d
commit 64dcc1f587
2 changed files with 47 additions and 82 deletions
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35
sys/arch/x86/include/i82489reg.h
View File

@ -1,4 +1,4 @@
/* $NetBSD: i82489reg.h,v 1.2 2007/11/14 14:45:50 ad Exp $ */
/* $NetBSD: i82489reg.h,v 1.3 2007/11/14 15:54:22 joerg Exp $ */
/*-
* Copyright (c) 1998 The NetBSD Foundation, Inc.
@ -63,7 +63,11 @@
#define LAPIC_EOI 0x0b0 /* End Int. W */
#define LAPIC_RRR 0x0c0 /* Remote read R */
#define LAPIC_LDR 0x0d0 /* Logical dest. RW */
#define LAPIC_DFR 0x0e0 /* Dest. format RW */
# define LAPIC_DFR_MASK 0xf0000000
# define LAPIC_DFR_FLAT 0xf0000000
# define LAPIC_DFR_CLUSTER 0x00000000
#define LAPIC_SVR 0x0f0 /* Spurious intvec RW */
# define LAPIC_SVR_VECTOR_MASK 0x000000ff
@ -74,9 +78,9 @@
# define LAPIC_SVR_FOCUS 0x00000200
# define LAPIC_SVR_FDIS 0x00000200
#define LAPIC_ISR 0x100 /* Int. status. R */
#define LAPIC_TMR 0x180
#define LAPIC_IRR 0x200
#define LAPIC_ISR 0x100 /* In-Service Status */
#define LAPIC_TMR 0x180 /* Trigger Mode */
#define LAPIC_IRR 0x200 /* Interrupt Req */
#define LAPIC_ESR 0x280 /* Err status. R */
#define LAPIC_ICRLO 0x300 /* Int. cmd. RW */
@ -84,32 +88,31 @@
# define LAPIC_DLMODE_FIXED 0x00000000
# define LAPIC_DLMODE_LOW 0x00000100
# define LAPIC_DLMODE_SMI 0x00000200
# define LAPIC_DLMODE_RR 0x00000300
# define LAPIC_DLMODE_NMI 0x00000400
# define LAPIC_DLMODE_INIT 0x00000500
# define LAPIC_DLMODE_STARTUP 0x00000600
# define LAPIC_DLMODE_EXTINT 0x00000700
# define LAPIC_DSTMODE_PHYS 0x00000000
# define LAPIC_DSTMODE_LOG 0x00000800
# define LAPIC_DLSTAT_BUSY 0x00001000
# define LAPIC_DLSTAT_IDLE 0x00000000
# define LAPIC_LVL_ASSERT 0x00004000
# define LAPIC_LVL_DEASSERT 0x00000000
# define LAPIC_LEVEL_MASK 0x00004000
# define LAPIC_LEVEL_ASSERT 0x00004000
# define LAPIC_LEVEL_DEASSERT 0x00000000
# define LAPIC_LVL_TRIG 0x00008000
# define LAPIC_RRSTAT_MASK 0x00030000
# define LAPIC_RRSTAT_INPROG 0x00010000
# define LAPIC_RRSTAT_VALID 0x00020000
# define LAPIC_TRIGGER_MASK 0x00008000
# define LAPIC_TRIGGER_EDGE 0x00000000
# define LAPIC_TRIGGER_LEVEL 0x00008000
# define LAPIC_DEST_MASK 0x000c0000
# define LAPIC_DEST_DEFAULT 0x00000000
# define LAPIC_DEST_SELF 0x00040000
# define LAPIC_DEST_ALLINCL 0x00080000
# define LAPIC_DEST_ALLEXCL 0x000c0000
# define LAPIC_RESV2_MASK 0xfff00000
#define LAPIC_ICRHI 0x310 /* Int. cmd. RW */
# define LAPIC_ID_MASK 0x0f000000
@ -121,9 +124,9 @@
# define LAPIC_LVTT_M 0x00010000
# define LAPIC_LVTT_TM 0x00020000
#define LAPIC_PCINT 0x340
#define LAPIC_TMINT 0x330 /* Loc.vec (Thermal) */
#define LAPIC_PCINT 0x340 /* Loc.vec (Perf Mon) */
#define LAPIC_LVINT0 0x350 /* Loc.vec (LINT0) RW */
# define LAPIC_LVT_PERIODIC 0x00020000
# define LAPIC_LVT_MASKED 0x00010000
# define LAPIC_LVT_LEVTRIG 0x00008000
# define LAPIC_LVT_REMOTE_IRR 0x00004000

94
sys/arch/x86/x86/lapic.c
View File

@ -1,4 +1,4 @@
/* $NetBSD: lapic.c,v 1.26 2007/11/14 14:50:33 ad Exp $ */
/* $NetBSD: lapic.c,v 1.27 2007/11/14 15:54:22 joerg Exp $ */
/*-
* Copyright (c) 2000 The NetBSD Foundation, Inc.
@ -39,7 +39,7 @@
*/
#include <sys/cdefs.h>
__KERNEL_RCSID(0, "$NetBSD: lapic.c,v 1.26 2007/11/14 14:50:33 ad Exp $");
__KERNEL_RCSID(0, "$NetBSD: lapic.c,v 1.27 2007/11/14 15:54:22 joerg Exp $");
#include "opt_ddb.h"
#include "opt_mpbios.h" /* for MPDEBUG */
@ -67,9 +67,7 @@ __KERNEL_RCSID(0, "$NetBSD: lapic.c,v 1.26 2007/11/14 14:50:33 ad Exp $");
#include <machine/pcb.h>
#include <machine/specialreg.h>
#include <machine/segments.h>
#ifdef _HAVE_TIMECOUNTER
#include <x86/x86/tsc.h>
#endif
#include <machine/apicvar.h>
#include <machine/i82489reg.h>
@ -79,7 +77,7 @@ __KERNEL_RCSID(0, "$NetBSD: lapic.c,v 1.26 2007/11/14 14:50:33 ad Exp $");
void lapic_clockintr(void *, struct intrframe *);
static void lapic_delay(unsigned int);
static uint32_t lapic_gettick(void);
static uint32_t lapic_gettick(void);
static void lapic_map(paddr_t);
static void lapic_hwmask(struct pic *, int);
@ -101,8 +99,7 @@ struct pic local_pic = {
};
static void
lapic_map(lapic_base)
paddr_t lapic_base;
lapic_map(paddr_t lapic_base)
{
int s;
pt_entry_t *pte;
@ -136,13 +133,13 @@ lapic_map(lapic_base)
* enable local apic
*/
void
lapic_enable()
lapic_enable(void)
{
i82489_writereg(LAPIC_SVR, LAPIC_SVR_ENABLE | LAPIC_SPURIOUS_VECTOR);
}
void
lapic_set_lvt()
lapic_set_lvt(void)
{
struct cpu_info *ci = curcpu();
int i;
@ -204,8 +201,7 @@ lapic_set_lvt()
* Initialize fixed idt vectors for use by local apic.
*/
void
lapic_boot_init(lapic_base)
paddr_t lapic_base;
lapic_boot_init(paddr_t lapic_base)
{
lapic_map(lapic_base);
@ -224,7 +220,8 @@ lapic_boot_init(lapic_base)
idt_vec_set(LAPIC_TIMER_VECTOR, Xintr_lapic_ltimer);
}
static inline u_int32_t lapic_gettick()
static uint32_t
lapic_gettick(void)
{
return i82489_readreg(LAPIC_CCR_TIMER);
}
@ -232,23 +229,22 @@ static inline u_int32_t lapic_gettick()
#include <sys/kernel.h> /* for hz */
int lapic_timer = 0;
u_int32_t lapic_tval;
uint32_t lapic_tval;
/*
* this gets us up to a 4GHz busclock....
*/
u_int32_t lapic_per_second;
u_int32_t lapic_frac_usec_per_cycle;
u_int64_t lapic_frac_cycle_per_usec;
u_int32_t lapic_delaytab[26];
uint32_t lapic_per_second;
uint32_t lapic_frac_usec_per_cycle;
uint64_t lapic_frac_cycle_per_usec;
uint32_t lapic_delaytab[26];
extern u_int i8254_get_timecount(struct timecounter *);
void
lapic_clockintr(void *arg, struct intrframe *frame)
{
#ifndef __HAVE_TIMECOUNTER
static int microset_iter; /* call cc_microset once/sec */
#endif /* __HAVE_TIMECOUNTER */
#if defined(TIMECOUNTER_DEBUG) && defined(__HAVE_TIMECOUNTER)
#if defined(TIMECOUNTER_DEBUG)
static u_int last_count[X86_MAXPROCS],
last_delta[X86_MAXPROCS],
last_tsc[X86_MAXPROCS],
@ -259,7 +255,7 @@ lapic_clockintr(void *arg, struct intrframe *frame)
ci->ci_isources[LIR_TIMER]->is_evcnt.ev_count++;
#if defined(TIMECOUNTER_DEBUG) && defined(__HAVE_TIMECOUNTER)
#if defined(TIMECOUNTER_DEBUG)
{
int cid = ci->ci_cpuid;
extern u_int i8254_get_timecount(struct timecounter *);
@ -318,23 +314,7 @@ lapic_clockintr(void *arg, struct intrframe *frame)
last_tsc[cid] = c_tsc;
last_tscdelta[cid] = tsc_delta;
}
#endif /* TIMECOUNTER_DEBUG && __HAVE_TIMECOUNTER */
#ifndef __HAVE_TIMECOUNTER
/*
* If we have a cycle counter, do the microset thing.
*/
if (ci->ci_feature_flags & CPUID_TSC) {
if (CPU_IS_PRIMARY(ci) && (microset_iter--) == 0) {
microset_iter = hz - 1;
cc_microset_time = time;
#if defined(MULTIPROCESSOR)
x86_broadcast_ipi(X86_IPI_MICROSET);
#endif
cc_microset(ci);
}
}
#endif /* !__HAVE_TIMECOUNTER */
#endif /* TIMECOUNTER_DEBUG */
hardclock((struct clockframe *)frame);
}
@ -346,15 +326,6 @@ extern int fixtick;
void
lapic_initclocks()
{
#if !defined(__HAVE_TIMECOUNTER) && defined(NTP)
/*
* we'll actually get (lapic_per_second/lapic_tval) interrupts/sec.
*/
fixtick = 1000000 -
((int64_t)tick * lapic_per_second + lapic_tval / 2) / lapic_tval;
#endif /* !__HAVE_TIMECOUNTER && NTP */
/*
* Start local apic countdown timer running, in repeated mode.
*
@ -384,12 +355,11 @@ extern void (*initclock_func)(void); /* XXX put in header file */
* We're actually using the IRQ0 timer. Hmm.
*/
void
lapic_calibrate_timer(ci)
struct cpu_info *ci;
lapic_calibrate_timer(struct cpu_info *ci)
{
unsigned int starttick, tick1, tick2, endtick;
unsigned int startapic, apic1, apic2, endapic;
u_int64_t dtick, dapic, tmp;
uint64_t dtick, dapic, tmp;
int i;
char tbuf[9];
@ -477,11 +447,7 @@ lapic_calibrate_timer(ci)
*/
delay_func = lapic_delay;
initclock_func = lapic_initclocks;
#ifdef __HAVE_TIMECOUNTER
initrtclock(0);
#else
initrtclock();
#endif
}
}
@ -520,10 +486,8 @@ lapic_delay(unsigned int usec)
* XXX the following belong mostly or partly elsewhere..
*/
static inline void i82489_icr_wait(void);
static inline void
i82489_icr_wait()
static void
i82489_icr_wait(void)
{
#ifdef DIAGNOSTIC
unsigned j = 100000;
@ -540,8 +504,7 @@ i82489_icr_wait()
}
int
x86_ipi_init(target)
int target;
x86_ipi_init(int target)
{
if ((target&LAPIC_DEST_MASK)==0) {
@ -549,14 +512,14 @@ x86_ipi_init(target)
}
i82489_writereg(LAPIC_ICRLO, (target & LAPIC_DEST_MASK) |
LAPIC_DLMODE_INIT | LAPIC_LVL_ASSERT );
LAPIC_DLMODE_INIT | LAPIC_LEVEL_ASSERT );
i82489_icr_wait();
i8254_delay(10000);
i82489_writereg(LAPIC_ICRLO, (target & LAPIC_DEST_MASK) |
LAPIC_DLMODE_INIT | LAPIC_LVL_TRIG | LAPIC_LVL_DEASSERT);
LAPIC_DLMODE_INIT | LAPIC_TRIGGER_LEVEL | LAPIC_LEVEL_DEASSERT);
i82489_icr_wait();
@ -564,8 +527,7 @@ x86_ipi_init(target)
}
int
x86_ipi(vec,target,dl)
int vec,target,dl;
x86_ipi(int vec, int target, int dl)
{
int result, s;
@ -577,7 +539,7 @@ x86_ipi(vec,target,dl)
i82489_writereg(LAPIC_ICRHI, target << LAPIC_ID_SHIFT);
i82489_writereg(LAPIC_ICRLO,
(target & LAPIC_DEST_MASK) | vec | dl | LAPIC_LVL_ASSERT);
(target & LAPIC_DEST_MASK) | vec | dl | LAPIC_LEVEL_ASSERT);
#ifdef DIAGNOSTIC
i82489_icr_wait();