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Define the contents of the Video Valid register on the TGA and TGA2.

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thorpej 1998-04-29 02:11:19 +00:00
parent b54911c568
commit 6493eddd91
1 changed files with 16 additions and 1 deletions
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17
sys/dev/pci/tgareg.h
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@ -1,4 +1,4 @@
/* $NetBSD: tgareg.h,v 1.1 1998/04/15 20:16:33 drochner Exp $ */ /* $NetBSD: tgareg.h,v 1.2 1998/04/29 02:11:19 thorpej Exp $ */
/* /*
* Copyright (c) 1995, 1996 Carnegie-Mellon University. * Copyright (c) 1995, 1996 Carnegie-Mellon University.
@ -156,4 +156,19 @@ typedef u_int32_t tga_reg_t;
/* reserved 0x07f */ /* reserved 0x07f */
/*
* Video Valid Register
*/
#define VVR_VIDEOVALID 0x00000001 /* 0 VGA, 1 TGA2 (TGA2 only) */
#define VVR_BLANK 0x00000002 /* 0 active, 1 blank */
#define VVR_CURSOR 0x00000004 /* 0 disable, 1 enable (TGA2 R/O) */
#define VVR_INTERLACE 0x00000008 /* 0 N/Int, 1 Int. (TGA2 R/O) */
#define VVR_DPMS_MASK 0x00000030 /* See "DMPS mask" below */
#define VVR_DPMS_SHIFT 4
#define VVR_DDC 0x00000040 /* DDC-in pin value (R/O) */
#define VVR_TILED 0x00000400 /* 0 linear, 1 tiled (not on TGA2) */
#define VVR_LDDLY_MASK 0x01ff0000 /* load delay in quad pixel clock ticks
(not on TGA2) */
#define VVR_LDDLY_SHIFT 16
#endif /* _ALPHA_INCLUDE_TGAREG_H_ */ #endif /* _ALPHA_INCLUDE_TGAREG_H_ */