From 6489500f0a98c66d38d38d5e37cf78dcbe972b73 Mon Sep 17 00:00:00 2001
From: thorpej <thorpej@NetBSD.org>
Date: Sun, 1 Aug 1999 21:43:04 +0000
Subject: [PATCH] Make sure the branch target of the delay loop is aligned to a
 cache half-line (8-byte) boundary.  Inspired by a discussion w/ Scott
 Reynolds.

---
 sys/arch/sun3/sun3x/locore.s | 12 +++++++++++-
 sys/arch/x68k/x68k/locore.s  | 12 +++++++++++-
 2 files changed, 22 insertions(+), 2 deletions(-)

diff --git a/sys/arch/sun3/sun3x/locore.s b/sys/arch/sun3/sun3x/locore.s
index fd163da5473c..28b92e482c28 100644
--- a/sys/arch/sun3/sun3x/locore.s
+++ b/sys/arch/sun3/sun3x/locore.s
@@ -1,4 +1,4 @@
-/*	$NetBSD: locore.s,v 1.35 1999/04/30 09:21:54 christos Exp $	*/
+/*	$NetBSD: locore.s,v 1.36 1999/08/01 21:43:04 thorpej Exp $	*/
 
 /*
  * Copyright (c) 1988 University of Utah.
@@ -1068,6 +1068,16 @@ GLOBAL(_delay)
 	movl	sp@(4),d0
 	| d1 = delay_divisor;
 	movl	_C_LABEL(delay_divisor),d1
+	jra	L_delay			/* Jump into the loop! */
+
+	/*
+	 * Align the branch target of the loop to a half-line (8-byte)
+	 * boundary to minimize cache effects.  This guarantees both
+	 * that there will be no prefetch stalls due to cache line burst
+	 * operations and that the loop will run from a single cache
+	 * half-line.
+	 */
+	.align	8
 L_delay:
 	subl	d1,d0
 	jgt	L_delay
diff --git a/sys/arch/x68k/x68k/locore.s b/sys/arch/x68k/x68k/locore.s
index 5f43e9617077..8fa3acc22ae5 100644
--- a/sys/arch/x68k/x68k/locore.s
+++ b/sys/arch/x68k/x68k/locore.s
@@ -1,4 +1,4 @@
-/*	$NetBSD: locore.s,v 1.46 1999/05/05 13:46:20 minoura Exp $	*/
+/*	$NetBSD: locore.s,v 1.47 1999/08/01 21:45:35 thorpej Exp $	*/
 
 /*
  * Copyright (c) 1988 University of Utah.
@@ -1663,6 +1663,16 @@ ENTRY_NOPROFILE(_delay)
 	movl	sp@(4),d0
 	| d1 = delay_divisor
 	movl	_C_LABEL(delay_divisor),d1
+	jra	L_delay			/* Jump into the loop! */
+
+	/*
+	 * Align the branch target of the loop to a half-line (8-byte)
+	 * boundary to minimize cache effects.  This guarantees both
+	 * that there will be no prefetch stalls due to cache line burst
+	 * operations and that the loop will run from a single cache
+	 * half-line.
+	 */
+	.align	8
 L_delay:
 	subl	d1,d0
 	jgt	L_delay