more additions from nonaka's landisk port.
This commit is contained in:
christos
parent
104d75eb91
commit
63fcf30b44
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@ -1,4 +1,4 @@
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/* $NetBSD: cache_sh4.h,v 1.5 2002/04/28 17:10:33 uch Exp $ */
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/* $NetBSD: cache_sh4.h,v 1.6 2005/06/29 16:51:20 christos Exp $ */
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/*-
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* Copyright (c) 2002 The NetBSD Foundation, Inc.
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@ -37,7 +37,7 @@
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*/
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/*
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* SH4: SH7750 SH7750S
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* SH4: SH7750 SH7750S SH7750R SH7751 SH7751R
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*/
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#ifndef _SH3_CACHE_SH4_H_
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@ -50,6 +50,7 @@
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#define SH4_CACHE_LINESZ 32
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#define SH4_CCR 0xff00001c
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#define SH4_CCR_EMODE 0x80000000
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#define SH4_CCR_IIX 0x00008000
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#define SH4_CCR_ICI 0x00000800
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#define SH4_CCR_ICE 0x00000100
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@ -86,7 +87,7 @@
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/* address specification */
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#define CCDA_A 0x00000008 /* associate bit */
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#define CCDA_ENTRY_SHIFT 5 /* line size 32B */
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#define CCDA_ENTRY_MASK 0x00003fe0 /* [13:5] 512-entries */
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#define CCDA_ENTRY_MASK 0x00003fe0 /* [13:5] 256-entries */
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/* data specification */
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#define CCDA_V 0x00000001
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#define CCDA_U 0x00000002
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@ -105,12 +106,12 @@ do { \
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u_int32_t __e, __a; \
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\
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/* D-cache */ \
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for (__e = 0; __e < (SH4_DCACHE_SIZE / SH4_CACHE_LINESZ); __e++) {\
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for (__e = 0; __e < (sh_cache_size_dcache / SH4_CACHE_LINESZ); __e++) {\
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__a = SH4_CCDA | (__e << CCDA_ENTRY_SHIFT); \
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(*(__volatile__ u_int32_t *)__a) &= ~(CCDA_U | CCDA_V); \
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} \
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/* I-cache */ \
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for (__e = 0; __e < (SH4_ICACHE_SIZE / SH4_CACHE_LINESZ); __e++) {\
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for (__e = 0; __e < (sh_cache_size_icache / SH4_CACHE_LINESZ); __e++) {\
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__a = SH4_CCIA | (__e << CCIA_ENTRY_SHIFT); \
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(*(__volatile__ u_int32_t *)__a) &= ~(CCIA_V); \
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} \
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@ -118,6 +119,10 @@ do { \
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#define SH7750_CACHE_FLUSH() SH4_CACHE_FLUSH()
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#define SH7750S_CACHE_FLUSH() SH4_CACHE_FLUSH()
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#define SH7750R_CACHE_FLUSH() SH4_CACHE_FLUSH()
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#define SH7751_CACHE_FLUSH() SH4_CACHE_FLUSH()
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#define SH7751R_CACHE_FLUSH() SH4_CACHE_FLUSH()
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#ifndef _LOCORE
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extern void sh4_cache_config(void);
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@ -1,4 +1,4 @@
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/* $NetBSD: cputypes.h,v 1.7 2002/04/28 17:10:34 uch Exp $ */
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/* $NetBSD: cputypes.h,v 1.8 2005/06/29 16:51:20 christos Exp $ */
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/*-
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* Copyright (c) 2002 The NetBSD Foundation, Inc.
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@ -59,6 +59,10 @@
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/* SH4 series */
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#define CPU_PRODUCT_7750 6
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#define CPU_PRODUCT_7750S 7
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#define CPU_PRODUCT_7750R 8
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#define CPU_PRODUCT_7751 9
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#define CPU_PRODUCT_7751R 10
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#ifndef _LOCORE
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extern int cpu_arch;
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@ -1,4 +1,4 @@
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/* $NetBSD: exception.h,v 1.5 2004/03/25 01:02:30 uwe Exp $ */
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/* $NetBSD: exception.h,v 1.6 2005/06/29 16:51:20 christos Exp $ */
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/*-
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* Copyright (c) 2002 The NetBSD Foundation, Inc.
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@ -133,6 +133,41 @@
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#define SH7709_INTEVT2_ADC 0x980
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/* SH7750R, SH7751, SH7751R */
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#define SH4_INTEVT_IRL0 0x240
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#define SH4_INTEVT_IRL1 0x2a0
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#define SH4_INTEVT_IRL2 0x300
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#define SH4_INTEVT_IRL3 0x360
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#define SH4_INTEVT_IRQ0 0x200
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#define SH4_INTEVT_IRQ1 0x220
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#define SH4_INTEVT_IRQ2 0x240
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#define SH4_INTEVT_IRQ3 0x260
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#define SH4_INTEVT_IRQ4 0x280
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#define SH4_INTEVT_IRQ5 0x2a0
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#define SH4_INTEVT_IRQ6 0x2c0
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#define SH4_INTEVT_IRQ7 0x2e0
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#define SH4_INTEVT_IRQ8 0x300
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#define SH4_INTEVT_IRQ9 0x320
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#define SH4_INTEVT_IRQ10 0x340
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#define SH4_INTEVT_IRQ11 0x360
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#define SH4_INTEVT_IRQ12 0x380
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#define SH4_INTEVT_IRQ13 0x3a0
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#define SH4_INTEVT_IRQ14 0x3c0
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#define SH4_INTEVT_IRQ15 0x3e0
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#define SH4_INTEVT_TMU3 0xb00
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#define SH4_INTEVT_TMU4 0xb80
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#define SH4_INTEVT_PCISERR 0xa00
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#define SH4_INTEVT_PCIERR 0xae0
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#define SH4_INTEVT_PCIPWDWN 0xac0
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#define SH4_INTEVT_PCIPWON 0xaa0
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#define SH4_INTEVT_PCIDMA0 0xa80
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#define SH4_INTEVT_PCIDMA1 0xa60
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#define SH4_INTEVT_PCIDMA2 0xa40
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#define SH4_INTEVT_PCIDMA3 0xa20
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#ifndef _LOCORE
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#if defined(SH3) && defined(SH4)
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extern u_int32_t __sh_TRA;
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@ -1,4 +1,4 @@
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/* $NetBSD: intcreg.h,v 1.7 2003/10/07 01:24:32 uwe Exp $ */
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/* $NetBSD: intcreg.h,v 1.8 2005/06/29 16:51:20 christos Exp $ */
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/*-
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* Copyright (C) 1999 SAITOH Masanobu. All rights reserved.
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@ -80,12 +80,21 @@
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#define SH4_IPRB 0xffd00008 /* 16bit */
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#define SH4_IPRC 0xffd0000c /* 16bit */
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#define SH4_IPRD 0xffd00010 /* 16bit */
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#define SH4_INTPRI00 0xfe080000 /* 32bit */
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#define SH4_INTREQ00 0xfe080020 /* 32bit */
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#define SH4_INTMSK00 0xfe080040 /* 32bit */
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#define SH4_INTMSKCLR00 0xfe080060 /* 32bit */
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#define IPRC_GPIO_MASK 0xf000
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#define IPRC_DMAC_MASK 0x0f00
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#define IPRC_SCIF_MASK 0x00f0
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#define IPRC_HUDI_MASK 0x000f
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#define IPRD_IRL0_MASK 0xf000
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#define IPRD_IRL1_MASK 0x0f00
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#define IPRD_IRL2_MASK 0x00f0
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#define IPRD_IRL3_MASK 0x000f
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#define IPRA_TMU0_MASK 0xf000
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#define IPRA_TMU1_MASK 0x0f00
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#define IPRA_TMU2_MASK 0x00f0
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#define IPRB_REF_MASK 0x0f00
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#define IPRB_SCI_MASK 0x00f0
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#define INTPRI00_PCI0_MASK 0x0000000f
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#define INTPRI00_PCI1_MASK 0x000000f0
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#define INTPRI00_TMU3_MASK 0x00000f00
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#define INTPRI00_TMU4_MASK 0x0000f000
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/* INTREQ/INTMSK/INTMSKCLR */
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#define INTREQ00_PCISERR 0x00000001
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#define INTREQ00_PCIDMA3 0x00000002
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#define INTREQ00_PCIDMA2 0x00000004
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#define INTREQ00_PCIDMA1 0x00000008
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#define INTREQ00_PCIDMA0 0x00000010
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#define INTREQ00_PCIPWON 0x00000020
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#define INTREQ00_PCIPWDWN 0x00000040
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#define INTREQ00_PCIERR 0x00000080
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#define INTREQ00_TUNI3 0x00000100
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#define INTREQ00_TUNI4 0x00000200
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#endif /* !_SH3_INTCREG_H_ */
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@ -1,4 +1,4 @@
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/* $NetBSD: scifreg.h,v 1.4 2002/05/19 15:10:46 msaitoh Exp $ */
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/* $NetBSD: scifreg.h,v 1.5 2005/06/29 16:51:20 christos Exp $ */
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/*-
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* Copyright (C) 1999 SAITOH Masanobu. All rights reserved.
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@ -130,6 +130,15 @@
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#define FIFO_XMT_TRIGGER_2 0x0020
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#define FIFO_XMT_TRIGGER_1 0x0030
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#define SCSPTR2_RTSIO 0x0080
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#define SCSPTR2_RTSDT 0x0040
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#define SCSPTR2_CTSIO 0x0020
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#define SCSPTR2_CTSDT 0x0010
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#define SCSPTR2_SCKIO 0x0008
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#define SCSPTR2_SCKDT 0x0004
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#define SCSPTR2_SPB2IO 0x0002
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#define SCSPTR2_SPB2DT 0x0001
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#define SCLSR2_ORER 0x0001 /* overrun error */
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#endif
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@ -1,4 +1,4 @@
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/* $NetBSD: tmureg.h,v 1.7 2002/04/28 17:10:37 uch Exp $ */
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/* $NetBSD: tmureg.h,v 1.8 2005/06/29 16:51:20 christos Exp $ */
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/*-
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* Copyright (C) 1999 SAITOH Masanobu. All rights reserved.
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#define SH4_TCNT2 0xffd80024
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#define SH4_TCR2 0xffd80028
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#define SH4_TCPR2 0xffd8002c
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#define SH4_TSTR2 0xfe100004
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#define SH4_TCOR3 0xfe100008
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#define SH4_TCNT3 0xfe10000c
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#define SH4_TCR3 0xfe100010
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#define SH4_TCOR4 0xfe100014
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#define SH4_TCNT4 0xfe100018
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#define SH4_TCR4 0xfe10001c
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#define TOCR_TCOE 0x01
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#define TSTR_STR2 0x04
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#define TSTR_STR1 0x02
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#define TSTR_STR0 0x01
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#define TCR_ICPF 0x0200
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#define TCR_UNF 0x0100
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#define TCR_ICPE1 0x0080
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#define TCR_ICPE0 0x0040
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#define TCR_UNIE 0x0020
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#define TCR_CKEG1 0x0010
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#define TCR_CKEG0 0x0008
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#define TCR_TPSC2 0x0004
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#define TCR_TPSC1 0x0002
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#define TCR_TPSC0 0x0001
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#define TCR_TPSC_P4 0x0000
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#define TCR_TPSC_P16 0x0001
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#define TCR_TPSC_P64 0x0002
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#define TCR_TPSC_P1024 0x0003
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#define SH3_TCR_TPSC_RTC 0x0004
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#define SH3_TCR_TPSC_TCLK 0x0005
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#define SH4_TCR_TPSC_P512 0x0004
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#define SH4_TCR_TPSC_RTC 0x0006
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#define SH4_TCR_TPSC_TCLK 0x0007
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#define SH4_TSTR2_STR4 0x02
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#define SH4_TSTR2_STR3 0x01
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#define TOCR_TCOE 0x01
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#define TSTR_STR2 0x04
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#define TSTR_STR1 0x02
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#define TSTR_STR0 0x01
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#define TCR_ICPF 0x0200
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#define TCR_UNF 0x0100
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#define TCR_ICPE1 0x0080
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#define TCR_ICPE0 0x0040
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#define TCR_UNIE 0x0020
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#define TCR_CKEG1 0x0010
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#define TCR_CKEG0 0x0008
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#define TCR_TPSC2 0x0004
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#define TCR_TPSC1 0x0002
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#define TCR_TPSC0 0x0001
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#define TCR_TPSC_P4 0x0000
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#define TCR_TPSC_P16 0x0001
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#define TCR_TPSC_P64 0x0002
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#define TCR_TPSC_P256 0x0003
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#define SH3_TCR_TPSC_RTC 0x0004
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#define SH3_TCR_TPSC_TCLK 0x0005
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#define SH4_TCR_TPSC_P512 0x0004
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#define SH4_TCR_TPSC_RTC 0x0006
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#define SH4_TCR_TPSC_TCLK 0x0007
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#ifndef _LOCORE
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#if defined(SH3) && defined(SH4)
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