First pass at native NetBSD/mips support for GDB.
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jonathan
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63abec08b2
431
gnu/dist/gdb/mipsnbsd-nat.c
vendored
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431
gnu/dist/gdb/mipsnbsd-nat.c
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/* Native-dependent code for BSD Unix running on i386's, for GDB.
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Copyright 1997 Free Software Foundation, Inc.
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Contributed by Jonathan Stone(jonathan@dsg.stanford.edu) at Stanford
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This file is part of GDB.
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This program is free software; you can redistribute it and/or modify
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it under the terms of the GNU General Public License as published by
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the Free Software Foundation; either version 2 of the License, or
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(at your option) any later version.
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This program is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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GNU General Public License for more details.
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You should have received a copy of the GNU General Public License
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along with this program; if not, write to the Free Software
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Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
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$Id: mipsnbsd-nat.c,v 1.1 1997/10/19 20:52:57 jonathan Exp $
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*/
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#include <sys/types.h>
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#include <sys/param.h>
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#include <signal.h>
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#include <sys/user.h>
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#include <sys/ptrace.h>
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#include <machine/reg.h>
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#include <setjmp.h>
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#include "defs.h"
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#include "inferior.h"
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#include "gdbcore.h"
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#define JB_ELEMENT_SIZE 4
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void
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fetch_inferior_registers (regno)
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int regno;
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{
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struct reg inferior_registers;
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struct fpreg inferior_fp_registers;
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bzero(&inferior_registers, sizeof(inferior_registers));
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ptrace (PT_GETREGS, inferior_pid,
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(PTRACE_ARG3_TYPE) &inferior_registers, 0);
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memcpy (®isters[REGISTER_BYTE (0)], &inferior_registers, 4*71);
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bzero(&inferior_fp_registers, sizeof(inferior_fp_registers));
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ptrace (PT_GETFPREGS, inferior_pid,
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(PTRACE_ARG3_TYPE) &inferior_fp_registers, 0);
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memcpy (®isters[REGISTER_BYTE (18)], &inferior_fp_registers, 8*12+4*3);
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registers_fetched ();
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}
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void
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store_inferior_registers (regno)
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int regno;
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{
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struct reg inferior_registers;
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struct fpreg inferior_fp_registers;
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memcpy (&inferior_registers, ®isters[REGISTER_BYTE (0)], 4*71);
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ptrace (PT_SETREGS, inferior_pid,
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(PTRACE_ARG3_TYPE) &inferior_registers, 0);
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memcpy (&inferior_fp_registers, ®isters[REGISTER_BYTE (18)], 8*12+4*3);
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ptrace (PT_SETFPREGS, inferior_pid,
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(PTRACE_ARG3_TYPE) &inferior_fp_registers, 0);
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}
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/* Figure out where the longjmp will land.
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We expect the first arg to be a pointer to the jmp_buf structure from which
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we extract the pc (JB_PC) that we will land at. The pc is copied into PC.
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This routine returns true on success. */
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int
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get_longjmp_target(pc)
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CORE_ADDR *pc;
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{
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CORE_ADDR jb_addr;
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char buf[TARGET_PTR_BIT / TARGET_CHAR_BIT];
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jb_addr = read_register (A0_REGNUM);
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if (target_read_memory (jb_addr + JB_PC * JB_ELEMENT_SIZE, buf,
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TARGET_PTR_BIT / TARGET_CHAR_BIT))
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return 0;
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*pc = extract_address (buf, TARGET_PTR_BIT / TARGET_CHAR_BIT);
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return 1;
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}
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/* XXX - Add this to machine/regs.h instead? */
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struct md_core {
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struct reg intreg;
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struct fpreg freg;
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};
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/* Extract the register values out of the core file and store
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them where `read_register' will find them.
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CORE_REG_SECT points to the register values themselves, read into memory.
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CORE_REG_SIZE is the size of that area.
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WHICH says which set of registers we are handling (0 = int, 2 = float
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on machines where they are discontiguous).
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REG_ADDR is the offset from u.u_ar0 to the register values relative to
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core_reg_sect. This is used with old-fashioned core files to
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locate the registers in a large upage-plus-stack ".reg" section.
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Original upage address X is at location core_reg_sect+x+reg_addr.
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*/
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void
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fetch_core_registers (core_reg_sect, core_reg_size, which, ignore)
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char *core_reg_sect;
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unsigned core_reg_size;
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int which;
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unsigned int ignore; /* reg addr, unused in this version */
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{
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struct md_core *core_reg;
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core_reg = (struct md_core *)core_reg_sect;
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if (which == 0) {
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/* Integer registers */
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memcpy(®isters[REGISTER_BYTE (0)],
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&core_reg->intreg, sizeof(struct reg));
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}
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else if (which == 2) {
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/* Floating point registers */
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memcpy(®isters[REGISTER_BYTE (FP0_REGNUM)],
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&core_reg->freg, sizeof(struct fpreg));
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}
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}
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/* Get registers from a kernel crash dump.
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FIXME: NetBSD 1.3 does not produce kernel crashdumps. */
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void
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fetch_kcore_registers(pcb)
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struct pcb *pcb;
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{
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int i, *ip, tmp=0;
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u_long sp;
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#if 0
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supply_register(SP_REGNUM, (char *)&pcb->pcb_sp);
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supply_register(PC_REGNUM, (char *)&pcb->pcb_pc);
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#endif
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/* The kernel does not use the FPU, so ignore it. */
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registers_fetched ();
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}
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#ifdef __NetBSD__
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/* Non-zero if we just simulated a single-step ptrace call. This is
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needed because we cannot remove the breakpoints in the inferior
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process until after the `wait' in `wait_for_inferior'. Used for
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4.4bsd for mips, where the kernel does not emulate single-step. */
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int one_stepped;
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CORE_ADDR target_addr; /* Branch target offset, if we have a
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breakpoint there... */
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CORE_ADDR step_addr; /* Offset of instruction after instruction
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to be stepped, if we have a breakpoint
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there. */
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long step_cache [3]; /* Cache for instructions wiped out by
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step breakpoint(s)... */
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/* single_step() is called just before we want to resume the inferior,
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if we want to single-step it but there is no hardware or kernel single-step
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support (as on 4.4bsd for pmax). We find all the possible targets of the
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coming instruction and breakpoint them.
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single_step is also called just after the inferior stops. If we had
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set up a simulated single-step, we undo our damage. */
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/* thoughts:
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For the current instruction, check to see if we're in a delay slot.
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If we are, the next instruction executed will either be the target of
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the branch or jump instruction preceding the current instruction, or
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it will be the instruction following the current instruction. If
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we are not, then the next instruction executed will either be the
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instruction following the current instruction, or the instruction
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following that (if the current instruction is a branch likely instruction
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and the branch is not taken).
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So, if we are in a delay slot then we set a breakpoint for the target
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of the preceding instruction. Unless the preceding instruction was
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a jump instruction (only jumps are unconditional), we also set a break-
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point at the instruction following the current one and the instruction
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following that. Setting two breakpoints after the current instruction
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is cheaper and easier than figuring out whether the current instruction
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is a branch likely instruction. */
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void
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single_step (ignore)
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int ignore; /* pid, but we don't need it */
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{
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CORE_ADDR pc;
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CORE_ADDR epc;
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CORE_ADDR next;
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unsigned long cause;
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unsigned long delay_instruction;
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if (!one_stepped)
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{
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epc = read_register (PC_REGNUM);
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cause = read_register (CAUSE_REGNUM);
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pc = epc;
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#define CAUSE_BD 0x80000000UL
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if (cause & CAUSE_BD)
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pc += 4;
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next = pc + 4;
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target_addr = 0;
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step_addr = next;
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if (cause & CAUSE_BD)
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{
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delay_instruction =
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read_memory_integer (epc, sizeof(delay_instruction));
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/* Main instruction opcode mask - top six bits... */
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#define MI_IMASK 0xfc000000UL
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/* Opcode for ``special'' instructions.... */
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#define MI_SPECIAL 0x0
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/* Opcode for ``regimm'' instructions... */
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#define MI_REGIMM 0x04000000
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/* Mask for special instruction opcodes... */
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#if 0
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# define MS_IMASK 0x37 /* XXX Mellon's original, broken? */
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#else
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# define MS_IMASK 0x3f /* XXX jrs attempt at fix */
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#endif
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/* JALR and JR are special instructions... */
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#define MS_JALR 9
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#define MS_JR 8
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/* Target register for jump... */
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#define MS_JR_REG(x) (((x) & 0x03e00000) >> 21)
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/* J and JAL are regular instructions... */
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#define MI_J 0x08000000
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#define MI_JAL 0x0c000000
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/* All the bits following the opcode are used in J and JAL instructions... */
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#define MI_JMASK (~MI_IMASK)
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#define MI_JSIGN 0x20000000
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/* Coprocessor instructions use the bottom two bits of the opcode as a
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coprocessor id, so we only test the top four bits to see if this is a
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COPz instruction... */
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#define MC_MASK 0xf0000000UL
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#define MC_COPz 0x40000000
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/* The coprocessor subopcode is in the five bits following the regular
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instruction opcode... */
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#define MCB_MASK 0x03e00000
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/* All coprocessor branches have the following subopcode... */
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#define MCB_BC 0x01000000
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/* Offsets for coprocessor branches are contained in the bottom 16 bis. */
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#define MCB_OFFSET 0xffff
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/* The following are all the branch instructions with regular opcodes: */
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#define MI_BEQ 0x10000000
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#define MI_BEQL 0x50000000
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#define MI_BGTZ 0x1c000000
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#define MI_BGTZL 0x5c000000
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#define MI_BLEZ 0x18000000
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#define MI_BLEZL 0x58000000
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#define MI_BNE 0x14000000
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#define MI_BNEL 0x54000000
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/* They also use the lower sixteen bits for their target offset... */
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#define BRANCH_OFFSET 0xffff
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/* REGIMM instructions have a second opcode in bits 20 through 16... */
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#define REGIMM_MASK 0x001f0000
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/* The following are all the ``regimm'' branch instructions: */
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#define MRI_BGEZ 0x00010000
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#define MRI_BGEZAL 0x00110000
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#define MRI_BGEZALL 0x00130000
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#define MRI_BGEZL 0x00030000
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#define MRI_BLTZ 0x00000000
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#define MRI_BLTZAL 0x00100000
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#define MRI_BLTZALL 0x00120000
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#define MRI_BLTZL 0x00020000
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/* Decode the instruction sufficiently to determine
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the branch target... */
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switch (delay_instruction & MI_IMASK)
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{
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case MI_J:
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case MI_JAL:
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target_addr = delay_instruction & MI_JMASK;
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/* Sign extend... */
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if (target_addr & MI_JSIGN)
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target_addr |= ~(CORE_ADDR)MI_JMASK;
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target_addr += (pc >> 2) & ~MI_JMASK;
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target_addr <<= 2;
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step_addr = 0;
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break;
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case MI_SPECIAL:
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switch (delay_instruction & MS_IMASK)
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{
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case MS_JALR:
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case MS_JR:
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target_addr +=
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read_register (MS_JR_REG (delay_instruction));
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step_addr = 0;
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break;
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default:
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bad_delay:
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error ("In delay slot of non-branch instruction: %x\n",
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delay_instruction);
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break;
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}
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break;
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case MI_REGIMM:
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switch (delay_instruction & REGIMM_MASK)
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{
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case MRI_BGEZ:
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case MRI_BGEZAL:
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case MRI_BGEZALL:
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case MRI_BGEZL:
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case MRI_BLTZ:
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case MRI_BLTZAL:
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case MRI_BLTZALL:
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case MRI_BLTZL:
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/* Compiler should sign extend this... */
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target_addr = (short)delay_instruction;
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target_addr <<= 2;
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target_addr += pc;
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break;
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default:
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error ("In delay slot, register-immediate insn: %x\n",
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delay_instruction);
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goto bad_delay;
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}
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break;
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case MI_BEQ:
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case MI_BEQL:
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case MI_BGTZ:
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case MI_BGTZL:
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case MI_BLEZ:
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case MI_BLEZL:
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case MI_BNE:
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case MI_BNEL:
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target_addr = (short)delay_instruction;
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target_addr <<= 2;
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target_addr += pc;
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break;
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default:
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error ("In delay slot, unrecognised instruction: %x\n",
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delay_instruction);
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goto bad_delay;
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}
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}
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/* Don't try to put down two breakpoints in the same spot... */
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if (step_addr == target_addr)
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target_addr = 0;
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if (step_addr)
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{
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target_insert_breakpoint (step_addr, (char *)&step_cache [0]);
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if (step_addr + 4 != target_addr)
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target_insert_breakpoint (step_addr + 4, (char *)&step_cache [1]);
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}
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if (target_addr)
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{
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target_insert_breakpoint (target_addr, (char *)&step_cache [2]);
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}
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/* If the breakpoint occurred in a branch instruction,
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re-run the branch (the breakpoint instruction should
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be gone by now)... */
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if (epc != pc)
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{
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write_register (PC_REGNUM, epc);
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}
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one_stepped = 1;
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return;
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}
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else
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{
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epc = read_register (PC_REGNUM);
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cause = read_register (CAUSE_REGNUM);
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pc = epc;
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#define CAUSE_BD 0x80000000UL
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if (cause & CAUSE_BD)
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pc += 4;
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/* Remove step breakpoints */
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if (step_addr)
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{
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target_remove_breakpoint (step_addr, (char *)&step_cache [0]);
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if (step_addr + 4 != target_addr)
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target_remove_breakpoint (step_addr + 4, (char *)&step_cache [1]);
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}
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if (target_addr)
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{
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target_remove_breakpoint (target_addr, (char *)&step_cache [2]);
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target_addr = 0;
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}
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one_stepped = 0;
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}
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}
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/* Register that we are able to handle core file formats.
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FIXME: is this really bfd_target_unknown_flavour? */
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static struct core_fns netbsd_core_fns =
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{
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bfd_target_unknown_flavour,
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fetch_core_registers,
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NULL
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};
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void
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_initialize_mipsbsd_nat ()
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{
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add_core_fns (&netbsd_core_fns);
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}
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#endif /* __NetBSD__ */
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