These are not used anymore.
This commit is contained in:
ragge
parent
b80b95a77a
commit
630d0523f6
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@ -1,920 +0,0 @@
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/* $NetBSD: uba.c,v 1.51 2000/08/09 03:02:52 tv Exp $ */
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/*
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* Copyright (c) 1996 Jonathan Stone.
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* Copyright (c) 1994, 1996 Ludd, University of Lule}, Sweden.
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* Copyright (c) 1982, 1986 The Regents of the University of California.
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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||||
* notice, this list of conditions and the following disclaimer.
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||||
* 2. Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in the
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||||
* documentation and/or other materials provided with the distribution.
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||||
* 3. All advertising materials mentioning features or use of this software
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||||
* must display the following acknowledgement:
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* This product includes software developed by the University of
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* California, Berkeley and its contributors.
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* 4. Neither the name of the University nor the names of its contributors
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* may be used to endorse or promote products derived from this software
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* without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*
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* @(#)uba.c 7.10 (Berkeley) 12/16/90
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* @(#)autoconf.c 7.20 (Berkeley) 5/9/91
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*/
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#include <sys/param.h>
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#include <sys/types.h>
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#include <sys/time.h>
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#include <sys/systm.h>
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#include <sys/map.h>
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#include <sys/buf.h>
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#include <sys/proc.h>
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#include <sys/user.h>
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#include <sys/conf.h>
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#include <sys/dkstat.h>
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#include <sys/kernel.h>
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#include <sys/malloc.h>
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#include <sys/device.h>
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#include <uvm/uvm_extern.h>
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#include <machine/pte.h>
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#include <machine/cpu.h>
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#include <machine/mtpr.h>
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#include <machine/nexus.h>
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#include <machine/sid.h>
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#include <machine/scb.h>
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#include <machine/frame.h>
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#include <vax/uba/ubareg.h>
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#include <dev/qbus/ubavar.h>
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volatile int /* rbr, rcvec,*/ svec;
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static int ubasearch __P((struct device *, struct cfdata *, void *));
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static int ubaprint __P((void *, const char *));
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#if 0
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static void ubastray __P((int));
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#endif
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static void ubainitmaps __P((struct uba_softc *));
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extern struct cfdriver uba_cd;
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#define spluba spl7
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#if defined(DW780) || defined(DW750)
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int dw_match __P((struct device *, struct cfdata *, void *));
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int
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dw_match(parent, cf, aux)
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struct device *parent;
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struct cfdata *cf;
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void *aux;
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{
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struct sbi_attach_args *sa = (struct sbi_attach_args *)aux;
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if ((cf->cf_loc[0] != sa->nexnum) && (cf->cf_loc[0] > -1 ))
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return 0;
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/*
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* The uba type is actually only telling where the uba
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* space is in nexus space.
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*/
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if ((sa->type & ~3) != NEX_UBA0)
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return 0;
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return 1;
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}
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#endif
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#ifdef DW780
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/*
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* The DW780 are directly connected to the SBI on 11/780 and 8600.
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*/
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void dw780_attach __P((struct device *, struct device *, void *));
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void dw780_beforescan __P((struct uba_softc *));
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void dw780_afterscan __P((struct uba_softc *));
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int dw780_errchk __P((struct uba_softc *));
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void dw780_init __P((struct uba_softc *));
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void dw780_purge __P((struct uba_softc *, int));
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void uba_dw780int __P((int));
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static void ubaerror __P((struct uba_softc *, int *, int *));
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struct cfattach uba_sbi_ca = {
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sizeof(struct uba_softc), dw_match, dw780_attach
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};
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char ubasr_bits[] = UBASR_BITS;
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void
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dw780_attach(parent, self, aux)
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struct device *parent, *self;
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void *aux;
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{
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struct uba_softc *sc = (void *)self;
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struct sbi_attach_args *sa = aux;
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int ubaddr = sa->type & 3;
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int i;
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printf(": DW780\n");
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/*
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* Fill in bus specific data.
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*/
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sc->uh_uba = (void *)sa->nexaddr;
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sc->uh_nbdp = NBDP780;
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sc->uh_nr = sa->nexnum * (parent->dv_unit + 1);
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sc->uh_beforescan = dw780_beforescan;
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sc->uh_afterscan = dw780_afterscan;
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sc->uh_errchk = dw780_errchk;
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sc->uh_ubapurge = dw780_purge;
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sc->uh_ubainit = dw780_init;
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sc->uh_type = DW780;
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sc->uh_memsize = UBAPAGES;
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sc->uh_ibase = VAX_NBPG + ubaddr * VAX_NBPG;
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sc->uh_mr = sc->uh_uba->uba_map;
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for (i = 0; i < 4; i++)
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scb_vecalloc(256 + i * 64 + sa->nexnum * 4, uba_dw780int,
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sc->uh_dev.dv_unit, SCB_ISTACK, &sc->uh_intrcnt);
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evcnt_attach_dynamic(&sc->uh_intrcnt, EVCNT_TYPE_INTR, NULL,
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sc->uh_dev.dev_xname, "intr");
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uba_attach(sc, (parent->dv_unit ? UMEMB8600(ubaddr) :
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UMEMA8600(ubaddr)) + (UBAPAGES * VAX_NBPG));
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}
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void
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dw780_beforescan(sc)
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struct uba_softc *sc;
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{
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volatile int *hej = &sc->uh_uba->uba_sr;
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*hej = *hej;
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sc->uh_uba->uba_cr = UBACR_IFS|UBACR_BRIE;
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}
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void
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dw780_afterscan(sc)
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struct uba_softc *sc;
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{
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sc->uh_uba->uba_cr = UBACR_IFS | UBACR_BRIE |
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UBACR_USEFIE | UBACR_SUEFIE |
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(sc->uh_uba->uba_cr & 0x7c000000);
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}
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/*
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* On DW780 badaddr() in uba space sets a bit in uba_sr instead of
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* doing a machine check.
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*/
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int
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dw780_errchk(sc)
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struct uba_softc *sc;
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{
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volatile int *hej = &sc->uh_uba->uba_sr;
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if (*hej) {
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*hej = *hej;
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return 1;
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}
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return 0;
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}
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void
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uba_dw780int(uba)
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int uba;
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{
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int br, vec;
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struct uba_softc *sc = uba_cd.cd_devs[uba];
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struct uba_regs *ur = sc->uh_uba;
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br = mfpr(PR_IPL);
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vec = ur->uba_brrvr[br - 0x14];
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if (vec <= 0) {
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ubaerror(sc, &br, (int *)&vec);
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if (svec == 0)
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return;
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}
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if (cold)
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scb_fake(vec + sc->uh_ibase, br);
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else {
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struct ivec_dsp *ivec = &scb_vec[vec / 4];
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(*ivec->hoppaddr)(ivec->pushlarg);
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}
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}
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void
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dw780_init(sc)
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struct uba_softc *sc;
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{
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sc->uh_uba->uba_cr = UBACR_ADINIT;
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sc->uh_uba->uba_cr = UBACR_IFS|UBACR_BRIE|UBACR_USEFIE|UBACR_SUEFIE;
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while ((sc->uh_uba->uba_cnfgr & UBACNFGR_UBIC) == 0)
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;
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}
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void
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dw780_purge(sc, bdp)
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struct uba_softc *sc;
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int bdp;
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{
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sc->uh_uba->uba_dpr[bdp] |= UBADPR_BNE;
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}
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int ubawedgecnt = 10;
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int ubacrazy = 500;
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int zvcnt_max = 5000; /* in 8 sec */
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int ubaerrcnt;
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/*
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* This routine is called by the locore code to process a UBA
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* error on an 11/780 or 8600. The arguments are passed
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* on the stack, and value-result (through some trickery).
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* In particular, the uvec argument is used for further
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* uba processing so the result aspect of it is very important.
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* It must not be declared register.
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*/
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/*ARGSUSED*/
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void
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ubaerror(uh, ipl, uvec)
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register struct uba_softc *uh;
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int *ipl, *uvec;
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{
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struct uba_regs *uba = uh->uh_uba;
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register int sr, s;
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char sbuf[256], sbuf2[256];
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if (*uvec == 0) {
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/*
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* Declare dt as unsigned so that negative values
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* are handled as >8 below, in case time was set back.
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*/
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u_long dt = time.tv_sec - uh->uh_zvtime;
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uh->uh_zvtotal++;
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if (dt > 8) {
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uh->uh_zvtime = time.tv_sec;
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uh->uh_zvcnt = 0;
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}
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if (++uh->uh_zvcnt > zvcnt_max) {
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printf("%s: too many zero vectors (%d in <%d sec)\n",
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uh->uh_dev.dv_xname, uh->uh_zvcnt, (int)dt + 1);
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bitmask_snprintf(uba->uba_cnfgr&(~0xff), UBACNFGR_BITS,
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sbuf, sizeof(sbuf));
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printf("\tIPL 0x%x\n\tcnfgr: %s Adapter Code: 0x%x\n",
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*ipl, sbuf, uba->uba_cnfgr&0xff);
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bitmask_snprintf(uba->uba_sr, ubasr_bits, sbuf, sizeof(sbuf));
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printf("\tsr: %s\n\tdcr: %x (MIC %sOK)\n",
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sbuf, uba->uba_dcr,
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(uba->uba_dcr&0x8000000)?"":"NOT ");
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ubareset(uh->uh_dev.dv_unit);
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}
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return;
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}
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if (uba->uba_cnfgr & NEX_CFGFLT) {
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bitmask_snprintf(uba->uba_sr, ubasr_bits, sbuf, sizeof(sbuf));
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bitmask_snprintf(uba->uba_cnfgr, NEXFLT_BITS, sbuf2, sizeof(sbuf2));
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printf("%s: sbi fault sr=%s cnfgr=%s\n",
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uh->uh_dev.dv_xname, sbuf, sbuf2);
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ubareset(uh->uh_dev.dv_unit);
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*uvec = 0;
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return;
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}
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sr = uba->uba_sr;
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s = spluba();
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bitmask_snprintf(uba->uba_sr, ubasr_bits, sbuf, sizeof(sbuf));
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printf("%s: uba error sr=%s fmer=%x fubar=%o\n", uh->uh_dev.dv_xname,
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sbuf, uba->uba_fmer, 4*uba->uba_fubar);
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splx(s);
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uba->uba_sr = sr;
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*uvec &= UBABRRVR_DIV;
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if (++ubaerrcnt % ubawedgecnt == 0) {
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if (ubaerrcnt > ubacrazy)
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panic("uba crazy");
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printf("ERROR LIMIT ");
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ubareset(uh->uh_dev.dv_unit);
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*uvec = 0;
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return;
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}
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return;
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}
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#endif
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#ifdef DW750
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/*
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* The DW780 and DW750 are quite similar to their function from
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* a programmers point of view. Differencies are number of BDP's
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* and bus status/command registers, the latter are (partly) IPR's
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* on 750.
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*/
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void dw750_attach __P((struct device *, struct device *, void *));
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void dw750_init __P((struct uba_softc *));
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void dw750_purge __P((struct uba_softc *, int));
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struct cfattach uba_cmi_ca = {
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sizeof(struct uba_softc), dw_match, dw750_attach
|
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};
|
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void
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dw750_attach(parent, self, aux)
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struct device *parent, *self;
|
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void *aux;
|
||||
{
|
||||
struct uba_softc *sc = (void *)self;
|
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struct sbi_attach_args *sa = aux;
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int ubaddr = sa->nexinfo & 1;
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printf(": DW750\n");
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/*
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* Fill in bus specific data.
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*/
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sc->uh_uba = (void *)sa->nexaddr;
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sc->uh_nbdp = NBDP750;
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sc->uh_nr = sa->nexnum;
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sc->uh_ubapurge = dw750_purge;
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sc->uh_ubainit = dw750_init;
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sc->uh_type = DW750;
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sc->uh_memsize = UBAPAGES;
|
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sc->uh_mr = sc->uh_uba->uba_map;
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uba_attach(sc, UMEM750(ubaddr) + (UBAPAGES * VAX_NBPG));
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}
|
||||
|
||||
void
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||||
dw750_init(sc)
|
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struct uba_softc *sc;
|
||||
{
|
||||
mtpr(0, PR_IUR);
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DELAY(500000);
|
||||
}
|
||||
|
||||
void
|
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dw750_purge(sc, bdp)
|
||||
struct uba_softc *sc;
|
||||
int bdp;
|
||||
{
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||||
sc->uh_uba->uba_dpr[bdp] |= UBADPR_PURGE | UBADPR_NXM | UBADPR_UCE;
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||||
}
|
||||
#endif
|
||||
|
||||
#ifdef QBA
|
||||
/*
|
||||
* The Q22 bus is the main IO bus on MicroVAX II/MicroVAX III systems.
|
||||
* It has an address space of 4MB (22 address bits), therefore the name,
|
||||
* and is hardware compatible with all 16 and 18 bits Q-bus devices.
|
||||
* This driver can only handle map registers up to 1MB due to map info
|
||||
* storage, but that should be enough for normal purposes.
|
||||
*/
|
||||
int qba_match __P((struct device *, struct cfdata *, void *));
|
||||
void qba_attach __P((struct device *, struct device *, void *));
|
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void qba_beforescan __P((struct uba_softc*));
|
||||
void qba_init __P((struct uba_softc*));
|
||||
|
||||
struct cfattach uba_mainbus_ca = {
|
||||
sizeof(struct uba_softc), qba_match, qba_attach
|
||||
};
|
||||
|
||||
int
|
||||
qba_match(parent, vcf, aux)
|
||||
struct device *parent;
|
||||
struct cfdata *vcf;
|
||||
void *aux;
|
||||
{
|
||||
struct bp_conf *bp = aux;
|
||||
|
||||
if (strcmp(bp->type, "uba"))
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return 0;
|
||||
|
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return 1;
|
||||
}
|
||||
|
||||
void
|
||||
qba_attach(parent, self, aux)
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||||
struct device *parent, *self;
|
||||
void *aux;
|
||||
{
|
||||
struct uba_softc *sc = (void *)self;
|
||||
|
||||
printf(": Q22\n");
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||||
/*
|
||||
* Fill in bus specific data.
|
||||
*/
|
||||
/* sc->uh_uba not used; no regs */
|
||||
/* sc->uh_nbdp is 0; Qbus has no BDP's */
|
||||
/* sc->uh_nr is 0; there can be only one! */
|
||||
/* sc->uh_afterscan; not used */
|
||||
/* sc->uh_errchk; not used */
|
||||
sc->uh_beforescan = qba_beforescan;
|
||||
sc->uh_ubainit = qba_init;
|
||||
sc->uh_type = QBA;
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sc->uh_memsize = QBAPAGES;
|
||||
/*
|
||||
* Map in the UBA page map into kernel space. On other UBAs,
|
||||
* the map registers are in the bus IO space.
|
||||
*/
|
||||
sc->uh_mr = (void *)vax_map_physmem(QBAMAP,
|
||||
(QBAPAGES * sizeof(struct pte)) / VAX_NBPG);
|
||||
|
||||
uba_attach(sc, QIOPAGE);
|
||||
}
|
||||
|
||||
/*
|
||||
* Called when the QBA is set up; to enable DMA access from
|
||||
* QBA devices to main memory.
|
||||
*/
|
||||
void
|
||||
qba_beforescan(sc)
|
||||
struct uba_softc *sc;
|
||||
{
|
||||
*((u_short *)(sc->uh_iopage + QIPCR)) = Q_LMEAE;
|
||||
}
|
||||
|
||||
void
|
||||
qba_init(sc)
|
||||
struct uba_softc *sc;
|
||||
{
|
||||
mtpr(0, PR_IUR);
|
||||
DELAY(500000);
|
||||
qba_beforescan(sc);
|
||||
}
|
||||
#endif
|
||||
#ifdef DW730
|
||||
struct cfattach uba_dw730_ca = {
|
||||
sizeof(struct uba_softc), dw730_match, dw730_attach
|
||||
};
|
||||
#endif
|
||||
#if 0
|
||||
/*
|
||||
* Stray interrupt vector handler, used when nowhere else to go to.
|
||||
*/
|
||||
void
|
||||
ubastray(arg)
|
||||
int arg;
|
||||
{
|
||||
struct callsframe *cf = FRAMEOFFSET(arg);
|
||||
struct uba_softc *sc = uba_cd.cd_devs[arg];
|
||||
int vector;
|
||||
|
||||
rbr = mfpr(PR_IPL);
|
||||
#ifdef DW780
|
||||
if (sc->uh_type == DW780)
|
||||
vector = svec >> 2;
|
||||
else
|
||||
#endif
|
||||
vector = (cf->ca_pc - (unsigned)&sc->uh_idsp[0]) >> 4;
|
||||
|
||||
if (cold) {
|
||||
#ifdef DW780
|
||||
if (sc->uh_type != DW780)
|
||||
#endif
|
||||
rcvec = vector;
|
||||
} else
|
||||
printf("uba%d: unexpected interrupt, vector 0x%x, br 0x%x\n",
|
||||
arg, svec, rbr);
|
||||
}
|
||||
#endif
|
||||
/*
|
||||
* Do transfer on device argument. The controller
|
||||
* and uba involved are implied by the device.
|
||||
* We queue for resource wait in the uba code if necessary.
|
||||
* We return 1 if the transfer was started, 0 if it was not.
|
||||
*
|
||||
* The onq argument must be zero iff the device is not on the
|
||||
* queue for this UBA. If onq is set, the device must be at the
|
||||
* head of the queue. In any case, if the transfer is started,
|
||||
* the device will be off the queue, and if not, it will be on.
|
||||
*
|
||||
* Drivers that allocate one BDP and hold it for some time should
|
||||
* set ud_keepbdp. In this case um_bdp tells which BDP is allocated
|
||||
* to the controller, unless it is zero, indicating that the controller
|
||||
* does not now have a BDP.
|
||||
*/
|
||||
int
|
||||
ubaqueue(uu, bp)
|
||||
register struct uba_unit *uu;
|
||||
struct buf *bp;
|
||||
{
|
||||
register struct uba_softc *uh;
|
||||
register int s;
|
||||
|
||||
uh = (void *)((struct device *)(uu->uu_softc))->dv_parent;
|
||||
s = spluba();
|
||||
/*
|
||||
* Honor exclusive BDP use requests.
|
||||
*/
|
||||
if ((uu->uu_xclu && uh->uh_users > 0) || uh->uh_xclu)
|
||||
goto rwait;
|
||||
if (uu->uu_keepbdp) {
|
||||
/*
|
||||
* First get just a BDP (though in fact it comes with
|
||||
* one map register too).
|
||||
*/
|
||||
if (uu->uu_bdp == 0) {
|
||||
uu->uu_bdp = uballoc(uh, (caddr_t)0, 0,
|
||||
UBA_NEEDBDP|UBA_CANTWAIT);
|
||||
if (uu->uu_bdp == 0)
|
||||
goto rwait;
|
||||
}
|
||||
/* now share it with this transfer */
|
||||
uu->uu_ubinfo = ubasetup(uh, bp,
|
||||
uu->uu_bdp|UBA_HAVEBDP|UBA_CANTWAIT);
|
||||
} else
|
||||
uu->uu_ubinfo = ubasetup(uh, bp, UBA_NEEDBDP|UBA_CANTWAIT);
|
||||
if (uu->uu_ubinfo == 0)
|
||||
goto rwait;
|
||||
uh->uh_users++;
|
||||
if (uu->uu_xclu)
|
||||
uh->uh_xclu = 1;
|
||||
|
||||
splx(s);
|
||||
return (1);
|
||||
|
||||
rwait:
|
||||
SIMPLEQ_INSERT_TAIL(&uh->uh_resq, uu, uu_resq);
|
||||
splx(s);
|
||||
return (0);
|
||||
}
|
||||
|
||||
void
|
||||
ubadone(uu)
|
||||
struct uba_unit *uu;
|
||||
{
|
||||
struct uba_softc *uh = (void *)((struct device *)
|
||||
(uu->uu_softc))->dv_parent;
|
||||
|
||||
if (uu->uu_xclu)
|
||||
uh->uh_xclu = 0;
|
||||
uh->uh_users--;
|
||||
if (uu->uu_keepbdp)
|
||||
uu->uu_ubinfo &= ~BDPMASK; /* keep BDP for misers */
|
||||
ubarelse(uh, &uu->uu_ubinfo);
|
||||
}
|
||||
|
||||
/*
|
||||
* Allocate and setup UBA map registers, and bdp's
|
||||
* Flags says whether bdp is needed, whether the caller can't
|
||||
* wait (e.g. if the caller is at interrupt level).
|
||||
* Return value encodes map register plus page offset,
|
||||
* bdp number and number of map registers.
|
||||
*/
|
||||
int
|
||||
ubasetup(uh, bp, flags)
|
||||
struct uba_softc *uh;
|
||||
struct buf *bp;
|
||||
int flags;
|
||||
{
|
||||
int npf;
|
||||
int temp;
|
||||
int reg, bdp;
|
||||
int a, o, ubinfo;
|
||||
|
||||
if (uh->uh_nbdp == 0)
|
||||
flags &= ~UBA_NEEDBDP;
|
||||
|
||||
o = (int)bp->b_data & VAX_PGOFSET;
|
||||
npf = vax_btoc(bp->b_bcount + o) + 1;
|
||||
if (npf > UBA_MAXNMR)
|
||||
panic("uba xfer too big");
|
||||
a = spluba();
|
||||
while ((reg = rmalloc(uh->uh_map, (long)npf)) == 0) {
|
||||
if (flags & UBA_CANTWAIT) {
|
||||
splx(a);
|
||||
return (0);
|
||||
}
|
||||
uh->uh_mrwant++;
|
||||
(void) tsleep(&uh->uh_mrwant, PSWP, "ubamrwant", 0);
|
||||
}
|
||||
if ((flags & UBA_NEED16) && reg + npf > 128) {
|
||||
/*
|
||||
* Could hang around and try again (if we can ever succeed).
|
||||
* Won't help any current device...
|
||||
*/
|
||||
rmfree(uh->uh_map, (long)npf, (long)reg);
|
||||
splx(a);
|
||||
return (0);
|
||||
}
|
||||
bdp = 0;
|
||||
if (flags & UBA_NEEDBDP) {
|
||||
while ((bdp = ffs((long)uh->uh_bdpfree)) == 0) {
|
||||
if (flags & UBA_CANTWAIT) {
|
||||
rmfree(uh->uh_map, (long)npf, (long)reg);
|
||||
splx(a);
|
||||
return (0);
|
||||
}
|
||||
uh->uh_bdpwant++;
|
||||
(void) tsleep(&uh->uh_bdpwant, PSWP, "ubabdpwant", 0);
|
||||
}
|
||||
uh->uh_bdpfree &= ~(1 << (bdp-1));
|
||||
} else if (flags & UBA_HAVEBDP)
|
||||
bdp = (flags >> 28) & 0xf;
|
||||
splx(a);
|
||||
reg--;
|
||||
ubinfo = UBAI_INFO(o, reg, npf, bdp);
|
||||
temp = (bdp << 21) | UBAMR_MRV;
|
||||
if (bdp && (o & 01))
|
||||
temp |= UBAMR_BO;
|
||||
|
||||
disk_reallymapin(bp, uh->uh_mr, reg, temp | PG_V);
|
||||
|
||||
return (ubinfo);
|
||||
}
|
||||
|
||||
/*
|
||||
* Non buffer setup interface... set up a buffer and call ubasetup.
|
||||
*/
|
||||
int
|
||||
uballoc(uh, addr, bcnt, flags)
|
||||
struct uba_softc *uh;
|
||||
caddr_t addr;
|
||||
int bcnt, flags;
|
||||
{
|
||||
struct buf ubabuf;
|
||||
|
||||
ubabuf.b_data = addr;
|
||||
ubabuf.b_flags = B_BUSY;
|
||||
ubabuf.b_bcount = bcnt;
|
||||
/* that's all the fields ubasetup() needs */
|
||||
return (ubasetup(uh, &ubabuf, flags));
|
||||
}
|
||||
|
||||
/*
|
||||
* Release resources on uba uban, and then unblock resource waiters.
|
||||
* The map register parameter is by value since we need to block
|
||||
* against uba resets on 11/780's.
|
||||
*/
|
||||
void
|
||||
ubarelse(uh, amr)
|
||||
struct uba_softc *uh;
|
||||
int *amr;
|
||||
{
|
||||
struct uba_unit *uu;
|
||||
register int bdp, reg, npf, s;
|
||||
int mr;
|
||||
|
||||
/*
|
||||
* Carefully see if we should release the space, since
|
||||
* it may be released asynchronously at uba reset time.
|
||||
*/
|
||||
s = spluba();
|
||||
mr = *amr;
|
||||
if (mr == 0) {
|
||||
/*
|
||||
* A ubareset() occurred before we got around
|
||||
* to releasing the space... no need to bother.
|
||||
*/
|
||||
splx(s);
|
||||
return;
|
||||
}
|
||||
*amr = 0;
|
||||
bdp = UBAI_BDP(mr);
|
||||
if (bdp) {
|
||||
if (uh->uh_ubapurge)
|
||||
(*uh->uh_ubapurge)(uh, bdp);
|
||||
|
||||
uh->uh_bdpfree |= 1 << (bdp-1); /* atomic */
|
||||
if (uh->uh_bdpwant) {
|
||||
uh->uh_bdpwant = 0;
|
||||
wakeup((caddr_t)&uh->uh_bdpwant);
|
||||
}
|
||||
}
|
||||
/*
|
||||
* Put back the registers in the resource map.
|
||||
* The map code must not be reentered,
|
||||
* nor can the registers be freed twice.
|
||||
* Unblock interrupts once this is done.
|
||||
*/
|
||||
npf = UBAI_NMR(mr);
|
||||
reg = UBAI_MR(mr) + 1;
|
||||
rmfree(uh->uh_map, (long)npf, (long)reg);
|
||||
splx(s);
|
||||
|
||||
/*
|
||||
* Wakeup sleepers for map registers,
|
||||
* and also, if there are processes blocked in dgo(),
|
||||
* give them a chance at the UNIBUS.
|
||||
*/
|
||||
if (uh->uh_mrwant) {
|
||||
uh->uh_mrwant = 0;
|
||||
wakeup((caddr_t)&uh->uh_mrwant);
|
||||
}
|
||||
while ((uu = uh->uh_resq.sqh_first)) {
|
||||
SIMPLEQ_REMOVE_HEAD(&uh->uh_resq, uu, uu_resq);
|
||||
if ((*uu->uu_ready)(uu) == 0)
|
||||
break;
|
||||
}
|
||||
}
|
||||
|
||||
void
|
||||
ubainitmaps(uhp)
|
||||
register struct uba_softc *uhp;
|
||||
{
|
||||
|
||||
if (uhp->uh_memsize > UBA_MAXMR)
|
||||
uhp->uh_memsize = UBA_MAXMR;
|
||||
rminit(uhp->uh_map, (long)uhp->uh_memsize, (long)1, "uba", UAMSIZ);
|
||||
uhp->uh_bdpfree = (1 << uhp->uh_nbdp) - 1;
|
||||
}
|
||||
|
||||
/*
|
||||
* Generate a reset on uba number uban. Then
|
||||
* call each device that asked to be called during attach,
|
||||
* giving it a chance to clean up so as to be able to continue.
|
||||
*/
|
||||
void
|
||||
ubareset(uban)
|
||||
int uban;
|
||||
{
|
||||
register struct uba_softc *uh = uba_cd.cd_devs[uban];
|
||||
int s, i;
|
||||
|
||||
s = spluba();
|
||||
uh->uh_users = 0;
|
||||
uh->uh_zvcnt = 0;
|
||||
uh->uh_xclu = 0;
|
||||
SIMPLEQ_INIT(&uh->uh_resq);
|
||||
uh->uh_bdpwant = 0;
|
||||
uh->uh_mrwant = 0;
|
||||
ubainitmaps(uh);
|
||||
wakeup((caddr_t)&uh->uh_bdpwant);
|
||||
wakeup((caddr_t)&uh->uh_mrwant);
|
||||
printf("%s: reset", uh->uh_dev.dv_xname);
|
||||
(*uh->uh_ubainit)(uh);
|
||||
|
||||
for (i = 0; i < uh->uh_resno; i++)
|
||||
(*uh->uh_reset[i])(uh->uh_resarg[i]);
|
||||
printf("\n");
|
||||
splx(s);
|
||||
}
|
||||
|
||||
#ifdef notyet
|
||||
/*
|
||||
* Determine the interrupt priority of a Q-bus
|
||||
* peripheral. The device probe routine must spl6(),
|
||||
* attempt to make the device request an interrupt,
|
||||
* delaying as necessary, then call this routine
|
||||
* before resetting the device.
|
||||
*/
|
||||
int
|
||||
qbgetpri()
|
||||
{
|
||||
int pri;
|
||||
|
||||
for (pri = 0x17; pri > 0x14; ) {
|
||||
if (rcvec && rcvec != 0x200) /* interrupted at pri */
|
||||
break;
|
||||
pri--;
|
||||
splx(pri - 1);
|
||||
}
|
||||
spl0();
|
||||
return (pri);
|
||||
}
|
||||
#endif
|
||||
|
||||
/*
|
||||
* The common attach routines:
|
||||
* Allocates interrupt vectors.
|
||||
* Puts correct values in uba_softc.
|
||||
* Calls the scan routine to search for uba devices.
|
||||
*/
|
||||
void
|
||||
uba_attach(sc, iopagephys)
|
||||
struct uba_softc *sc;
|
||||
paddr_t iopagephys;
|
||||
{
|
||||
|
||||
/*
|
||||
* Set last free interrupt vector for devices with
|
||||
* programmable interrupt vectors. Use is to decrement
|
||||
* this number and use result as interrupt vector.
|
||||
*/
|
||||
sc->uh_lastiv = 0x200;
|
||||
SIMPLEQ_INIT(&sc->uh_resq);
|
||||
|
||||
/*
|
||||
* Allocate place for unibus memory in virtual space.
|
||||
*/
|
||||
sc->uh_iopage = (caddr_t)vax_map_physmem(iopagephys, UBAIOPAGES);
|
||||
if (sc->uh_iopage == 0)
|
||||
return; /* vax_map_physmem() will complain for us */
|
||||
/*
|
||||
* Initialize the UNIBUS, by freeing the map
|
||||
* registers and the buffered data path registers
|
||||
*/
|
||||
sc->uh_map = (struct map *)malloc((u_long)
|
||||
(UAMSIZ * sizeof(struct map)), M_DEVBUF, M_NOWAIT);
|
||||
bzero((caddr_t)sc->uh_map, (unsigned)(UAMSIZ * sizeof (struct map)));
|
||||
ubainitmaps(sc);
|
||||
|
||||
/*
|
||||
* Map the first page of UNIBUS i/o space to the first page of memory
|
||||
* for devices which will need to dma to produce an interrupt.
|
||||
*/
|
||||
*(int *)(&sc->uh_mr[0]) = UBAMR_MRV;
|
||||
|
||||
if (sc->uh_beforescan)
|
||||
(*sc->uh_beforescan)(sc);
|
||||
/*
|
||||
* Now start searching for devices.
|
||||
*/
|
||||
config_search(ubasearch,(struct device *)sc, NULL);
|
||||
|
||||
if (sc->uh_afterscan)
|
||||
(*sc->uh_afterscan)(sc);
|
||||
}
|
||||
|
||||
int
|
||||
ubasearch(parent, cf, aux)
|
||||
struct device *parent;
|
||||
struct cfdata *cf;
|
||||
void *aux;
|
||||
{
|
||||
struct uba_softc *sc = (struct uba_softc *)parent;
|
||||
struct uba_attach_args ua;
|
||||
int i, vec, br;
|
||||
|
||||
ua.ua_addr = (caddr_t)((int)sc->uh_iopage + ubdevreg(cf->cf_loc[0]));
|
||||
ua.ua_reset = NULL;
|
||||
|
||||
if (badaddr(ua.ua_addr, 2) || (sc->uh_errchk ? (*sc->uh_errchk)(sc):0))
|
||||
goto forgetit;
|
||||
|
||||
scb_vecref(0, 0); /* Clear vector ref */
|
||||
i = (*cf->cf_attach->ca_match) (parent, cf, &ua);
|
||||
|
||||
if (sc->uh_errchk)
|
||||
if ((*sc->uh_errchk)(sc))
|
||||
goto forgetit;
|
||||
if (i == 0)
|
||||
goto forgetit;
|
||||
|
||||
i = scb_vecref(&vec, &br);
|
||||
if (i == 0)
|
||||
goto fail;
|
||||
if (vec == 0)
|
||||
goto fail;
|
||||
|
||||
if (ua.ua_reset) { /* device wants ubareset */
|
||||
if (sc->uh_resno == 0) {
|
||||
sc->uh_reset = malloc(1024, M_DEVBUF, M_NOWAIT);
|
||||
sc->uh_resarg = (int *)sc->uh_reset + 128;
|
||||
}
|
||||
#ifdef DIAGNOSTIC
|
||||
if (sc->uh_resno > 127) {
|
||||
printf("%s: Expand reset table, skipping reset %s%d\n",
|
||||
sc->uh_dev.dv_xname, cf->cf_driver->cd_name,
|
||||
cf->cf_unit);
|
||||
} else
|
||||
#endif
|
||||
{
|
||||
sc->uh_resarg[sc->uh_resno] = cf->cf_unit;
|
||||
sc->uh_reset[sc->uh_resno++] = ua.ua_reset;
|
||||
}
|
||||
}
|
||||
ua.ua_br = br;
|
||||
ua.ua_cvec = vec;
|
||||
ua.ua_iaddr = cf->cf_loc[0];
|
||||
|
||||
config_attach(parent, cf, &ua, ubaprint);
|
||||
return 0;
|
||||
|
||||
fail:
|
||||
printf("%s%d at %s csr %o %s\n",
|
||||
cf->cf_driver->cd_name, cf->cf_unit, parent->dv_xname,
|
||||
cf->cf_loc[0], (i ? "zero vector" : "didn't interrupt"));
|
||||
|
||||
forgetit:
|
||||
return 0;
|
||||
}
|
||||
|
||||
/*
|
||||
* Print out some interesting info common to all unibus devices.
|
||||
*/
|
||||
int
|
||||
ubaprint(aux, uba)
|
||||
void *aux;
|
||||
const char *uba;
|
||||
{
|
||||
struct uba_attach_args *ua = aux;
|
||||
|
||||
printf(" csr %o vec %o ipl %x", ua->ua_iaddr,
|
||||
ua->ua_cvec & 511, ua->ua_br);
|
||||
return UNCONF;
|
||||
}
|
||||
|
|
@ -1,250 +0,0 @@
|
|||
/* $NetBSD: ubareg.h,v 1.11 2000/01/24 02:40:36 matt Exp $ */
|
||||
|
||||
/*-
|
||||
* Copyright (c) 1982, 1986 The Regents of the University of California.
|
||||
* All rights reserved.
|
||||
* (c) UNIX System Laboratories, Inc.
|
||||
* All or some portions of this file are derived from material licensed
|
||||
* to the University of California by American Telephone and Telegraph
|
||||
* Co. or Unix System Laboratories, Inc. and are reproduced herein with
|
||||
* the permission of UNIX System Laboratories, Inc.
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions
|
||||
* are met:
|
||||
* 1. Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in the
|
||||
* documentation and/or other materials provided with the distribution.
|
||||
* 3. All advertising materials mentioning features or use of this software
|
||||
* must display the following acknowledgement:
|
||||
* This product includes software developed by the University of
|
||||
* California, Berkeley and its contributors.
|
||||
* 4. Neither the name of the University nor the names of its contributors
|
||||
* may be used to endorse or promote products derived from this software
|
||||
* without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
|
||||
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
|
||||
* ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
|
||||
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
|
||||
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
|
||||
* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
|
||||
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
|
||||
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
|
||||
* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
|
||||
* SUCH DAMAGE.
|
||||
*
|
||||
* @(#)ubareg.h 7.8 (Berkeley) 5/9/91
|
||||
*/
|
||||
|
||||
/*
|
||||
* VAX UNIBUS adapter registers
|
||||
*/
|
||||
|
||||
/*
|
||||
* "UNIBUS" adaptor types.
|
||||
* This code is used for both UNIBUSes and Q-buses
|
||||
* with different types of adaptors.
|
||||
* Definition of a type includes support code for that type.
|
||||
*/
|
||||
|
||||
#ifdef _KERNEL
|
||||
#include "opt_vax8200.h"
|
||||
#include "opt_vax8600.h"
|
||||
#include "opt_vax780.h"
|
||||
#include "opt_vax750.h"
|
||||
#include "opt_vax730.h"
|
||||
#include "opt_vax630.h"
|
||||
#include "opt_vax650.h"
|
||||
#include "opt_vax660.h"
|
||||
#include "opt_vax670.h"
|
||||
#endif
|
||||
|
||||
#if VAX780 || VAX8600
|
||||
#define DW780 1 /* has adaptor regs, sr: 780/785/8600 */
|
||||
#else
|
||||
#undef DW780
|
||||
#endif
|
||||
|
||||
|
||||
#if VAX750
|
||||
#define DW750 2 /* has adaptor regs, no sr: 750, 730 */
|
||||
#endif
|
||||
|
||||
#if VAX730
|
||||
#define DW730 3 /* has adaptor regs, no sr: 750, 730 */
|
||||
#endif
|
||||
|
||||
#if VAX630 || VAX650 || VAX660 || VAX670
|
||||
#define QBA 4 /* 22-bit Q-bus, no adaptor regs: uVAX II */
|
||||
#endif
|
||||
|
||||
/*
|
||||
* Size of unibus memory address space in pages
|
||||
* (also number of map registers).
|
||||
* QBAPAGES should be 8192, but we don't need nearly that much
|
||||
* address space, and the return from the allocation routine
|
||||
* can accommodate at most 2047 (ubavar.h: UBA_MAXMR);
|
||||
* QBAPAGES must be at least UBAPAGES. Choose pragmatically.
|
||||
*
|
||||
* Is there ever any need to have QBAPAGES != UBAPAGES???
|
||||
* Wont work now anyway, QBAPAGES _must_ be .eq. UBAPAGES.
|
||||
*/
|
||||
#define UBAPAGES 496
|
||||
#define NUBMREG 496
|
||||
#define QBAPAGES 1024
|
||||
#define UBAIOADDR 0760000 /* start of I/O page */
|
||||
#define UBAIOPAGES 16
|
||||
|
||||
#ifndef _LOCORE
|
||||
/*
|
||||
* DW780/DW750 hardware registers
|
||||
*/
|
||||
struct uba_regs {
|
||||
int uba_cnfgr; /* configuration register */
|
||||
int uba_cr; /* control register */
|
||||
int uba_sr; /* status register */
|
||||
int uba_dcr; /* diagnostic control register */
|
||||
int uba_fmer; /* failed map entry register */
|
||||
int uba_fubar; /* failed UNIBUS address register */
|
||||
int pad1[2];
|
||||
int uba_brsvr[4];
|
||||
int uba_brrvr[4]; /* receive vector registers */
|
||||
int uba_dpr[16]; /* buffered data path register */
|
||||
int pad2[480];
|
||||
struct pte uba_map[UBAPAGES]; /* unibus map register */
|
||||
int pad3[UBAIOPAGES]; /* no maps for device address space */
|
||||
};
|
||||
#endif
|
||||
|
||||
#ifdef DW780
|
||||
/* uba_cnfgr */
|
||||
#define UBACNFGR_UBINIT 0x00040000 /* unibus init asserted */
|
||||
#define UBACNFGR_UBPDN 0x00020000 /* unibus power down */
|
||||
#define UBACNFGR_UBIC 0x00010000 /* unibus init complete */
|
||||
|
||||
#define UBACNFGR_BITS \
|
||||
"\40\40PARFLT\37WSQFLT\36URDFLT\35ISQFLT\34MXTFLT\33XMTFLT\30ADPDN\27ADPUP\23UBINIT\22UBPDN\21UBIC"
|
||||
|
||||
/* uba_cr */
|
||||
#define UBACR_MRD16 0x40000000 /* map reg disable bit 4 */
|
||||
#define UBACR_MRD8 0x20000000 /* map reg disable bit 3 */
|
||||
#define UBACR_MRD4 0x10000000 /* map reg disable bit 2 */
|
||||
#define UBACR_MRD2 0x08000000 /* map reg disable bit 1 */
|
||||
#define UBACR_MRD1 0x04000000 /* map reg disable bit 0 */
|
||||
#define UBACR_IFS 0x00000040 /* interrupt field switch */
|
||||
#define UBACR_BRIE 0x00000020 /* BR interrupt enable */
|
||||
#define UBACR_USEFIE 0x00000010 /* UNIBUS to SBI error field IE */
|
||||
#define UBACR_SUEFIE 0x00000008 /* SBI to UNIBUS error field IE */
|
||||
#define UBACR_CNFIE 0x00000004 /* configuration IE */
|
||||
#define UBACR_UPF 0x00000002 /* UNIBUS power fail */
|
||||
#define UBACR_ADINIT 0x00000001 /* adapter init */
|
||||
|
||||
/* uba_sr */
|
||||
#define UBASR_BR7FULL 0x08000000 /* BR7 receive vector reg full */
|
||||
#define UBASR_BR6FULL 0x04000000 /* BR6 receive vector reg full */
|
||||
#define UBASR_BR5FULL 0x02000000 /* BR5 receive vector reg full */
|
||||
#define UBASR_BR4FULL 0x01000000 /* BR4 receive vector reg full */
|
||||
#define UBASR_RDTO 0x00000400 /* UNIBUS to SBI read data timeout */
|
||||
#define UBASR_RDS 0x00000200 /* read data substitute */
|
||||
#define UBASR_CRD 0x00000100 /* corrected read data */
|
||||
#define UBASR_CXTER 0x00000080 /* command transmit error */
|
||||
#define UBASR_CXTMO 0x00000040 /* command transmit timeout */
|
||||
#define UBASR_DPPE 0x00000020 /* data path parity error */
|
||||
#define UBASR_IVMR 0x00000010 /* invalid map register */
|
||||
#define UBASR_MRPF 0x00000008 /* map register parity failure */
|
||||
#define UBASR_LEB 0x00000004 /* lost error */
|
||||
#define UBASR_UBSTO 0x00000002 /* UNIBUS select timeout */
|
||||
#define UBASR_UBSSYNTO 0x00000001 /* UNIBUS slave sync timeout */
|
||||
|
||||
#define UBASR_BITS \
|
||||
"\20\13RDTO\12RDS\11CRD\10CXTER\7CXTMO\6DPPE\5IVMR\4MRPF\3LEB\2UBSTO\1UBSSYNTO"
|
||||
|
||||
/* uba_brrvr[] */
|
||||
#define UBABRRVR_AIRI 0x80000000 /* adapter interrupt request */
|
||||
#define UBABRRVR_DIV 0x0000ffff /* device interrupt vector field */
|
||||
#endif
|
||||
|
||||
/* uba_dpr */
|
||||
#ifdef DW780
|
||||
#define UBADPR_BNE 0x80000000 /* buffer not empty - purge */
|
||||
#define UBADPR_BTE 0x40000000 /* buffer transfer error */
|
||||
#define UBADPR_DPF 0x20000000 /* DP function (RO) */
|
||||
#define UBADPR_BS 0x007f0000 /* buffer state field */
|
||||
#define UBADPR_BUBA 0x0000ffff /* buffered UNIBUS address */
|
||||
#endif
|
||||
#ifdef DW750
|
||||
#define UBADPR_ERROR 0x80000000 /* error occurred */
|
||||
#define UBADPR_NXM 0x40000000 /* nxm from memory */
|
||||
#define UBADPR_UCE 0x20000000 /* uncorrectable error */
|
||||
#define UBADPR_PURGE 0x00000001 /* purge bdp */
|
||||
#endif
|
||||
|
||||
/* uba_mr[] */
|
||||
#define UBAMR_MRV 0x80000000 /* map register valid */
|
||||
#define UBAMR_BO 0x02000000 /* byte offset bit */
|
||||
#define UBAMR_DPDB 0x01e00000 /* data path designator field */
|
||||
#define UBAMR_SBIPFN 0x001fffff /* SBI page address field */
|
||||
|
||||
#define UBAMR_DPSHIFT 21 /* shift to data path designator */
|
||||
|
||||
/*
|
||||
* Number of unibus buffered data paths and possible uba's per cpu type.
|
||||
*/
|
||||
#define NBDP8600 15
|
||||
#define NBDP780 15
|
||||
#define NBDPBUA 5
|
||||
#define NBDP750 3
|
||||
#define NBDP730 0
|
||||
#define MAXNBDP 15
|
||||
|
||||
/*
|
||||
* Symbolic BUS addresses for UBAs.
|
||||
*/
|
||||
|
||||
#if VAX630 || VAX650
|
||||
#define QBAMAP 0x20088000
|
||||
#define QMEM 0x30000000
|
||||
#define QIOPAGE 0x20000000
|
||||
/*
|
||||
* Q-bus control registers
|
||||
*/
|
||||
#define QIPCR 0x1f40 /* from start of iopage */
|
||||
/* bits in QIPCR */
|
||||
#define Q_DBIRQ 0x0001 /* doorbell interrupt request */
|
||||
#define Q_LMEAE 0x0020 /* local mem external access enable */
|
||||
#define Q_DBIIE 0x0040 /* doorbell interrupt enable */
|
||||
#define Q_AUXHLT 0x0100 /* auxiliary processor halt */
|
||||
#define Q_DMAQPE 0x8000 /* Q22 bus address space parity error */
|
||||
#endif
|
||||
|
||||
#if VAX730
|
||||
#define UMEM730 0xfc0000
|
||||
#endif
|
||||
|
||||
#if VAX750
|
||||
#define UMEM750(i) (0xfc0000-(i)*0x40000)
|
||||
#endif
|
||||
|
||||
#if VAX780
|
||||
#define UMEM780(i) (0x20100000+(i)*0x40000)
|
||||
#endif
|
||||
|
||||
#if VAX8200 /* BEWARE, argument is node, not ubanum */
|
||||
#define UMEM8200(i) (0x20400000+(i)*0x40000)
|
||||
#endif
|
||||
|
||||
#if VAX8600 || VAX780
|
||||
#define UMEMA8600(i) (0x20100000+(i)*0x40000)
|
||||
#define UMEMB8600(i) (0x22100000+(i)*0x40000)
|
||||
#endif
|
||||
|
||||
/*
|
||||
* Macro to offset a UNIBUS device address, often expressed as
|
||||
* something like 0172520, by forcing it into the last 8K
|
||||
* of UNIBUS memory space.
|
||||
*/
|
||||
#define ubdevreg(addr) ((addr) & 017777)
|
||||
Loading…
Reference in New Issue