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Updated bde's comments wrt. i387 control word settings so that they 

describe NetBSD, rather than 386BSD 0.1.
Removed 386BSD and BDE control word constants, since we don't need and
will never use them.  However, The iBCS control word constant is kept,
since we might want to use it in the iBCS binary compatibility code.
This commit is contained in:
jtc 1994-09-22 00:37:13 +00:00
parent 97fc5017d9
commit 62db8972b1
1 changed files with 12 additions and 30 deletions
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42
sys/arch/i386/include/npx.h
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@ -34,7 +34,7 @@
* SUCH DAMAGE. * SUCH DAMAGE.
* *
* from: @(#)npx.h 5.3 (Berkeley) 1/18/91 * from: @(#)npx.h 5.3 (Berkeley) 1/18/91
* $Id: npx.h,v 1.9 1994/01/25 19:58:30 jtc Exp $ * $Id: npx.h,v 1.10 1994/09/22 00:37:13 jtc Exp $
*/ */
/* /*
@ -89,49 +89,31 @@ struct emcsts {
/* Intel prefers long real (53 bit) precision */ /* Intel prefers long real (53 bit) precision */
#define __iBCS_NPXCW__ 0x262 #define __iBCS_NPXCW__ 0x262
/* wfj prefers temporary real (64 bit) precision */
#define __386BSD_NPXCW__ 0x362
/* */
#define __NetBSD_NPXCW__ 0x127f #define __NetBSD_NPXCW__ 0x127f
/* /*
* bde prefers 53 bit precision and all exceptions masked.
*
* The standard control word from finit is 0x37F, giving: * The standard control word from finit is 0x37F, giving:
*
* round to nearest * round to nearest
* 64-bit precision * 64-bit precision
* all exceptions masked. * all exceptions masked.
* *
* Now I want: * Now we want:
* * affine mode (if we decide to support 287's)
* affine mode for 287's (if they work at all) (1 in bitfield 1<<12) * round to nearest
* 53-bit precision (2 in bitfield 3<<8) * 53-bit precision
* overflow exception unmasked (0 in bitfield 1<<3) * all exceptions masked.
* zero divide exception unmasked (0 in bitfield 1<<2)
* invalid-operand exception unmasked (0 in bitfield 1<<0).
* *
* 64-bit precision often gives bad results with high level languages * 64-bit precision often gives bad results with high level languages
* because it makes the results of calculations depend on whether * because it makes the results of calculations depend on whether
* intermediate values are stored in memory or in FPU registers. * intermediate values are stored in memory or in FPU registers.
* *
* The "Intel" and wfj control words have: * The iBCS control word has underflow, overflow, zero divide, and invalid
* * operation exceptions unmasked. But that causes an unexpected exception
* underflow exception unmasked (0 in bitfield 1<<4) * in the test program 'paranoia' and makes denormals useless (DBL_MIN / 2
* * underflows). It doesn't make a lot of sense to trap underflow without
* but that causes an unexpected exception in the test program 'paranoia' * trapping denormals.
* and makes denormals useless (DBL_MIN / 2 underflows). It doesn't make
* a lot of sense to trap underflow without trapping denormals.
*
* Later I will want the IEEE default of all exceptions masked. See the
* 0.0 math manpage for why this is better. The 0.1 math manpage is empty.
*/ */
#define __BDE_NPXCW__ 0x1272
#define __BETTER_BDE_NPXCW__ 0x127f
#ifdef __NetBSD__
#define __INITIAL_NPXCW__ __NetBSD_NPXCW__ #define __INITIAL_NPXCW__ __NetBSD_NPXCW__
#else
#define __INITIAL_NPXCW__ __iBCS_NPXCW__
#endif
#endif /* !_I386_NPX_H_ */ #endif /* !_I386_NPX_H_ */