Introduce separate ic_* fields for instruction caches.
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@ -1,4 +1,4 @@
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/* $NetBSD: cache.h,v 1.7 1996/05/16 15:57:10 abrown Exp $ */
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/* $NetBSD: cache.h,v 1.8 1996/06/12 14:47:45 pk Exp $ */
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/*
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/*
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* Copyright (c) 1996
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* Copyright (c) 1996
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@ -170,14 +170,19 @@ void cache_flush __P((caddr_t, u_int)); /* flush region */
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*/
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*/
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struct cacheinfo {
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struct cacheinfo {
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int c_totalsize; /* total size, in bytes */
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int c_totalsize; /* total size, in bytes */
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/* if split, MAX(icache,dcache) */
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int c_enabled; /* true => cache is enabled */
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int c_enabled; /* true => cache is enabled */
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int c_hwflush; /* true => have hardware flush */
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int c_hwflush; /* true => have hardware flush */
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int c_linesize; /* line size, in bytes */
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int c_linesize; /* line size, in bytes */
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int c_l2linesize; /* log2(linesize) */
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int c_l2linesize; /* log2(linesize) */
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int c_physical; /* true => cache is physical */
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int c_physical; /* true => cache is physical */
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int c_split; /* true => cache is split */
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int c_split; /* true => cache is split */
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int dc_totalsize; /* if split, data cache info */
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int ic_totalsize; /* instruction cache */
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int dc_enabled; /* note: instr cache in c_* */
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int ic_enabled;
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int ic_linesize;
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int ic_l2linesize;
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int dc_totalsize; /* data cache */
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int dc_enabled;
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int dc_linesize;
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int dc_linesize;
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int dc_l2linesize;
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int dc_l2linesize;
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int ec_totalsize; /* external cache info */
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int ec_totalsize; /* external cache info */
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