From 625d05a4ac6806279c372d0a2b4349d4e31376ca Mon Sep 17 00:00:00 2001 From: chris Date: Thu, 10 Oct 2002 23:19:13 +0000 Subject: [PATCH] Fix thinko from this morning, delay is reentrant, so resetting the timer to 0 on entry will confuse any already running delay. --- sys/arch/arm/footbridge/footbridge_clock.c | 19 ++++++++++++------- 1 file changed, 12 insertions(+), 7 deletions(-) diff --git a/sys/arch/arm/footbridge/footbridge_clock.c b/sys/arch/arm/footbridge/footbridge_clock.c index d41c6f0a1d0c..16ec6381968f 100644 --- a/sys/arch/arm/footbridge/footbridge_clock.c +++ b/sys/arch/arm/footbridge/footbridge_clock.c @@ -1,4 +1,4 @@ -/* $NetBSD: footbridge_clock.c,v 1.12 2002/10/10 10:12:27 chris Exp $ */ +/* $NetBSD: footbridge_clock.c,v 1.13 2002/10/10 23:19:13 chris Exp $ */ /* * Copyright (c) 1997 Mark Brinicombe. @@ -427,12 +427,13 @@ delay(n) } return; } - last = delay_clock_count; - - /* reset timer */ - bus_space_write_4(clock_sc->sc_iot, clock_sc->sc_ioh, - TIMER_3_CLEAR, 0); + /* + * read the current value (do not reset it as delay is reentrant) + */ + last = bus_space_read_4(clock_sc->sc_iot, clock_sc->sc_ioh, + TIMER_3_VALUE); + delta = usecs = 0; while (n > usecs) @@ -447,7 +448,11 @@ delay(n) if (cur == 0) { - /* reset the timer */ + /* + * reset the timer, note that if something blocks us for more + * than 1/100s we may delay for too long, but I believe that + * is fairly unlikely. + */ bus_space_write_4(clock_sc->sc_iot, clock_sc->sc_ioh, TIMER_3_CLEAR, 0); }