Aren/NetBSD
1
0
Fork 0
Code Issues Pull Requests Packages Projects Releases Wiki Activity

Sanitize names a bit, still could use more namespace cleanup

Browse Source
This commit is contained in:
martin 2010-12-11 14:28:38 +00:00
parent 3670e11cda
commit 6251718992
2 changed files with 15 additions and 15 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

10
sys/dev/pci/if_bnx.c
View File

@ -1,4 +1,4 @@
/* $NetBSD: if_bnx.c,v 1.38 2010/12/11 14:19:29 pgoyette Exp $ */
/* $NetBSD: if_bnx.c,v 1.39 2010/12/11 14:28:38 martin Exp $ */
/* $OpenBSD: if_bnx.c,v 1.85 2009/11/09 14:32:41 dlg Exp $ */
/*-
@ -35,7 +35,7 @@
#if 0
__FBSDID("$FreeBSD: src/sys/dev/bce/if_bce.c,v 1.3 2006/04/13 14:12:26 ru Exp $");
#endif
__KERNEL_RCSID(0, "$NetBSD: if_bnx.c,v 1.38 2010/12/11 14:19:29 pgoyette Exp $");
__KERNEL_RCSID(0, "$NetBSD: if_bnx.c,v 1.39 2010/12/11 14:28:38 martin Exp $");
/*
* The following controllers are supported by this driver:
@ -3105,12 +3105,12 @@ bnx_init_context(struct bnx_softc *sc)
vcid_addr = GET_CID_ADDR(96);
while (vcid_addr) {
vcid_addr -= PHY_BNX_CTX_SIZE;
vcid_addr -= BNX_PHY_CTX_SIZE;
REG_WR(sc, BNX_CTX_VIRT_ADDR, 0);
REG_WR(sc, BNX_CTX_PAGE_TBL, vcid_addr);
for(offset = 0; offset < PHY_BNX_CTX_SIZE; offset += 4) {
for(offset = 0; offset < BNX_PHY_CTX_SIZE; offset += 4) {
CTX_WR(sc, 0x00, offset, 0);
}
@ -3411,7 +3411,7 @@ bnx_chipinit(struct bnx_softc *sc)
REG_WR(sc, BNX_MQ_CONFIG, val);
val = 0x10000 + (MAX_CID_CNT * MB_KERNEL_BNX_CTX_SIZE);
val = 0x10000 + (MAX_CID_CNT * BNX_MB_KERNEL_CTX_SIZE);
REG_WR(sc, BNX_MQ_KNL_BYP_WIND_START, val);
REG_WR(sc, BNX_MQ_KNL_WIND_END, val);

20
sys/dev/pci/if_bnxreg.h
View File

@ -1,4 +1,4 @@
/* $NetBSD: if_bnxreg.h,v 1.12 2010/12/11 12:14:06 martin Exp $ */
/* $NetBSD: if_bnxreg.h,v 1.13 2010/12/11 14:28:38 martin Exp $ */
/* $OpenBSD: if_bnxreg.h,v 1.33 2009/09/05 16:02:28 claudio Exp $ */
/*-
@ -4590,16 +4590,16 @@ struct l2_fhdr {
#define GET_CID_ADDR(_cid) ((_cid) << BNX_CTX_SHIFT)
#define GET_CID(_cid_addr) ((_cid_addr) >> BNX_CTX_SHIFT)
#define PHY_BNX_CTX_SHIFT 6
#define PHY_BNX_CTX_SIZE (1 << PHY_BNX_CTX_SHIFT)
#define PHY_BNX_CTX_MASK (PHY_BNX_CTX_SIZE - 1)
#define BNX_PHY_CTX_SHIFT 6
#define BNX_PHY_CTX_SIZE (1 << BNX_PHY_CTX_SHIFT)
#define BNX_PHY_CTX_MASK (BNX_PHY_CTX_SIZE - 1)
#define GET_PCID_ADDR(_pcid) ((_pcid) << PHY_BNX_CTX_SHIFT)
#define GET_PCID(_pcid_addr) ((_pcid_addr) >> PHY_BNX_CTX_SHIFT)
#define MB_KERNEL_BNX_CTX_SHIFT 8
#define MB_KERNEL_BNX_CTX_SIZE (1 << MB_KERNEL_BNX_CTX_SHIFT)
#define MB_KERNEL_BNX_CTX_MASK (MB_KERNEL_BNX_CTX_SIZE - 1)
#define MB_GET_CID_ADDR(_cid) (0x10000 + ((_cid) << MB_KERNEL_BNX_CTX_SHIFT))
#define BNX_MB_KERNEL_CTX_SHIFT 8
#define BNX_MB_KERNEL_CTX_SIZE (1 << BNX_MB_KERNEL_CTX_SHIFT)
#define BNX_MB_KERNEL_CTX_MASK (BNX_MB_KERNEL_CTX_SIZE - 1)
#define BNX_MB_GET_CID_ADDR(_cid) (0x10000 + ((_cid) << BNX_MB_KERNEL_CTX_SHIFT))
#define MAX_CID_CNT 0x4000
#define MAX_CID_ADDR (GET_CID_ADDR(MAX_CID_CNT))
@ -4608,8 +4608,8 @@ struct l2_fhdr {
#define TX_CID 16
#define RX_CID 0
#define MB_TX_CID_ADDR MB_GET_CID_ADDR(TX_CID)
#define MB_RX_CID_ADDR MB_GET_CID_ADDR(RX_CID)
#define MB_TX_CID_ADDR BNX_MB_GET_CID_ADDR(TX_CID)
#define MB_RX_CID_ADDR BNX_MB_GET_CID_ADDR(RX_CID)
/****************************************************************************/
/* BNX Processor Firmwware Load Definitions */