Expose a bunch of CPU details, including implementation version and
architecture extensions, via sysctl: hw.cpu0.model = 21264A-0 (EV67) hw.cpu0.major = 11 hw.cpu0.minor = 0 hw.cpu0.implver = 2 hw.cpu0.amask = 0x1307 hw.cpu0.bwx = 1 hw.cpu0.fix = 1 hw.cpu0.cix = 1 hw.cpu0.mvi = 1 hw.cpu0.pat = 1 hw.cpu0.pmi = 1 hw.cpu0.vax_fp = 1 hw.cpu0.ieee_fp = 1 hw.cpu0.primary_eligible = 1 hw.cpu0.primary = 1 hw.cpu0.cpu_id = 0 hw.cpu0.pcc_freq = 239990688 as well as some potentially interesting system-level variables: machdep.cctr = 0 machdep.is_qemu = 1 Should address the basic concern in PR port-alpha/15835.
This commit is contained in:
thorpej
parent
6f43686d40
commit
6214e4cc92
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@ -1,7 +1,7 @@
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/* $NetBSD: cpu.c,v 1.102 2020/10/10 03:05:04 thorpej Exp $ */
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/* $NetBSD: cpu.c,v 1.103 2020/10/15 01:00:01 thorpej Exp $ */
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/*-
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* Copyright (c) 1998, 1999, 2000, 2001 The NetBSD Foundation, Inc.
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* Copyright (c) 1998, 1999, 2000, 2001, 2020 The NetBSD Foundation, Inc.
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* All rights reserved.
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*
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* This code is derived from software contributed to The NetBSD Foundation
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@ -59,7 +59,7 @@
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#include <sys/cdefs.h> /* RCS ID & Copyright macro defns */
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__KERNEL_RCSID(0, "$NetBSD: cpu.c,v 1.102 2020/10/10 03:05:04 thorpej Exp $");
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__KERNEL_RCSID(0, "$NetBSD: cpu.c,v 1.103 2020/10/15 01:00:01 thorpej Exp $");
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#include "opt_ddb.h"
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#include "opt_multiprocessor.h"
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@ -71,6 +71,7 @@ __KERNEL_RCSID(0, "$NetBSD: cpu.c,v 1.102 2020/10/10 03:05:04 thorpej Exp $");
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#include <sys/proc.h>
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#include <sys/atomic.h>
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#include <sys/cpu.h>
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#include <sys/sysctl.h>
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#include <uvm/uvm_extern.h>
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@ -147,33 +148,151 @@ static const char * const lcaminor[] = {
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"",
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"21066", "21066",
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"21068", "21068",
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"21066A", "21068A", 0
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"21066A", "21068A",
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NULL
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};
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const struct cputable_struct {
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int cpu_major_code;
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const char *cpu_evname;
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const char *cpu_major_name;
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const char * const *cpu_minor_names;
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} cpunametable[] = {
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{ PCS_PROC_EV3, "EV3", NULL },
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{ PCS_PROC_EV4, "21064", NULL },
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{ PCS_PROC_SIMULATION, "Sim", NULL },
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{ PCS_PROC_LCA4, "LCA", lcaminor },
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{ PCS_PROC_EV5, "21164", NULL },
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{ PCS_PROC_EV45, "21064A", NULL },
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{ PCS_PROC_EV56, "21164A", NULL },
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{ PCS_PROC_EV6, "21264", NULL },
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{ PCS_PROC_PCA56, "PCA56", NULL },
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{ PCS_PROC_PCA57, "PCA57", NULL },
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{ PCS_PROC_EV67, "21264A", NULL },
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{ PCS_PROC_EV68CB, "21264C", NULL },
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{ PCS_PROC_EV68AL, "21264B", NULL },
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{ PCS_PROC_EV68CX, "21264D", NULL },
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{ PCS_PROC_EV7, "21364", NULL },
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{ PCS_PROC_EV79, "EV79", NULL },
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{ PCS_PROC_EV69, "EV69", NULL },
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[PCS_PROC_EV3] ={ "EV3", NULL, NULL },
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[PCS_PROC_EV4] ={ "EV4", "21064", NULL },
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[PCS_PROC_SIMULATION]={ "Sim", NULL, NULL },
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[PCS_PROC_LCA4] ={ "LCA4", NULL, lcaminor },
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[PCS_PROC_EV5] ={ "EV5", "21164", NULL },
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[PCS_PROC_EV45] ={ "EV45", "21064A", NULL },
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[PCS_PROC_EV56] ={ "EV56", "21164A", NULL },
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[PCS_PROC_EV6] ={ "EV6", "21264", NULL },
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[PCS_PROC_PCA56] ={ "PCA56", "21164PC", NULL },
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[PCS_PROC_PCA57] ={ "PCA57", "21164PC"/*XXX*/,NULL },
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[PCS_PROC_EV67] ={ "EV67", "21264A", NULL },
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[PCS_PROC_EV68CB] ={ "EV68CB", "21264C", NULL },
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[PCS_PROC_EV68AL] ={ "EV68AL", "21264B", NULL },
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[PCS_PROC_EV68CX] ={ "EV68CX", "21264D", NULL },
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[PCS_PROC_EV7] ={ "EV7", "21364", NULL },
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[PCS_PROC_EV79] ={ "EV79", NULL, NULL },
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[PCS_PROC_EV69] ={ "EV69", NULL, NULL },
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};
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static bool
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cpu_description(const struct cpu_softc * const sc,
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char * const buf, size_t const buflen)
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{
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const char * const *s;
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const char *ev;
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int i;
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const uint32_t major = sc->sc_major_type;
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const uint32_t minor = sc->sc_minor_type;
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if (major < __arraycount(cpunametable) &&
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(ev = cpunametable[major].cpu_evname) != NULL) {
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s = cpunametable[major].cpu_minor_names;
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for (i = 0; s != NULL && s[i] != NULL; i++) {
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if (i == minor && strlen(s[i]) != 0) {
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break;
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}
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}
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if (s == NULL || s[i] == NULL) {
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s = &cpunametable[major].cpu_major_name;
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i = 0;
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if (s[i] == NULL) {
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s = NULL;
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}
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}
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/*
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* Example strings:
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*
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* Sim-0
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* 21068-3 (LCA4) [uses minor table]
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* 21264C-5 (EV68CB)
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* 21164PC-1 (PCA56)
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*/
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if (s != NULL) {
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snprintf(buf, buflen, "%s-%d (%s)", s[i], minor, ev);
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} else {
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snprintf(buf, buflen, "%s-%d", ev, minor);
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}
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return true;
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}
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snprintf(buf, buflen, "UNKNOWN CPU TYPE (%u:%u)", major, minor);
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return false;
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}
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static int
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cpu_sysctl_model(SYSCTLFN_ARGS)
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{
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struct sysctlnode node = *rnode;
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const struct cpu_softc * const sc = node.sysctl_data;
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char model[32];
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cpu_description(sc, model, sizeof(model));
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node.sysctl_data = model;
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return sysctl_lookup(SYSCTLFN_CALL(&node));
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}
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static int
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cpu_sysctl_amask_bit(SYSCTLFN_ARGS, unsigned long const bit)
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{
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struct sysctlnode node = *rnode;
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const struct cpu_softc * const sc = node.sysctl_data;
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bool result = (sc->sc_amask & bit) ? true : false;
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node.sysctl_data = &result;
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return sysctl_lookup(SYSCTLFN_CALL(&node));
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}
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static int
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cpu_sysctl_bwx(SYSCTLFN_ARGS)
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{
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return cpu_sysctl_amask_bit(SYSCTLFN_CALL(rnode), ALPHA_AMASK_BWX);
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}
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static int
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cpu_sysctl_fix(SYSCTLFN_ARGS)
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{
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return cpu_sysctl_amask_bit(SYSCTLFN_CALL(rnode), ALPHA_AMASK_FIX);
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}
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static int
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cpu_sysctl_cix(SYSCTLFN_ARGS)
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{
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return cpu_sysctl_amask_bit(SYSCTLFN_CALL(rnode), ALPHA_AMASK_CIX);
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}
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static int
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cpu_sysctl_mvi(SYSCTLFN_ARGS)
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{
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return cpu_sysctl_amask_bit(SYSCTLFN_CALL(rnode), ALPHA_AMASK_MVI);
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}
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static int
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cpu_sysctl_pat(SYSCTLFN_ARGS)
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{
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return cpu_sysctl_amask_bit(SYSCTLFN_CALL(rnode), ALPHA_AMASK_PAT);
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}
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static int
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cpu_sysctl_pmi(SYSCTLFN_ARGS)
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{
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return cpu_sysctl_amask_bit(SYSCTLFN_CALL(rnode), ALPHA_AMASK_PMI);
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}
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static int
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cpu_sysctl_primary(SYSCTLFN_ARGS)
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{
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struct sysctlnode node = *rnode;
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const struct cpu_softc * const sc = node.sysctl_data;
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bool result = CPU_IS_PRIMARY(sc->sc_ci);
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node.sysctl_data = &result;
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return sysctl_lookup(SYSCTLFN_CALL(&node));
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}
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/*
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* The following is an attempt to map out how booting secondary CPUs
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* works.
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@ -219,43 +338,30 @@ static void
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cpuattach(device_t parent, device_t self, void *aux)
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{
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struct cpu_softc * const sc = device_private(self);
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struct mainbus_attach_args *ma = aux;
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int i;
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const char * const *s;
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struct pcs *p;
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uint32_t major, minor;
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const struct mainbus_attach_args * const ma = aux;
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struct cpu_info *ci;
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char model[32];
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const bool primary = ma->ma_slot == hwrpb->rpb_primary_cpu_id;
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sc->sc_dev = self;
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p = LOCATE_PCS(hwrpb, ma->ma_slot);
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major = PCS_CPU_MAJORTYPE(p);
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minor = PCS_CPU_MINORTYPE(p);
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const struct pcs * const p = LOCATE_PCS(hwrpb, ma->ma_slot);
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sc->sc_major_type = PCS_CPU_MAJORTYPE(p);
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sc->sc_minor_type = PCS_CPU_MINORTYPE(p);
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aprint_normal(": ID %d%s, ", ma->ma_slot,
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ma->ma_slot == hwrpb->rpb_primary_cpu_id ? " (primary)" : "");
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const bool recognized = cpu_description(sc, model, sizeof(model));
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for(i = 0; i < __arraycount(cpunametable); ++i) {
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if (cpunametable[i].cpu_major_code == major) {
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aprint_normal("%s-%d",
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cpunametable[i].cpu_major_name, minor);
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s = cpunametable[i].cpu_minor_names;
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for(i = 0; s && s[i]; ++i) {
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if (i == minor && strlen(s[i]) != 0) {
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aprint_normal(" (%s)", s[i]);
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goto recognized;
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}
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}
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goto recognized;
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}
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aprint_normal(": ID %d%s, ", ma->ma_slot, primary ? " (primary)" : "");
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if (recognized) {
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aprint_normal("%s", model);
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} else {
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aprint_error("%s", model);
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}
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aprint_error("UNKNOWN CPU TYPE (%d:%d)", major, minor);
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recognized:
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aprint_naive("\n");
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aprint_normal("\n");
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#ifdef DEBUG
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if (p->pcs_proc_var != 0) {
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bool needcomma = false;
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const char *vaxfp = "";
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@ -263,16 +369,19 @@ recognized:
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const char *pe = "";
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if (p->pcs_proc_var & PCS_VAR_VAXFP) {
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sc->sc_vax_fp = true;
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vaxfp = "VAX FP support";
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needcomma = true;
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}
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if (p->pcs_proc_var & PCS_VAR_IEEEFP) {
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sc->sc_ieee_fp = true;
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ieeefp = ", IEEE FP support";
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if (!needcomma)
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ieeefp += 2;
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needcomma = true;
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}
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if (p->pcs_proc_var & PCS_VAR_PE) {
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sc->sc_primary_eligible = true;
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pe = ", Primary Eligible";
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if (!needcomma)
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pe += 2;
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@ -285,19 +394,18 @@ recognized:
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p->pcs_proc_var & PCS_VAR_RESERVED);
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aprint_debug("\n");
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}
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#endif
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if (ma->ma_slot > ALPHA_WHAMI_MAXID) {
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if (ma->ma_slot == hwrpb->rpb_primary_cpu_id)
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if (primary)
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panic("cpu_attach: primary CPU ID too large");
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aprint_error_dev(sc->sc_dev,
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"processor ID too large, ignoring\n");
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return;
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}
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if (ma->ma_slot == hwrpb->rpb_primary_cpu_id)
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if (primary) {
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ci = &cpu_info_primary;
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else {
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} else {
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/*
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* kmem_zalloc() will guarante cache line alignment for
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* all allocations >= CACHE_LINE_SIZE.
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@ -312,19 +420,14 @@ recognized:
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ci->ci_softc = sc;
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ci->ci_pcc_freq = hwrpb->rpb_cc_freq;
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/*
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* Though we could (should?) attach the LCA cpus' PCI
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* bus here there is no good reason to do so, and
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* the bus attachment code is easier to understand
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* and more compact if done the 'normal' way.
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*/
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sc->sc_ci = ci;
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#if defined(MULTIPROCESSOR)
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/*
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* Make sure the processor is available for use.
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*/
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if ((p->pcs_flags & PCS_PA) == 0) {
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if (ma->ma_slot == hwrpb->rpb_primary_cpu_id)
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if (primary)
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panic("cpu_attach: primary not available?!");
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aprint_normal_dev(sc->sc_dev,
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"processor not available for use\n");
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@ -333,7 +436,7 @@ recognized:
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/* Make sure the processor has valid PALcode. */
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if ((p->pcs_flags & PCS_PV) == 0) {
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if (ma->ma_slot == hwrpb->rpb_primary_cpu_id)
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if (primary)
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panic("cpu_attach: primary has invalid PALcode?!");
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aprint_error_dev(sc->sc_dev, "PALcode not valid\n");
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return;
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@ -344,7 +447,7 @@ recognized:
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* If we're the primary CPU, no more work to do; we're already
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* running!
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*/
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if (ma->ma_slot == hwrpb->rpb_primary_cpu_id) {
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if (primary) {
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cpu_announce_extensions(ci);
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#if defined(MULTIPROCESSOR)
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ci->ci_flags |= CPUF_PRIMARY|CPUF_RUNNING;
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@ -387,6 +490,154 @@ recognized:
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#if defined(MULTIPROCESSOR)
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alpha_ipi_init(ci);
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#endif
|
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struct sysctllog **log = &sc->sc_sysctllog;
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const struct sysctlnode *rnode, *cnode;
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int error;
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error = sysctl_createv(log, 0, NULL, &rnode, CTLFLAG_PERMANENT,
|
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CTLTYPE_NODE, device_xname(sc->sc_dev),
|
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SYSCTL_DESCR("cpu properties"),
|
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NULL, 0,
|
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NULL, 0, CTL_HW, CTL_CREATE, CTL_EOL);
|
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if (error)
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return;
|
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|
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error = sysctl_createv(log, 0, &rnode, &cnode,
|
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CTLFLAG_PERMANENT, CTLTYPE_STRING, "model",
|
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SYSCTL_DESCR("cpu model"),
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cpu_sysctl_model, 0,
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(void *)sc, 0, CTL_CREATE, CTL_EOL);
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if (error)
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return;
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error = sysctl_createv(log, 0, &rnode, &cnode,
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CTLFLAG_PERMANENT, CTLTYPE_INT, "major",
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SYSCTL_DESCR("cpu major type"),
|
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NULL, 0,
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&sc->sc_major_type, 0, CTL_CREATE, CTL_EOL);
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if (error)
|
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return;
|
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error = sysctl_createv(log, 0, &rnode, &cnode,
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CTLFLAG_PERMANENT, CTLTYPE_INT, "minor",
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SYSCTL_DESCR("cpu minor type"),
|
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NULL, 0,
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&sc->sc_minor_type, 0, CTL_CREATE, CTL_EOL);
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if (error)
|
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return;
|
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error = sysctl_createv(log, 0, &rnode, &cnode,
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CTLFLAG_PERMANENT, CTLTYPE_LONG, "implver",
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SYSCTL_DESCR("cpu implementation version"),
|
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NULL, 0,
|
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&sc->sc_implver, 0, CTL_CREATE, CTL_EOL);
|
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if (error)
|
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return;
|
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|
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error = sysctl_createv(log, 0, &rnode, &cnode,
|
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CTLFLAG_PERMANENT|CTLFLAG_HEX, CTLTYPE_LONG, "amask",
|
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SYSCTL_DESCR("architecture extensions mask"),
|
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NULL, 0,
|
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&sc->sc_amask, 0, CTL_CREATE, CTL_EOL);
|
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if (error)
|
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return;
|
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|
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error = sysctl_createv(log, 0, &rnode, &cnode,
|
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CTLFLAG_PERMANENT, CTLTYPE_BOOL, "bwx",
|
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SYSCTL_DESCR("cpu supports BWX extension"),
|
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cpu_sysctl_bwx, 0,
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(void *)sc, 0, CTL_CREATE, CTL_EOL);
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if (error)
|
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return;
|
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|
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error = sysctl_createv(log, 0, &rnode, &cnode,
|
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CTLFLAG_PERMANENT, CTLTYPE_BOOL, "fix",
|
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SYSCTL_DESCR("cpu supports FIX extension"),
|
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cpu_sysctl_fix, 0,
|
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(void *)sc, 0, CTL_CREATE, CTL_EOL);
|
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if (error)
|
||||
return;
|
||||
|
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error = sysctl_createv(log, 0, &rnode, &cnode,
|
||||
CTLFLAG_PERMANENT, CTLTYPE_BOOL, "cix",
|
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SYSCTL_DESCR("cpu supports CIX extension"),
|
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cpu_sysctl_cix, 0,
|
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(void *)sc, 0, CTL_CREATE, CTL_EOL);
|
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if (error)
|
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return;
|
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|
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error = sysctl_createv(log, 0, &rnode, &cnode,
|
||||
CTLFLAG_PERMANENT, CTLTYPE_BOOL, "mvi",
|
||||
SYSCTL_DESCR("cpu supports MVI extension"),
|
||||
cpu_sysctl_mvi, 0,
|
||||
(void *)sc, 0, CTL_CREATE, CTL_EOL);
|
||||
if (error)
|
||||
return;
|
||||
|
||||
error = sysctl_createv(log, 0, &rnode, &cnode,
|
||||
CTLFLAG_PERMANENT, CTLTYPE_BOOL, "pat",
|
||||
SYSCTL_DESCR("cpu supports PAT extension"),
|
||||
cpu_sysctl_pat, 0,
|
||||
(void *)sc, 0, CTL_CREATE, CTL_EOL);
|
||||
if (error)
|
||||
return;
|
||||
|
||||
error = sysctl_createv(log, 0, &rnode, &cnode,
|
||||
CTLFLAG_PERMANENT, CTLTYPE_BOOL, "pmi",
|
||||
SYSCTL_DESCR("cpu supports PMI extension"),
|
||||
cpu_sysctl_pmi, 0,
|
||||
(void *)sc, 0, CTL_CREATE, CTL_EOL);
|
||||
if (error)
|
||||
return;
|
||||
|
||||
error = sysctl_createv(log, 0, &rnode, &cnode,
|
||||
CTLFLAG_PERMANENT, CTLTYPE_BOOL, "vax_fp",
|
||||
SYSCTL_DESCR("cpu supports VAX FP"),
|
||||
NULL, 0,
|
||||
&sc->sc_vax_fp, 0, CTL_CREATE, CTL_EOL);
|
||||
if (error)
|
||||
return;
|
||||
|
||||
error = sysctl_createv(log, 0, &rnode, &cnode,
|
||||
CTLFLAG_PERMANENT, CTLTYPE_BOOL, "ieee_fp",
|
||||
SYSCTL_DESCR("cpu supports IEEE FP"),
|
||||
NULL, 0,
|
||||
&sc->sc_ieee_fp, 0, CTL_CREATE, CTL_EOL);
|
||||
if (error)
|
||||
return;
|
||||
|
||||
error = sysctl_createv(log, 0, &rnode, &cnode,
|
||||
CTLFLAG_PERMANENT, CTLTYPE_BOOL, "primary_eligible",
|
||||
SYSCTL_DESCR("cpu is primary-eligible"),
|
||||
NULL, 0,
|
||||
&sc->sc_primary_eligible, 0, CTL_CREATE, CTL_EOL);
|
||||
if (error)
|
||||
return;
|
||||
|
||||
error = sysctl_createv(log, 0, &rnode, &cnode,
|
||||
CTLFLAG_PERMANENT, CTLTYPE_BOOL, "primary",
|
||||
SYSCTL_DESCR("cpu is the primary cpu"),
|
||||
cpu_sysctl_primary, 0,
|
||||
(void *)sc, 0, CTL_CREATE, CTL_EOL);
|
||||
if (error)
|
||||
return;
|
||||
|
||||
error = sysctl_createv(log, 0, &rnode, &cnode,
|
||||
CTLFLAG_PERMANENT, CTLTYPE_LONG, "cpu_id",
|
||||
SYSCTL_DESCR("hardware cpu ID"),
|
||||
NULL, 0,
|
||||
&sc->sc_ci->ci_cpuid, 0, CTL_CREATE, CTL_EOL);
|
||||
if (error)
|
||||
return;
|
||||
|
||||
error = sysctl_createv(log, 0, &rnode, &cnode,
|
||||
CTLFLAG_PERMANENT, CTLTYPE_LONG, "pcc_freq",
|
||||
SYSCTL_DESCR("PCC frequency"),
|
||||
NULL, 0,
|
||||
&sc->sc_ci->ci_pcc_freq, 0, CTL_CREATE, CTL_EOL);
|
||||
if (error)
|
||||
return;
|
||||
}
|
||||
|
||||
static void
|
||||
|
|
@ -399,6 +650,9 @@ cpu_announce_extensions(struct cpu_info *ci)
|
|||
if (implver >= ALPHA_IMPLVER_EV5)
|
||||
amask = (~alpha_amask(ALPHA_AMASK_ALL)) & ALPHA_AMASK_ALL;
|
||||
|
||||
ci->ci_softc->sc_implver = implver;
|
||||
ci->ci_softc->sc_amask = amask;
|
||||
|
||||
if (ci->ci_cpuid == hwrpb->rpb_primary_cpu_id) {
|
||||
cpu_implver = implver;
|
||||
cpu_amask = amask;
|
||||
|
|
@ -417,7 +671,7 @@ cpu_announce_extensions(struct cpu_info *ci)
|
|||
|
||||
if (amask) {
|
||||
snprintb(bits, sizeof(bits),
|
||||
ALPHA_AMASK_BITS, cpu_amask);
|
||||
ALPHA_AMASK_BITS, amask);
|
||||
aprint_normal_dev(ci->ci_softc->sc_dev,
|
||||
"Architecture extensions: %s\n", bits);
|
||||
}
|
||||
|
|
|
|||
|
|
@ -1,4 +1,4 @@
|
|||
/* $NetBSD: machdep.c,v 1.368 2020/10/14 00:59:50 thorpej Exp $ */
|
||||
/* $NetBSD: machdep.c,v 1.369 2020/10/15 01:00:01 thorpej Exp $ */
|
||||
|
||||
/*-
|
||||
* Copyright (c) 1998, 1999, 2000, 2019, 2020 The NetBSD Foundation, Inc.
|
||||
|
|
@ -67,7 +67,7 @@
|
|||
|
||||
#include <sys/cdefs.h> /* RCS ID & Copyright macro defns */
|
||||
|
||||
__KERNEL_RCSID(0, "$NetBSD: machdep.c,v 1.368 2020/10/14 00:59:50 thorpej Exp $");
|
||||
__KERNEL_RCSID(0, "$NetBSD: machdep.c,v 1.369 2020/10/15 01:00:01 thorpej Exp $");
|
||||
|
||||
#include <sys/param.h>
|
||||
#include <sys/systm.h>
|
||||
|
|
@ -1628,6 +1628,16 @@ SYSCTL_SETUP(sysctl_machdep_setup, "sysctl machdep subtree setup")
|
|||
CTLTYPE_INT, "fp_sync_complete", NULL,
|
||||
NULL, 0, &alpha_fp_sync_complete, 0,
|
||||
CTL_MACHDEP, CPU_FP_SYNC_COMPLETE, CTL_EOL);
|
||||
sysctl_createv(clog, 0, NULL, NULL,
|
||||
CTLFLAG_PERMANENT,
|
||||
CTLTYPE_INT, "cctr", NULL,
|
||||
NULL, 0, &alpha_use_cctr, 0,
|
||||
CTL_MACHDEP, CPU_CCTR, CTL_EOL);
|
||||
sysctl_createv(clog, 0, NULL, NULL,
|
||||
CTLFLAG_PERMANENT,
|
||||
CTLTYPE_BOOL, "is_qemu", NULL,
|
||||
NULL, 0, &alpha_is_qemu, 0,
|
||||
CTL_MACHDEP, CPU_IS_QEMU, CTL_EOL);
|
||||
}
|
||||
|
||||
/*
|
||||
|
|
|
|||
|
|
@ -1,4 +1,4 @@
|
|||
/* $NetBSD: cpu.h,v 1.98 2020/09/29 01:33:00 thorpej Exp $ */
|
||||
/* $NetBSD: cpu.h,v 1.99 2020/10/15 01:00:01 thorpej Exp $ */
|
||||
|
||||
/*-
|
||||
* Copyright (c) 1998, 1999, 2000, 2001 The NetBSD Foundation, Inc.
|
||||
|
|
@ -229,6 +229,9 @@ void cpu_signotify(struct lwp *);
|
|||
#define CPU_UNALIGNED_SIGBUS 5 /* int: SIGBUS unaligned accesses */
|
||||
#define CPU_BOOTED_KERNEL 6 /* string: booted kernel name */
|
||||
#define CPU_FP_SYNC_COMPLETE 7 /* int: always fixup sync fp traps */
|
||||
#define CPU_CCTR 8 /* int: using CC timecounter */
|
||||
#define CPU_IS_QEMU 9 /* int: running under Qemu */
|
||||
|
||||
|
||||
#ifdef _KERNEL
|
||||
|
||||
|
|
|
|||
|
|
@ -1,4 +1,4 @@
|
|||
/* $NetBSD: cpuvar.h,v 1.5 2011/06/14 15:34:22 matt Exp $ */
|
||||
/* $NetBSD: cpuvar.h,v 1.6 2020/10/15 01:00:01 thorpej Exp $ */
|
||||
|
||||
/*-
|
||||
* Copyright (c) 2000 The NetBSD Foundation, Inc.
|
||||
|
|
@ -33,6 +33,21 @@
|
|||
|
||||
struct cpu_softc {
|
||||
device_t sc_dev; /* base device */
|
||||
struct cpu_info *sc_ci; /* our cpu_info structure */
|
||||
|
||||
/* Info exported to user-space. */
|
||||
uint32_t sc_major_type; /* CPU major type */
|
||||
uint32_t sc_minor_type; /* CPU minor type */
|
||||
bool sc_vax_fp; /* supports VAX FP */
|
||||
bool sc_ieee_fp; /* supports IEEE FP */
|
||||
bool sc_primary_eligible; /* CPU is primary eligible */
|
||||
|
||||
/* These are only valid if the CPU runs kernel code. */
|
||||
u_long sc_amask; /* AMASK bits (inverted) */
|
||||
u_long sc_implver; /* IMPLVER */
|
||||
|
||||
struct sysctllog *sc_sysctllog;
|
||||
|
||||
struct evcnt sc_evcnt_clock; /* clock interrupts */
|
||||
struct evcnt sc_evcnt_device; /* device interrupts */
|
||||
#if defined(MULTIPROCESSOR)
|
||||
|
|
|
|||
Loading…
Reference in New Issue